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Second attempt at correct encodings for Thumb2 bitfield instructions.

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llvm-svn: 119575
This commit is contained in:
Owen Anderson 2010-11-17 22:16:31 +00:00
parent 16aeabf0d5
commit ea6ac4cdff
2 changed files with 55 additions and 13 deletions
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57
lib/Target/ARM/ARMInstrThumb2.td
View File

@ -1989,27 +1989,54 @@ defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
IIC_iBITi, IIC_iBITr, IIC_iBITsi, IIC_iBITi, IIC_iBITr, IIC_iBITsi,
BinOpFrag<(and node:$LHS, (not node:$RHS))>>; BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
let Constraints = "$src = $dst" in class T2BitFI<dag oops, dag iops, InstrItinClass itin,
def t2BFC : T2I<(outs rGPR:$dst), (ins rGPR:$src, bf_inv_mask_imm:$imm), string opc, string asm, list<dag> pattern>
IIC_iUNAsi, "bfc", "\t$dst, $imm", : T2I<oops, iops, itin, opc, asm, pattern> {
[(set rGPR:$dst, (and rGPR:$src, bf_inv_mask_imm:$imm))]> { bits<4> Rd;
bits<5> msb;
bits<5> lsb;
let Inst{11-8} = Rd{3-0};
let Inst{4-0} = msb{4-0};
let Inst{14-12} = lsb{4-2};
let Inst{7-6} = lsb{1-0};
}
class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: T2BitFI<oops, iops, itin, opc, asm, pattern> {
bits<4> Rn;
let Inst{19-16} = Rn{3-0};
}
let Constraints = "$src = $Rd" in
def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
IIC_iUNAsi, "bfc", "\t$Rd, $imm",
[(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
let Inst{31-27} = 0b11110; let Inst{31-27} = 0b11110;
let Inst{25} = 1; let Inst{25} = 1;
let Inst{24-20} = 0b10110; let Inst{24-20} = 0b10110;
let Inst{19-16} = 0b1111; // Rn let Inst{19-16} = 0b1111; // Rn
let Inst{15} = 0; let Inst{15} = 0;
bits<10> imm;
let msb{4-0} = imm{9-5};
let lsb{4-0} = imm{4-0};
} }
def t2SBFX: T2I<(outs rGPR:$dst), (ins rGPR:$src, imm0_31:$lsb, imm0_31:$width), def t2SBFX: T2TwoRegBitFI<
IIC_iUNAsi, "sbfx", "\t$dst, $src, $lsb, $width", []> { (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm0_31_m1:$msb),
IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
let Inst{31-27} = 0b11110; let Inst{31-27} = 0b11110;
let Inst{25} = 1; let Inst{25} = 1;
let Inst{24-20} = 0b10100; let Inst{24-20} = 0b10100;
let Inst{15} = 0; let Inst{15} = 0;
} }
def t2UBFX: T2I<(outs rGPR:$dst), (ins rGPR:$src, imm0_31:$lsb, imm0_31:$width), def t2UBFX: T2TwoRegBitFI<
IIC_iUNAsi, "ubfx", "\t$dst, $src, $lsb, $width", []> { (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm0_31_m1:$msb),
IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
let Inst{31-27} = 0b11110; let Inst{31-27} = 0b11110;
let Inst{25} = 1; let Inst{25} = 1;
let Inst{24-20} = 0b11100; let Inst{24-20} = 0b11100;
@ -2017,16 +2044,20 @@ def t2UBFX: T2I<(outs rGPR:$dst), (ins rGPR:$src, imm0_31:$lsb, imm0_31:$width),
} }
// A8.6.18 BFI - Bitfield insert (Encoding T1) // A8.6.18 BFI - Bitfield insert (Encoding T1)
let Constraints = "$src = $dst" in let Constraints = "$src = $Rd" in
def t2BFI : T2I<(outs rGPR:$dst), def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
(ins rGPR:$src, rGPR:$val, bf_inv_mask_imm:$imm), (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
IIC_iBITi, "bfi", "\t$dst, $val, $imm", IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
[(set rGPR:$dst, (ARMbfi rGPR:$src, rGPR:$val, [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
bf_inv_mask_imm:$imm))]> { bf_inv_mask_imm:$imm))]> {
let Inst{31-27} = 0b11110; let Inst{31-27} = 0b11110;
let Inst{25} = 1; let Inst{25} = 1;
let Inst{24-20} = 0b10110; let Inst{24-20} = 0b10110;
let Inst{15} = 0; let Inst{15} = 0;
bits<10> imm;
let msb{4-0} = imm{9-5};
let lsb{4-0} = imm{4-0};
} }
defm t2ORN : T2I_bin_irs<0b0011, "orn", defm t2ORN : T2I_bin_irs<0b0011, "orn",

11
test/MC/ARM/thumb2.s
View File

@ -52,3 +52,14 @@
@ CHECK: rrx r0, r0 @ encoding: [0x30,0x00,0x4f,0xea] @ CHECK: rrx r0, r0 @ encoding: [0x30,0x00,0x4f,0xea]
rrx r0, r0 rrx r0, r0
@ CHECK: bfc r0, #4, #20 @ encoding: [0x17,0x10,0x6f,0xf3]
bfc r0, #4, #20
@ CHECK: bfc r0, #0, #23 @ encoding: [0x16,0x00,0x6f,0xf3]
bfc r0, #0, #23
@ CHECK: bfc r0, #12, #20 @ encoding: [0x1f,0x30,0x6f,0xf3]
bfc r0, #12, #20
@ CHECK: sbfx r0, r0, #7, #11 @ encoding: [0xca,0x10,0x40,0xf3]
sbfx r0, r0, #7, #11
@ CHECK: ubfx r0, r0, #7, #11 @ encoding: [0xca,0x10,0xc0,0xf3]
ubfx r0, r0, #7, #11