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[X86] Add TSXLDTRK instructions.

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Summary: For more details about these instructions, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference

Reviewers: craig.topper, RKSimon, LuoYuanke

Reviewed By: craig.topper

Subscribers: mgorny, hiraditya, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D77205
This commit is contained in:
WangTianQing 2020-04-09 13:15:42 +08:00 committed by Xiang1 Zhang
parent 12b4002a61
commit ea7b0ac6a4
12 changed files with 102 additions and 0 deletions
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10
include/llvm/IR/IntrinsicsX86.td
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@ -4938,3 +4938,13 @@ let TargetPrefix = "x86" in {
def int_x86_serialize : GCCBuiltin<"__builtin_ia32_serialize">,
Intrinsic<[], [], []>;
}
//===----------------------------------------------------------------------===//
// TSXLDTRK - TSX Suspend Load Address Tracking
let TargetPrefix = "x86" in {
def int_x86_xsusldtrk : GCCBuiltin<"__builtin_ia32_xsusldtrk">,
Intrinsic<[], [], []>;
def int_x86_xresldtrk : GCCBuiltin<"__builtin_ia32_xresldtrk">,
Intrinsic<[], [], []>;
}

1
lib/Support/Host.cpp
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@ -1478,6 +1478,7 @@ bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
Features["enqcmd"] = HasLeaf7 && ((ECX >> 29) & 1);
Features["serialize"] = HasLeaf7 && ((EDX >> 14) & 1);
Features["tsxldtrk"] = HasLeaf7 && ((EDX >> 16) & 1);
// There are two CPUID leafs which information associated with the pconfig
// instruction:
// EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th

2
lib/Target/X86/X86.td
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@ -275,6 +275,8 @@ def FeatureENQCMD : SubtargetFeature<"enqcmd", "HasENQCMD", "true",
"Has ENQCMD instructions">;
def FeatureSERIALIZE : SubtargetFeature<"serialize", "HasSERIALIZE", "true",
"Has serialize instruction">;
def FeatureTSXLDTRK : SubtargetFeature<"tsxldtrk", "HasTSXLDTRK", "true",
"Support TSXLDTRK instructions">;
// On some processors, instructions that implicitly take two memory operands are
// slow. In practice, this means that CALL, PUSH, and POP with memory operands
// should be avoided in favor of a MOV + register CALL/PUSH/POP.

11
lib/Target/X86/X86InstrInfo.td
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@ -956,6 +956,7 @@ def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
def HasPCONFIG : Predicate<"Subtarget->hasPCONFIG()">;
def HasENQCMD : Predicate<"Subtarget->hasENQCMD()">;
def HasSERIALIZE : Predicate<"Subtarget->hasSERIALIZE()">;
def HasTSXLDTRK : Predicate<"Subtarget->hasTSXLDTRK()">;
def Not64BitMode : Predicate<"!Subtarget->is64Bit()">,
AssemblerPredicate<(all_of (not Mode64Bit)), "Not 64-bit mode">;
def In64BitMode : Predicate<"Subtarget->is64Bit()">,
@ -2869,6 +2870,16 @@ def SERIALIZE : I<0x01, MRM_E8, (outs), (ins), "serialize",
[(int_x86_serialize)]>, PS,
Requires<[HasSERIALIZE]>;
//===----------------------------------------------------------------------===//
// TSXLDTRK - TSX Suspend Load Address Tracking
//
let Predicates = [HasTSXLDTRK] in {
def XSUSLDTRK : I<0x01, MRM_E8, (outs), (ins), "xsusldtrk",
[(int_x86_xsusldtrk)]>, XD;
def XRESLDTRK : I<0x01, MRM_E9, (outs), (ins), "xresldtrk",
[(int_x86_xresldtrk)]>, XD;
}
//===----------------------------------------------------------------------===//
// Pattern fragments to auto generate TBM instructions.
//===----------------------------------------------------------------------===//

4
lib/Target/X86/X86Subtarget.h
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@ -400,6 +400,9 @@ protected:
/// Processor supports SERIALIZE instruction
bool HasSERIALIZE = false;
/// Processor supports TSXLDTRK instruction
bool HasTSXLDTRK = false;
/// Processor has a single uop BEXTR implementation.
bool HasFastBEXTR = false;
@ -716,6 +719,7 @@ public:
bool hasINVPCID() const { return HasINVPCID; }
bool hasENQCMD() const { return HasENQCMD; }
bool hasSERIALIZE() const { return HasSERIALIZE; }
bool hasTSXLDTRK() const { return HasTSXLDTRK; }
bool useRetpolineIndirectCalls() const { return UseRetpolineIndirectCalls; }
bool useRetpolineIndirectBranches() const {
return UseRetpolineIndirectBranches;

32
test/CodeGen/X86/tsxldtrk-intrinsic.ll Normal file
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@ -0,0 +1,32 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+tsxldtrk | FileCheck %s --check-prefix=X64
; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+tsxldtrk | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mtriple=x86_64-linux-gnux32 -mattr=+tsxldtrk | FileCheck %s --check-prefix=X32
define void @test_tsxldtrk() {
; X64-LABEL: test_tsxldtrk:
; X64: # %bb.0: # %entry
; X64-NEXT: xsusldtrk
; X64-NEXT: xresldtrk
; X64-NEXT: retq
;
; X86-LABEL: test_tsxldtrk:
; X86: # %bb.0: # %entry
; X86-NEXT: xsusldtrk
; X86-NEXT: xresldtrk
; X86-NEXT: retl
;
; X32-LABEL: test_tsxldtrk:
; X32: # %bb.0: # %entry
; X32-NEXT: xsusldtrk
; X32-NEXT: xresldtrk
; X32-NEXT: retq
entry:
call void @llvm.x86.xsusldtrk()
call void @llvm.x86.xresldtrk()
ret void
}
declare void @llvm.x86.xsusldtrk()
declare void @llvm.x86.xresldtrk()

6
test/MC/Disassembler/X86/x86-16.txt
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@ -839,3 +839,9 @@
# CHECK: serialize
0x0f 0x01 0xe8
# CHECK: xsusldtrk
0xf2 0x0f 0x01 0xe8
# CHECK: xresldtrk
0xf2 0x0f 0x01 0xe9

6
test/MC/Disassembler/X86/x86-32.txt
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@ -946,3 +946,9 @@
# CHECK: serialize
0x0f 0x01 0xe8
# CHECK: xsusldtrk
0xf2 0x0f 0x01 0xe8
# CHECK: xresldtrk
0xf2 0x0f 0x01 0xe9

6
test/MC/Disassembler/X86/x86-64.txt
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@ -694,3 +694,9 @@
# CHECK: serialize
0x0f 0x01 0xe8
# CHECK: xsusldtrk
0xf2 0x0f 0x01 0xe8
# CHECK: xresldtrk
0xf2 0x0f 0x01 0xe9

8
test/MC/X86/x86-16.s
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@ -1033,3 +1033,11 @@ enqcmds (%edi), %edi
// CHECK: serialize
// CHECK: encoding: [0x0f,0x01,0xe8]
serialize
// CHECK: xsusldtrk
// CHECK: encoding: [0xf2,0x0f,0x01,0xe8]
xsusldtrk
// CHECK: xresldtrk
// CHECK: encoding: [0xf2,0x0f,0x01,0xe9]
xresldtrk

8
test/MC/X86/x86-32-coverage.s
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@ -10880,3 +10880,11 @@ enqcmds 8128(%bx,%di), %ax
// CHECK: serialize
// CHECK: encoding: [0x0f,0x01,0xe8]
serialize
// CHECK: xsusldtrk
// CHECK: encoding: [0xf2,0x0f,0x01,0xe8]
xsusldtrk
// CHECK: xresldtrk
// CHECK: encoding: [0xf2,0x0f,0x01,0xe9]
xresldtrk

8
test/MC/X86/x86-64.s
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@ -1881,3 +1881,11 @@ enqcmds 485498096, %rax
// CHECK: serialize
// CHECK: encoding: [0x0f,0x01,0xe8]
serialize
// CHECK: xsusldtrk
// CHECK: encoding: [0xf2,0x0f,0x01,0xe8]
xsusldtrk
// CHECK: xresldtrk
// CHECK: encoding: [0xf2,0x0f,0x01,0xe9]
xresldtrk