mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-21 12:02:58 +02:00
[AMDGPU][mc] Fix memory corruption uncovered by AddressSanitizer during coverage/smoke Gfx7/8 testing.
Coverage/smoke Gfx7/8 tests were committed r292922 but then reverted by r292974 due to AddressSanitizer failure, which is fixed by this patch. Tests to be re-committed soon. llvm-svn: 293338
This commit is contained in:
parent
cfa8ee39df
commit
ead6d1c1e8
@ -2373,8 +2373,6 @@ void AMDGPUAsmParser::cvtDS(MCInst &Inst, const OperandVector &Operands) {
|
||||
}
|
||||
|
||||
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOffset);
|
||||
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGDS);
|
||||
|
||||
if (!GDSOnly) {
|
||||
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGDS);
|
||||
}
|
||||
|
@ -335,12 +335,14 @@ unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI) {
|
||||
}
|
||||
|
||||
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo) {
|
||||
assert(OpNo <= Desc.NumOperands);
|
||||
unsigned OpType = Desc.OpInfo[OpNo].OperandType;
|
||||
return OpType >= AMDGPU::OPERAND_SRC_FIRST &&
|
||||
OpType <= AMDGPU::OPERAND_SRC_LAST;
|
||||
}
|
||||
|
||||
bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo) {
|
||||
assert(OpNo <= Desc.NumOperands);
|
||||
unsigned OpType = Desc.OpInfo[OpNo].OperandType;
|
||||
switch (OpType) {
|
||||
case AMDGPU::OPERAND_REG_IMM_FP32:
|
||||
@ -356,6 +358,7 @@ bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo) {
|
||||
}
|
||||
|
||||
bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo) {
|
||||
assert(OpNo <= Desc.NumOperands);
|
||||
unsigned OpType = Desc.OpInfo[OpNo].OperandType;
|
||||
return OpType >= AMDGPU::OPERAND_REG_INLINE_C_FIRST &&
|
||||
OpType <= AMDGPU::OPERAND_REG_INLINE_C_LAST;
|
||||
@ -399,6 +402,7 @@ unsigned getRegBitWidth(const MCRegisterClass &RC) {
|
||||
|
||||
unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
|
||||
unsigned OpNo) {
|
||||
assert(OpNo <= Desc.NumOperands);
|
||||
unsigned RCID = Desc.OpInfo[OpNo].RegClass;
|
||||
return getRegBitWidth(MRI->getRegClass(RCID)) / 8;
|
||||
}
|
||||
|
Loading…
Reference in New Issue
Block a user