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[AMDGPU][llvm-mc] Support of Trap Handler registers (TTMP0..11 and TBA/TMA)git status
Tests added along with implemented feature. Note that there is a small leftover of unecessary MI sheduling issue (more info in the review). CodeGen/AMDGPU/salu-to-valu.ll updated to fix the false regression. TODO: Support for TTMP quads, comma-separated syntax in "[]" and more. Differential Revision: http://reviews.llvm.org/D17825 llvm-svn: 266205
This commit is contained in:
Artem Tamazov
parent
9cd420ea3a
commit
ead8b434de
@ -384,17 +384,32 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
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FlatUsed = true;
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continue;
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case AMDGPU::TBA:
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case AMDGPU::TBA_LO:
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case AMDGPU::TBA_HI:
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case AMDGPU::TMA:
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case AMDGPU::TMA_LO:
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case AMDGPU::TMA_HI:
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llvm_unreachable("Trap Handler registers should not be used");
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continue;
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default:
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break;
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}
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if (AMDGPU::SReg_32RegClass.contains(reg)) {
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if (AMDGPU::TTMP_32RegClass.contains(reg)) {
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llvm_unreachable("Trap Handler registers should not be used");
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}
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isSGPR = true;
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width = 1;
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} else if (AMDGPU::VGPR_32RegClass.contains(reg)) {
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isSGPR = false;
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width = 1;
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} else if (AMDGPU::SReg_64RegClass.contains(reg)) {
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if (AMDGPU::TTMP_64RegClass.contains(reg)) {
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llvm_unreachable("Trap Handler registers should not be used");
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}
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isSGPR = true;
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width = 2;
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} else if (AMDGPU::VReg_64RegClass.contains(reg)) {
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@ -574,8 +574,10 @@ struct OptionalOperand {
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}
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static int getRegClass(bool IsVgpr, unsigned RegWidth) {
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if (IsVgpr) {
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enum RegisterKind { IS_VGPR, IS_SGPR, IS_TTMP };
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static int getRegClass(RegisterKind Is, unsigned RegWidth) {
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if (Is == IS_VGPR) {
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switch (RegWidth) {
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default: return -1;
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case 1: return AMDGPU::VGPR_32RegClassID;
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@ -585,16 +587,23 @@ static int getRegClass(bool IsVgpr, unsigned RegWidth) {
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case 8: return AMDGPU::VReg_256RegClassID;
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case 16: return AMDGPU::VReg_512RegClassID;
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}
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} else if (Is == IS_TTMP) {
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switch (RegWidth) {
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default: return -1;
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case 1: return AMDGPU::TTMP_32RegClassID;
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case 2: return AMDGPU::TTMP_64RegClassID;
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}
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} else if (Is == IS_SGPR) {
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switch (RegWidth) {
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default: return -1;
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case 1: return AMDGPU::SGPR_32RegClassID;
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case 2: return AMDGPU::SGPR_64RegClassID;
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case 4: return AMDGPU::SReg_128RegClassID;
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case 8: return AMDGPU::SReg_256RegClassID;
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case 16: return AMDGPU::SReg_512RegClassID;
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}
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}
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switch (RegWidth) {
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default: return -1;
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case 1: return AMDGPU::SGPR_32RegClassID;
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case 2: return AMDGPU::SGPR_64RegClassID;
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case 4: return AMDGPU::SReg_128RegClassID;
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case 8: return AMDGPU::SReg_256RegClassID;
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case 16: return AMDGPU::SReg_512RegClassID;
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}
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return -1;
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}
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static unsigned getRegForName(StringRef RegName) {
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@ -611,6 +620,10 @@ static unsigned getRegForName(StringRef RegName) {
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.Case("vcc_hi", AMDGPU::VCC_HI)
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.Case("exec_lo", AMDGPU::EXEC_LO)
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.Case("exec_hi", AMDGPU::EXEC_HI)
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.Case("tma_lo", AMDGPU::TMA_LO)
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.Case("tma_hi", AMDGPU::TMA_HI)
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.Case("tba_lo", AMDGPU::TBA_LO)
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.Case("tba_hi", AMDGPU::TBA_HI)
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.Default(0);
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}
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@ -641,21 +654,21 @@ std::unique_ptr<AMDGPUOperand> AMDGPUAsmParser::parseRegister() {
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TRI, &getSTI(), false);
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}
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// Match vgprs and sgprs
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if (RegName[0] != 's' && RegName[0] != 'v')
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// Match vgprs, sgprs and ttmps
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if (RegName[0] != 's' && RegName[0] != 'v' && !RegName.startswith("ttmp"))
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return nullptr;
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bool IsVgpr = RegName[0] == 'v';
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const RegisterKind Is = RegName[0] == 'v' ? IS_VGPR : RegName[0] == 's' ? IS_SGPR : IS_TTMP;
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unsigned RegWidth;
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unsigned RegIndexInClass;
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if (RegName.size() > 1) {
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// We have a 32-bit register
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if (RegName.size() > (Is == IS_TTMP ? strlen("ttmp") : 1) ) {
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// We have a single 32-bit register. Syntax: vXX
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RegWidth = 1;
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if (RegName.substr(1).getAsInteger(10, RegIndexInClass))
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if (RegName.substr(Is == IS_TTMP ? strlen("ttmp") : 1).getAsInteger(10, RegIndexInClass))
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return nullptr;
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Parser.Lex();
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} else {
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// We have a register greater than 32-bits.
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// We have a register greater than 32-bits (a range of single registers). Syntax: v[XX:YY]
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int64_t RegLo, RegHi;
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Parser.Lex();
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@ -678,11 +691,11 @@ std::unique_ptr<AMDGPUOperand> AMDGPUAsmParser::parseRegister() {
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Parser.Lex();
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RegWidth = (RegHi - RegLo) + 1;
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if (IsVgpr) {
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if (Is == IS_VGPR) {
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// VGPR registers aren't aligned.
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RegIndexInClass = RegLo;
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} else {
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// SGPR registers are aligned. Max alignment is 4 dwords.
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// SGPR and TTMP registers must be are aligned. Max required alignment is 4 dwords.
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unsigned Size = std::min(RegWidth, 4u);
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if (RegLo % Size != 0)
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return nullptr;
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@ -691,7 +704,7 @@ std::unique_ptr<AMDGPUOperand> AMDGPUAsmParser::parseRegister() {
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}
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}
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int RCID = getRegClass(IsVgpr, RegWidth);
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int RCID = getRegClass(Is, RegWidth);
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if (RCID == -1)
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return nullptr;
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@ -18,6 +18,8 @@
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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#include <string>
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using namespace llvm;
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void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
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@ -189,6 +191,18 @@ void AMDGPUInstPrinter::printRegOperand(unsigned reg, raw_ostream &O,
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case AMDGPU::VCC_HI:
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O << "vcc_hi";
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return;
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case AMDGPU::TBA_LO:
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O << "tba_lo";
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return;
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case AMDGPU::TBA_HI:
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O << "tba_hi";
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return;
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case AMDGPU::TMA_LO:
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O << "tma_lo";
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return;
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case AMDGPU::TMA_HI:
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O << "tma_hi";
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return;
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case AMDGPU::EXEC_LO:
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O << "exec_lo";
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return;
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@ -205,41 +219,44 @@ void AMDGPUInstPrinter::printRegOperand(unsigned reg, raw_ostream &O,
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break;
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}
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char Type;
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std::string Type;
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unsigned NumRegs;
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if (MRI.getRegClass(AMDGPU::VGPR_32RegClassID).contains(reg)) {
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Type = 'v';
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Type = "v";
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NumRegs = 1;
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} else if (MRI.getRegClass(AMDGPU::SGPR_32RegClassID).contains(reg)) {
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Type = 's';
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Type = "s";
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NumRegs = 1;
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} else if (MRI.getRegClass(AMDGPU::VReg_64RegClassID).contains(reg)) {
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Type = 'v';
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Type = "v";
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NumRegs = 2;
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} else if (MRI.getRegClass(AMDGPU::SReg_64RegClassID).contains(reg)) {
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Type = 's';
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} else if (MRI.getRegClass(AMDGPU::SGPR_64RegClassID).contains(reg)) {
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Type = "s";
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NumRegs = 2;
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} else if (MRI.getRegClass(AMDGPU::TTMP_64RegClassID).contains(reg)) {
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Type = "ttmp";
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NumRegs = 2;
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} else if (MRI.getRegClass(AMDGPU::VReg_128RegClassID).contains(reg)) {
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Type = 'v';
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Type = "v";
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NumRegs = 4;
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} else if (MRI.getRegClass(AMDGPU::SReg_128RegClassID).contains(reg)) {
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Type = 's';
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Type = "s";
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NumRegs = 4;
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} else if (MRI.getRegClass(AMDGPU::VReg_96RegClassID).contains(reg)) {
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Type = 'v';
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Type = "v";
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NumRegs = 3;
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} else if (MRI.getRegClass(AMDGPU::VReg_256RegClassID).contains(reg)) {
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Type = 'v';
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Type = "v";
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NumRegs = 8;
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} else if (MRI.getRegClass(AMDGPU::SReg_256RegClassID).contains(reg)) {
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Type = 's';
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Type = "s";
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NumRegs = 8;
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} else if (MRI.getRegClass(AMDGPU::VReg_512RegClassID).contains(reg)) {
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Type = 'v';
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Type = "v";
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NumRegs = 16;
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} else if (MRI.getRegClass(AMDGPU::SReg_512RegClassID).contains(reg)) {
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Type = 's';
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Type = "s";
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NumRegs = 16;
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} else {
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O << getRegisterName(reg);
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@ -249,6 +266,8 @@ void AMDGPUInstPrinter::printRegOperand(unsigned reg, raw_ostream &O,
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// The low 8 bits of the encoding value is the register index, for both VGPRs
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// and SGPRs.
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unsigned RegIdx = MRI.getEncodingValue(reg) & ((1 << 8) - 1);
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if (Type == "ttmp")
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RegIdx -= 112; // Trap temps start at offset 112. TODO: Get this from tablegen.
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if (NumRegs == 1) {
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O << Type << RegIdx;
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return;
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@ -114,6 +114,16 @@ BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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reserveRegisterTuples(Reserved, AMDGPU::EXEC);
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reserveRegisterTuples(Reserved, AMDGPU::FLAT_SCR);
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// Reserve Trap Handler registers - support is not implemented in Codegen.
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reserveRegisterTuples(Reserved, AMDGPU::TBA);
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reserveRegisterTuples(Reserved, AMDGPU::TMA);
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reserveRegisterTuples(Reserved, AMDGPU::TTMP0_TTMP1);
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reserveRegisterTuples(Reserved, AMDGPU::TTMP2_TTMP3);
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reserveRegisterTuples(Reserved, AMDGPU::TTMP4_TTMP5);
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reserveRegisterTuples(Reserved, AMDGPU::TTMP6_TTMP7);
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reserveRegisterTuples(Reserved, AMDGPU::TTMP8_TTMP9);
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reserveRegisterTuples(Reserved, AMDGPU::TTMP10_TTMP11);
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// Reserve the last 2 registers so we will always have at least 2 more that
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// will physically contain VCC.
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reserveRegisterTuples(Reserved, AMDGPU::SGPR102_SGPR103);
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@ -640,7 +650,21 @@ unsigned SIRegisterInfo::getPhysRegSubReg(unsigned Reg,
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switch(Channel) {
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case 0: return AMDGPU::VCC_LO;
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case 1: return AMDGPU::VCC_HI;
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default: llvm_unreachable("Invalid SubIdx for VCC");
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default: llvm_unreachable("Invalid SubIdx for VCC"); break;
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}
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case AMDGPU::TBA:
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switch(Channel) {
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case 0: return AMDGPU::TBA_LO;
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case 1: return AMDGPU::TBA_HI;
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default: llvm_unreachable("Invalid SubIdx for TBA"); break;
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}
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case AMDGPU::TMA:
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switch(Channel) {
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case 0: return AMDGPU::TMA_LO;
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case 1: return AMDGPU::TMA_HI;
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default: llvm_unreachable("Invalid SubIdx for TMA"); break;
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}
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case AMDGPU::FLAT_SCR:
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@ -44,6 +44,40 @@ def EXEC : RegisterWithSubRegs<"EXEC", [EXEC_LO, EXEC_HI]>,
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def SCC : SIReg<"scc", 253>;
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def M0 : SIReg <"m0", 124>;
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// Trap handler registers
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def TBA_LO : SIReg<"tba_lo", 108>;
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def TBA_HI : SIReg<"tba_hi", 109>;
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def TBA : RegisterWithSubRegs<"tba", [TBA_LO, TBA_HI]>,
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DwarfRegAlias<TBA_LO> {
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let Namespace = "AMDGPU";
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let SubRegIndices = [sub0, sub1];
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let HWEncoding = 108;
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}
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def TMA_LO : SIReg<"tma_lo", 110>;
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def TMA_HI : SIReg<"tma_hi", 111>;
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def TMA : RegisterWithSubRegs<"tma", [TMA_LO, TMA_HI]>,
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DwarfRegAlias<TMA_LO> {
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let Namespace = "AMDGPU";
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let SubRegIndices = [sub0, sub1];
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let HWEncoding = 110;
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}
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def TTMP0 : SIReg <"ttmp0", 112>;
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def TTMP1 : SIReg <"ttmp1", 113>;
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def TTMP2 : SIReg <"ttmp2", 114>;
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def TTMP3 : SIReg <"ttmp3", 115>;
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def TTMP4 : SIReg <"ttmp4", 116>;
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def TTMP5 : SIReg <"ttmp5", 117>;
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def TTMP6 : SIReg <"ttmp6", 118>;
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def TTMP7 : SIReg <"ttmp7", 119>;
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def TTMP8 : SIReg <"ttmp8", 120>;
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def TTMP9 : SIReg <"ttmp9", 121>;
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def TTMP10 : SIReg <"ttmp10", 122>;
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def TTMP11 : SIReg <"ttmp11", 123>;
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multiclass FLAT_SCR_LOHI_m <string n, bits<16> ci_e, bits<16> vi_e> {
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def _ci : SIReg<n, ci_e>;
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def _vi : SIReg<n, vi_e>;
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@ -135,6 +169,24 @@ def SGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
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(add (decimate (shl SGPR_32, 14), 4)),
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(add (decimate (shl SGPR_32, 15), 4))]>;
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// Trap handler TMP 32-bit registers
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def TTMP_32 : RegisterClass<"AMDGPU", [i32, f32], 32,
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(add (sequence "TTMP%u", 0, 11))> {
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let isAllocatable = 0;
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}
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// Trap handler TMP 64-bit registers
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def TTMP_64Regs : RegisterTuples<[sub0, sub1],
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[(add (decimate TTMP_32, 2)),
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(add (decimate (shl TTMP_32, 1), 2))]>;
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// Trap handler TMP 128-bit registers
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def TTMP_128Regs : RegisterTuples<[sub0, sub1, sub2, sub3],
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[(add (decimate TTMP_32, 4)),
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(add (decimate (shl TTMP_32, 1), 4)),
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(add (decimate (shl TTMP_32, 2), 4)),
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(add (decimate (shl TTMP_32, 3), 4))]>;
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// VGPR 32-bit registers
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def VGPR_32 : RegisterClass<"AMDGPU", [i32, f32], 32,
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(add (sequence "VGPR%u", 0, 255))>;
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@ -199,13 +251,18 @@ class RegImmMatcher<string name> : AsmOperandClass {
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// Register class for all scalar registers (SGPRs + Special Registers)
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def SReg_32 : RegisterClass<"AMDGPU", [i32, f32], 32,
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(add SGPR_32, M0, VCC_LO, VCC_HI, EXEC_LO, EXEC_HI, FLAT_SCR_LO, FLAT_SCR_HI)
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(add SGPR_32, M0, VCC_LO, VCC_HI, EXEC_LO, EXEC_HI, FLAT_SCR_LO, FLAT_SCR_HI,
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TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI)
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>;
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def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64], 32, (add SGPR_64Regs)>;
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def TTMP_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64], 32, (add TTMP_64Regs)> {
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let isAllocatable = 0;
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}
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def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64, i1], 32,
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(add SGPR_64, VCC, EXEC, FLAT_SCR)
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(add SGPR_64, VCC, EXEC, FLAT_SCR, TTMP_64)
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>;
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def SReg_128 : RegisterClass<"AMDGPU", [v4i32, v16i8, v2i64], 32, (add SGPR_128)> {
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@ -201,22 +201,14 @@ entry:
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; GCN-LABEL: {{^}}smrd_valu_ci_offset_x16:
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; GCN-NOHSA-NOT: v_add
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; GCN-NOHSA: s_mov_b32 [[OFFSET0:s[0-9]+]], 0x13480{{$}}
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; GCN-NOHSA-NOT: v_add
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; GCN-NOHSA: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET0]] addr64{{$}}
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; GCN-NOHSA-NOT: v_add
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; GCN-NOHSA: s_mov_b32 [[OFFSET1:s[0-9]+]], 0x13490{{$}}
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; GCN-NOHSA-NOT: v_add
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; GCN-NOHSA: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET1]] addr64{{$}}
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; GCN-NOHSA-NOT: v_add
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; GCN-NOHSA: s_mov_b32 [[OFFSET2:s[0-9]+]], 0x134a0{{$}}
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; GCN-NOHSA-NOT: v_add
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; GCN-NOHSA: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET2]] addr64{{$}}
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; GCN-NOHSA-NOT: v_add
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; GCN-NOHSA: s_mov_b32 [[OFFSET3:s[0-9]+]], 0x134b0{{$}}
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; GCN-NOHSA-NOT: v_add
|
||||
; GCN-NOHSA: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET3]] addr64{{$}}
|
||||
; GCN-NOHSA-DAG: s_mov_b32 [[OFFSET0:s[0-9]+]], 0x13480{{$}}
|
||||
; GCN-NOHSA-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET0]] addr64{{$}}
|
||||
; GCN-NOHSA-DAG: s_mov_b32 [[OFFSET1:s[0-9]+]], 0x13490{{$}}
|
||||
; GCN-NOHSA-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET1]] addr64{{$}}
|
||||
; GCN-NOHSA-DAG: s_mov_b32 [[OFFSET2:s[0-9]+]], 0x134a0{{$}}
|
||||
; GCN-NOHSA-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET2]] addr64{{$}}
|
||||
; GCN-NOHSA-DAG: s_mov_b32 [[OFFSET3:s[0-9]+]], 0x134b0{{$}}
|
||||
; GCN-NOHSA-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET3]] addr64{{$}}
|
||||
|
||||
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
||||
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
||||
|
||||
99
test/MC/AMDGPU/trap.s
Normal file
99
test/MC/AMDGPU/trap.s
Normal file
@ -0,0 +1,99 @@
|
||||
// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=SICI
|
||||
// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s --check-prefix=SICI
|
||||
// RUN: llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck %s --check-prefix=VI
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Trap Handler related - 32 bit registers
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
s_add_u32 ttmp0, ttmp0, 4
|
||||
// SICI: s_add_u32 ttmp0, ttmp0, 4 ; encoding: [0x70,0x84,0x70,0x80]
|
||||
// VI: s_add_u32 ttmp0, ttmp0, 4 ; encoding: [0x70,0x84,0x70,0x80]
|
||||
|
||||
s_add_u32 ttmp4, 8, ttmp4
|
||||
// SICI: s_add_u32 ttmp4, 8, ttmp4 ; encoding: [0x88,0x74,0x74,0x80]
|
||||
// VI: s_add_u32 ttmp4, 8, ttmp4 ; encoding: [0x88,0x74,0x74,0x80]
|
||||
|
||||
s_add_u32 ttmp4, ttmp4, 0x00000100
|
||||
// SICI: s_add_u32 ttmp4, ttmp4, 0x100 ; encoding: [0x74,0xff,0x74,0x80,0x00,0x01,0x00,0x00]
|
||||
// VI: s_add_u32 ttmp4, ttmp4, 0x100 ; encoding: [0x74,0xff,0x74,0x80,0x00,0x01,0x00,0x00]
|
||||
|
||||
s_add_u32 ttmp4, ttmp4, 4
|
||||
// SICI: s_add_u32 ttmp4, ttmp4, 4 ; encoding: [0x74,0x84,0x74,0x80]
|
||||
// VI: s_add_u32 ttmp4, ttmp4, 4 ; encoding: [0x74,0x84,0x74,0x80]
|
||||
|
||||
s_add_u32 ttmp4, ttmp8, ttmp4
|
||||
// SICI: s_add_u32 ttmp4, ttmp8, ttmp4 ; encoding: [0x78,0x74,0x74,0x80]
|
||||
// VI: s_add_u32 ttmp4, ttmp8, ttmp4 ; encoding: [0x78,0x74,0x74,0x80]
|
||||
|
||||
s_and_b32 ttmp10, ttmp8, 0x00000080
|
||||
// SICI: s_and_b32 ttmp10, ttmp8, 0x80 ; encoding: [0x78,0xff,0x7a,0x87,0x80,0x00,0x00,0x00]
|
||||
// VI: s_and_b32 ttmp10, ttmp8, 0x80 ; encoding: [0x78,0xff,0x7a,0x86,0x80,0x00,0x00,0x00]
|
||||
|
||||
s_and_b32 ttmp9, tma_hi, 0x0000ffff
|
||||
// SICI: s_and_b32 ttmp9, tma_hi, 0xffff ; encoding: [0x6f,0xff,0x79,0x87,0xff,0xff,0x00,0x00]
|
||||
// VI: s_and_b32 ttmp9, tma_hi, 0xffff ; encoding: [0x6f,0xff,0x79,0x86,0xff,0xff,0x00,0x00]
|
||||
|
||||
s_and_b32 ttmp9, ttmp9, 0x000001ff
|
||||
// SICI: s_and_b32 ttmp9, ttmp9, 0x1ff ; encoding: [0x79,0xff,0x79,0x87,0xff,0x01,0x00,0x00]
|
||||
// VI: s_and_b32 ttmp9, ttmp9, 0x1ff ; encoding: [0x79,0xff,0x79,0x86,0xff,0x01,0x00,0x00]
|
||||
|
||||
s_and_b32 ttmp9, tma_lo, 0xffff0000
|
||||
// SICI: s_and_b32 ttmp9, tma_lo, 0xffff0000 ; encoding: [0x6e,0xff,0x79,0x87,0x00,0x00,0xff,0xff]
|
||||
// VI: s_and_b32 ttmp9, tma_lo, 0xffff0000 ; encoding: [0x6e,0xff,0x79,0x86,0x00,0x00,0xff,0xff]
|
||||
|
||||
s_and_b32 ttmp9, ttmp9, ttmp8
|
||||
// SICI: s_and_b32 ttmp9, ttmp9, ttmp8 ; encoding: [0x79,0x78,0x79,0x87]
|
||||
// VI: s_and_b32 ttmp9, ttmp9, ttmp8 ; encoding: [0x79,0x78,0x79,0x86]
|
||||
|
||||
s_and_b32 ttmp8, ttmp1, 0x01000000
|
||||
// SICI: s_and_b32 ttmp8, ttmp1, 0x1000000 ; encoding: [0x71,0xff,0x78,0x87,0x00,0x00,0x00,0x01]
|
||||
// VI: s_and_b32 ttmp8, ttmp1, 0x1000000 ; encoding: [0x71,0xff,0x78,0x86,0x00,0x00,0x00,0x01]
|
||||
|
||||
s_cmp_eq_i32 ttmp8, 0
|
||||
// SICI: s_cmp_eq_i32 ttmp8, 0 ; encoding: [0x78,0x80,0x00,0xbf]
|
||||
// VI: s_cmp_eq_i32 ttmp8, 0 ; encoding: [0x78,0x80,0x00,0xbf]
|
||||
|
||||
s_cmp_eq_i32 ttmp8, 0x000000fe
|
||||
// SICI: s_cmp_eq_i32 ttmp8, 0xfe ; encoding: [0x78,0xff,0x00,0xbf,0xfe,0x00,0x00,0x00]
|
||||
// VI: s_cmp_eq_i32 ttmp8, 0xfe ; encoding: [0x78,0xff,0x00,0xbf,0xfe,0x00,0x00,0x00]
|
||||
|
||||
s_lshr_b32 ttmp8, ttmp8, 12
|
||||
// SICI: s_lshr_b32 ttmp8, ttmp8, 12 ; encoding: [0x78,0x8c,0x78,0x90]
|
||||
// VI: s_lshr_b32 ttmp8, ttmp8, 12 ; encoding: [0x78,0x8c,0x78,0x8f]
|
||||
|
||||
s_mov_b32 m0, ttmp8
|
||||
// SICI: s_mov_b32 m0, ttmp8 ; encoding: [0x78,0x03,0xfc,0xbe]
|
||||
// VI: s_mov_b32 m0, ttmp8 ; encoding: [0x78,0x00,0xfc,0xbe]
|
||||
|
||||
s_mov_b32 ttmp10, 0
|
||||
// SICI: s_mov_b32 ttmp10, 0 ; encoding: [0x80,0x03,0xfa,0xbe]
|
||||
// VI: s_mov_b32 ttmp10, 0 ; encoding: [0x80,0x00,0xfa,0xbe]
|
||||
|
||||
s_mov_b32 ttmp11, 0x01024fac
|
||||
// SICI: s_mov_b32 ttmp11, 0x1024fac ; encoding: [0xff,0x03,0xfb,0xbe,0xac,0x4f,0x02,0x01]
|
||||
// VI: s_mov_b32 ttmp11, 0x1024fac ; encoding: [0xff,0x00,0xfb,0xbe,0xac,0x4f,0x02,0x01]
|
||||
|
||||
s_mov_b32 ttmp8, m0
|
||||
// SICI: s_mov_b32 ttmp8, m0 ; encoding: [0x7c,0x03,0xf8,0xbe]
|
||||
// VI: s_mov_b32 ttmp8, m0 ; encoding: [0x7c,0x00,0xf8,0xbe]
|
||||
|
||||
s_mov_b32 ttmp8, tma_lo
|
||||
// SICI: s_mov_b32 ttmp8, tma_lo ; encoding: [0x6e,0x03,0xf8,0xbe]
|
||||
// VI: s_mov_b32 ttmp8, tma_lo ; encoding: [0x6e,0x00,0xf8,0xbe]
|
||||
|
||||
s_mul_i32 ttmp8, 0x00000324, ttmp8
|
||||
// SICI: s_mul_i32 ttmp8, 0x324, ttmp8 ; encoding: [0xff,0x78,0x78,0x93,0x24,0x03,0x00,0x00]
|
||||
// VI: s_mul_i32 ttmp8, 0x324, ttmp8 ; encoding: [0xff,0x78,0x78,0x92,0x24,0x03,0x00,0x00]
|
||||
|
||||
s_or_b32 ttmp9, ttmp9, 0x00280000
|
||||
// SICI: s_or_b32 ttmp9, ttmp9, 0x280000 ; encoding: [0x79,0xff,0x79,0x88,0x00,0x00,0x28,0x00]
|
||||
// VI: s_or_b32 ttmp9, ttmp9, 0x280000 ; encoding: [0x79,0xff,0x79,0x87,0x00,0x00,0x28,0x00]
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Trap Handler related - Pairs and quadruples of registers
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
s_mov_b64 ttmp[4:5], exec
|
||||
// SICI: s_mov_b64 ttmp[4:5], exec ; encoding: [0x7e,0x04,0xf4,0xbe]
|
||||
// VI: s_mov_b64 ttmp[4:5], exec ; encoding: [0x7e,0x01,0xf4,0xbe]
|
||||
Loading…
Reference in New Issue
Block a user