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AMDGPU: Select d16 loads into low component of register
llvm-svn: 318005
This commit is contained in:
Matt Arsenault
parent
d9c8715837
commit
eaea634604
@ -201,6 +201,8 @@ private:
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bool SelectVOP3PMadMixModsImpl(SDValue In, SDValue &Src, unsigned &Mods) const;
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bool SelectVOP3PMadMixMods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
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bool SelectHi16Elt(SDValue In, SDValue &Src) const;
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void SelectADD_SUB_I64(SDNode *N);
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void SelectUADDO_USUBO(SDNode *N);
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void SelectDIV_SCALE(SDNode *N);
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@ -1134,8 +1136,6 @@ bool AMDGPUDAGToDAGISel::SelectMUBUFScratchOffen(SDNode *Parent,
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if (ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) {
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unsigned Imm = CAddr->getZExtValue();
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assert(!SIInstrInfo::isLegalMUBUFImmOffset(Imm) &&
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"should have been selected by other pattern");
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SDValue HighBits = CurDAG->getTargetConstant(Imm & ~4095, DL, MVT::i32);
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MachineSDNode *MovHighBits = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32,
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@ -2024,6 +2024,35 @@ bool AMDGPUDAGToDAGISel::SelectVOP3PMadMixMods(SDValue In, SDValue &Src,
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return true;
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}
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// TODO: Can we identify things like v_mad_mixhi_f16?
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bool AMDGPUDAGToDAGISel::SelectHi16Elt(SDValue In, SDValue &Src) const {
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if (In.isUndef()) {
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Src = In;
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return true;
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}
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(In)) {
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SDLoc SL(In);
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SDValue K = CurDAG->getTargetConstant(C->getZExtValue() << 16, SL, MVT::i32);
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MachineSDNode *MovK = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32,
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SL, MVT::i32, K);
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Src = SDValue(MovK, 0);
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return true;
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}
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if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(In)) {
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SDLoc SL(In);
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SDValue K = CurDAG->getTargetConstant(
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C->getValueAPF().bitcastToAPInt().getZExtValue() << 16, SL, MVT::i32);
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MachineSDNode *MovK = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32,
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SL, MVT::i32, K);
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Src = SDValue(MovK, 0);
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return true;
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}
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return isExtractHiElt(In, Src);
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}
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void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
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const AMDGPUTargetLowering& Lowering =
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*static_cast<const AMDGPUTargetLowering*>(getTargetLowering());
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@ -133,6 +133,29 @@ def shl_oneuse : HasOneUseBinOp<shl>;
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def select_oneuse : HasOneUseTernaryOp<select>;
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def srl_16 : PatFrag<
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(ops node:$src0), (srl_oneuse node:$src0, (i32 16))
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>;
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def hi_i16_elt : PatFrag<
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(ops node:$src0), (i16 (trunc (i32 (srl_16 node:$src0))))
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>;
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def hi_f16_elt : PatLeaf<
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(vt), [{
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if (N->getOpcode() != ISD::BITCAST)
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return false;
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SDValue Tmp = N->getOperand(0);
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if (Tmp.getOpcode() != ISD::SRL)
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return false;
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if (const auto *RHS = dyn_cast<ConstantSDNode>(Tmp.getOperand(1))
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return RHS->getZExtValue() == 16;
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return false;
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}]>;
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//===----------------------------------------------------------------------===//
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// PatLeafs for floating-point comparisons
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//===----------------------------------------------------------------------===//
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@ -811,7 +811,7 @@ def BUFFER_WBINVL1_SC : MUBUF_Invalidate <"buffer_wbinvl1_sc",
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let SubtargetPredicate = HasD16LoadStore in {
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defm BUFFER_LOAD_UBYTE_D16 : MUBUF_Pseudo_Loads <
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"buffer_load_ubyte_d16", VGPR_32, i32
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"buffer_load_ubyte_d16", VGPR_32, i32, null_frag, 1
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>;
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defm BUFFER_LOAD_UBYTE_D16_HI : MUBUF_Pseudo_Loads <
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@ -819,7 +819,7 @@ defm BUFFER_LOAD_UBYTE_D16_HI : MUBUF_Pseudo_Loads <
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>;
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defm BUFFER_LOAD_SBYTE_D16 : MUBUF_Pseudo_Loads <
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"buffer_load_sbyte_d16", VGPR_32, i32
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"buffer_load_sbyte_d16", VGPR_32, i32, null_frag, 1
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>;
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defm BUFFER_LOAD_SBYTE_D16_HI : MUBUF_Pseudo_Loads <
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@ -827,7 +827,7 @@ defm BUFFER_LOAD_SBYTE_D16_HI : MUBUF_Pseudo_Loads <
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>;
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defm BUFFER_LOAD_SHORT_D16 : MUBUF_Pseudo_Loads <
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"buffer_load_short_d16", VGPR_32, i32
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"buffer_load_short_d16", VGPR_32, i32, null_frag, 1
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>;
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defm BUFFER_LOAD_SHORT_D16_HI : MUBUF_Pseudo_Loads <
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@ -1169,6 +1169,36 @@ multiclass MUBUFScratchLoadPat_Hi16 <MUBUF_Pseudo InstrOffen,
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>;
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}
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multiclass MUBUFScratchLoadPat_Lo16 <MUBUF_Pseudo InstrOffen,
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MUBUF_Pseudo InstrOffset,
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ValueType vt, PatFrag ld> {
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def : GCNPat <
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(build_vector (vt (ld (MUBUFScratchOffen v4i32:$srsrc, i32:$vaddr,
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i32:$soffset, u16imm:$offset))),
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(vt (Hi16Elt vt:$hi))),
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(v2i16 (InstrOffen $vaddr, $srsrc, $soffset, $offset, 0, 0, 0, $hi))
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>;
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def : GCNPat <
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(build_vector (f16 (bitconvert (vt (ld (MUBUFScratchOffen v4i32:$srsrc, i32:$vaddr,
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i32:$soffset, u16imm:$offset))))),
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(f16 (Hi16Elt f16:$hi))),
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(v2f16 (InstrOffen $vaddr, $srsrc, $soffset, $offset, 0, 0, 0, $hi))
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>;
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def : GCNPat <
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(build_vector (vt (ld (MUBUFScratchOffset v4i32:$srsrc, i32:$soffset, u16imm:$offset))),
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(vt (Hi16Elt vt:$hi))),
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(v2i16 (InstrOffset $srsrc, $soffset, $offset, 0, 0, 0, $hi))
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>;
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def : GCNPat <
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(build_vector (f16 (bitconvert (vt (ld (MUBUFScratchOffset v4i32:$srsrc, i32:$soffset, u16imm:$offset))))),
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(f16 (Hi16Elt f16:$hi))),
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(v2f16 (InstrOffset $srsrc, $soffset, $offset, 0, 0, 0, $hi))
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>;
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}
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defm : MUBUFScratchLoadPat <BUFFER_LOAD_SBYTE_OFFEN, BUFFER_LOAD_SBYTE_OFFSET, i32, sextloadi8_private>;
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defm : MUBUFScratchLoadPat <BUFFER_LOAD_UBYTE_OFFEN, BUFFER_LOAD_UBYTE_OFFSET, i32, az_extloadi8_private>;
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defm : MUBUFScratchLoadPat <BUFFER_LOAD_SBYTE_OFFEN, BUFFER_LOAD_SBYTE_OFFSET, i16, sextloadi8_private>;
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@ -1184,6 +1214,10 @@ let OtherPredicates = [HasD16LoadStore] in {
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defm : MUBUFScratchLoadPat_Hi16<BUFFER_LOAD_SHORT_D16_HI_OFFEN, BUFFER_LOAD_SHORT_D16_HI_OFFSET, i16, load_private>;
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defm : MUBUFScratchLoadPat_Hi16<BUFFER_LOAD_UBYTE_D16_HI_OFFEN, BUFFER_LOAD_UBYTE_D16_HI_OFFSET, i16, az_extloadi8_private>;
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defm : MUBUFScratchLoadPat_Hi16<BUFFER_LOAD_SBYTE_D16_HI_OFFEN, BUFFER_LOAD_SBYTE_D16_HI_OFFSET, i16, sextloadi8_private>;
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defm : MUBUFScratchLoadPat_Lo16<BUFFER_LOAD_SHORT_D16_OFFEN, BUFFER_LOAD_SHORT_D16_OFFSET, i16, load_private>;
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defm : MUBUFScratchLoadPat_Lo16<BUFFER_LOAD_UBYTE_D16_OFFEN, BUFFER_LOAD_UBYTE_D16_OFFSET, i16, az_extloadi8_private>;
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defm : MUBUFScratchLoadPat_Lo16<BUFFER_LOAD_SBYTE_D16_OFFEN, BUFFER_LOAD_SBYTE_D16_OFFSET, i16, sextloadi8_private>;
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}
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// BUFFER_LOAD_DWORD*, addr64=0
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@ -559,6 +559,19 @@ multiclass DSReadPat_Hi16 <DS_Pseudo inst, PatFrag frag, ValueType vt = i16> {
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>;
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}
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multiclass DSReadPat_Lo16 <DS_Pseudo inst, PatFrag frag, ValueType vt = i16> {
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def : GCNPat <
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(build_vector (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))), (vt (Hi16Elt vt:$hi))),
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(v2i16 (inst $ptr, (as_i16imm $offset), 0, $hi))
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>;
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def : GCNPat <
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(build_vector (f16 (bitconvert (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))))), (f16 (Hi16Elt f16:$hi))),
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(v2f16 (inst $ptr, (as_i16imm $offset), 0, $hi))
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>;
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}
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def : DSReadPat <DS_READ_I8, i32, sextloadi8_local_m0>;
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def : DSReadPat <DS_READ_U8, i32, az_extloadi8_local_m0>;
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def : DSReadPat <DS_READ_I8, i16, sextloadi8_local_m0>;
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@ -587,6 +600,11 @@ let AddedComplexity = 100 in {
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defm : DSReadPat_Hi16<DS_READ_U16_D16_HI, load_local>;
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defm : DSReadPat_Hi16<DS_READ_U8_D16_HI, az_extloadi8_local>;
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defm : DSReadPat_Hi16<DS_READ_I8_D16_HI, sextloadi8_local>;
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defm : DSReadPat_Lo16<DS_READ_U16_D16, load_local>;
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defm : DSReadPat_Lo16<DS_READ_U8_D16, az_extloadi8_local>;
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defm : DSReadPat_Lo16<DS_READ_I8_D16, sextloadi8_local>;
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}
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}
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@ -654,6 +654,30 @@ multiclass FlatSignedLoadPat_Hi16 <FLAT_Pseudo inst, SDPatternOperator node, Val
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>;
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}
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multiclass FlatLoadPat_Lo16 <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt = i16> {
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def : GCNPat <
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(build_vector (vt (node (FLATOffset i64:$vaddr, i16:$offset, i1:$slc))), (vt (Hi16Elt vt:$hi))),
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(v2i16 (inst $vaddr, $offset, 0, $slc, $hi))
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>;
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def : GCNPat <
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(build_vector (f16 (bitconvert (vt (node (FLATOffset i64:$vaddr, i16:$offset, i1:$slc))))), (f16 (Hi16Elt f16:$hi))),
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(v2f16 (inst $vaddr, $offset, 0, $slc, $hi))
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>;
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}
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multiclass FlatSignedLoadPat_Lo16 <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt = i16> {
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def : GCNPat <
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(build_vector (vt (node (FLATOffsetSigned i64:$vaddr, i16:$offset, i1:$slc))), (vt (Hi16Elt vt:$hi))),
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(v2i16 (inst $vaddr, $offset, 0, $slc, $hi))
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>;
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def : GCNPat <
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(build_vector (f16 (bitconvert (vt (node (FLATOffsetSigned i64:$vaddr, i16:$offset, i1:$slc))))), (f16 (Hi16Elt f16:$hi))),
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(v2f16 (inst $vaddr, $offset, 0, $slc, $hi))
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>;
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}
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class FlatLoadAtomicPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat <
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(vt (node (FLATAtomic i64:$vaddr, i16:$offset, i1:$slc))),
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(inst $vaddr, $offset, 0, $slc)
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@ -765,6 +789,12 @@ defm : FlatLoadPat_Hi16 <FLAT_LOAD_UBYTE_D16_HI, az_extloadi8_flat>;
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defm : FlatLoadPat_Hi16 <FLAT_LOAD_SBYTE_D16_HI, sextloadi8_flat>;
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defm : FlatLoadPat_Hi16 <FLAT_LOAD_SHORT_D16_HI, load_flat>;
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}
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let AddedComplexity = 9 in {
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defm : FlatLoadPat_Lo16 <FLAT_LOAD_UBYTE_D16, az_extloadi8_flat>;
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defm : FlatLoadPat_Lo16 <FLAT_LOAD_SBYTE_D16, sextloadi8_flat>;
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defm : FlatLoadPat_Lo16 <FLAT_LOAD_SHORT_D16, load_flat>;
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}
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}
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} // End OtherPredicates = [HasFlatAddressSpace]
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@ -801,6 +831,11 @@ def : FlatStoreSignedPat <GLOBAL_STORE_BYTE_D16_HI, truncstorei8_hi16_global, i3
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defm : FlatSignedLoadPat_Hi16 <GLOBAL_LOAD_UBYTE_D16_HI, az_extloadi8_global>;
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defm : FlatSignedLoadPat_Hi16 <GLOBAL_LOAD_SBYTE_D16_HI, sextloadi8_global>;
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defm : FlatSignedLoadPat_Hi16 <GLOBAL_LOAD_SHORT_D16_HI, load_global>;
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defm : FlatSignedLoadPat_Lo16 <GLOBAL_LOAD_UBYTE_D16, az_extloadi8_global>;
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defm : FlatSignedLoadPat_Lo16 <GLOBAL_LOAD_SBYTE_D16, sextloadi8_global>;
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defm : FlatSignedLoadPat_Lo16 <GLOBAL_LOAD_SHORT_D16, load_global>;
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}
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def : FlatStoreSignedAtomicPat <GLOBAL_STORE_DWORD, store_atomic_global, i32>;
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@ -843,6 +843,9 @@ def VOP3OpSelMods0 : ComplexPattern<untyped, 3, "SelectVOP3OpSelMods0">;
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def VOP3PMadMixMods : ComplexPattern<untyped, 2, "SelectVOP3PMadMixMods">;
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def Hi16Elt : ComplexPattern<untyped, 1, "SelectHi16Elt">;
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//===----------------------------------------------------------------------===//
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// SI assembler operands
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//===----------------------------------------------------------------------===//
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@ -100,15 +100,16 @@ define amdgpu_kernel void @extract_vector_elt_v4i16(i16 addrspace(1)* %out, <4 x
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; SICIVI: buffer_store_short
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; SICIVI: buffer_store_short
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; GFX9: buffer_load_ushort
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; SICIVI: buffer_load_ushort
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; SICIVI: buffer_store_short
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; GFX9: buffer_load_ushort
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; GFX9: global_load_short_d16_hi
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; GFX9: global_load_short_d16 v
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; GFX9: buffer_store_dword
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; GFX9: buffer_store_dword
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; GCN: buffer_load_ushort
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; GCN: buffer_store_short
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; GFX9: buffer_load_ushort
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; GFX9: buffer_store_short
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define amdgpu_kernel void @dynamic_extract_vector_elt_v3i16(i16 addrspace(1)* %out, <3 x i16> %foo, i32 %idx) #0 {
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%p0 = extractelement <3 x i16> %foo, i32 %idx
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%out1 = getelementptr i16, i16 addrspace(1)* %out, i32 1
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@ -503,4 +503,102 @@ entry:
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ret void
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}
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; FIXME: Remove m0 init and waitcnt between reads
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; FIXME: Is there a cost to using the extload over not?
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; GCN-LABEL: {{^}}load_local_v2i16_split:
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; GCN: s_waitcnt
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; GFX9-NEXT: s_mov_b32 m0, -1
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; GFX9-NEXT: ds_read_u16 v1, v0
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; GFX9-NEXT: s_waitcnt
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; GFX9-NEXT: ds_read_u16_d16_hi v1, v0 offset:2
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; GFX9-NEXT: s_waitcnt
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; GFX9-NEXT: v_mov_b32_e32 v0, v1
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; GFX9-NEXT: s_setpc_b64
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define <2 x i16> @load_local_v2i16_split(i16 addrspace(3)* %in) #0 {
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entry:
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%gep = getelementptr inbounds i16, i16 addrspace(3)* %in, i32 1
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%load0 = load volatile i16, i16 addrspace(3)* %in
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%load1 = load volatile i16, i16 addrspace(3)* %gep
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%build0 = insertelement <2 x i16> undef, i16 %load0, i32 0
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%build1 = insertelement <2 x i16> %build0, i16 %load1, i32 1
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ret <2 x i16> %build1
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}
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; FIXME: Remove waitcnt between reads
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; GCN-LABEL: {{^}}load_global_v2i16_split:
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; GCN: s_waitcnt
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; GFX9-NEXT: global_load_ushort v2
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; GFX9-NEXT: s_waitcnt
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; GFX9-NEXT: global_load_short_d16_hi v2
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; GFX9-NEXT: s_waitcnt
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; GFX9-NEXT: v_mov_b32_e32 v0, v2
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; GFX9-NEXT: s_setpc_b64
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define <2 x i16> @load_global_v2i16_split(i16 addrspace(1)* %in) #0 {
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entry:
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%gep = getelementptr inbounds i16, i16 addrspace(1)* %in, i64 1
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%load0 = load volatile i16, i16 addrspace(1)* %in
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%load1 = load volatile i16, i16 addrspace(1)* %gep
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%build0 = insertelement <2 x i16> undef, i16 %load0, i32 0
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%build1 = insertelement <2 x i16> %build0, i16 %load1, i32 1
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ret <2 x i16> %build1
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}
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; FIXME: Remove waitcnt between reads
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; GCN-LABEL: {{^}}load_flat_v2i16_split:
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; GCN: s_waitcnt
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; GFX9-NEXT: flat_load_ushort v2
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; GFX9-NEXT: s_waitcnt
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; GFX9-NEXT: flat_load_short_d16_hi v2
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; GFX9-NEXT: s_waitcnt
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; GFX9-NEXT: v_mov_b32_e32 v0, v2
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; GFX9-NEXT: s_setpc_b64
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define <2 x i16> @load_flat_v2i16_split(i16 addrspace(4)* %in) #0 {
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entry:
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%gep = getelementptr inbounds i16, i16 addrspace(4)* %in, i64 1
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%load0 = load volatile i16, i16 addrspace(4)* %in
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%load1 = load volatile i16, i16 addrspace(4)* %gep
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%build0 = insertelement <2 x i16> undef, i16 %load0, i32 0
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%build1 = insertelement <2 x i16> %build0, i16 %load1, i32 1
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ret <2 x i16> %build1
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}
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; FIXME: Remove waitcnt between reads
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; GCN-LABEL: {{^}}load_constant_v2i16_split:
|
||||
; GCN: s_waitcnt
|
||||
; GFX9-NEXT: global_load_ushort v2
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: global_load_short_d16_hi v2
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: v_mov_b32_e32 v0, v2
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
define <2 x i16> @load_constant_v2i16_split(i16 addrspace(2)* %in) #0 {
|
||||
entry:
|
||||
%gep = getelementptr inbounds i16, i16 addrspace(2)* %in, i64 1
|
||||
%load0 = load volatile i16, i16 addrspace(2)* %in
|
||||
%load1 = load volatile i16, i16 addrspace(2)* %gep
|
||||
%build0 = insertelement <2 x i16> undef, i16 %load0, i32 0
|
||||
%build1 = insertelement <2 x i16> %build0, i16 %load1, i32 1
|
||||
ret <2 x i16> %build1
|
||||
}
|
||||
|
||||
; FIXME: Remove m0 init and waitcnt between reads
|
||||
; FIXME: Is there a cost to using the extload over not?
|
||||
; GCN-LABEL: {{^}}load_private_v2i16_split:
|
||||
; GCN: s_waitcnt
|
||||
; GFX9-NEXT: buffer_load_ushort v1, v0, s[0:3], s4 offen{{$}}
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: buffer_load_short_d16_hi v1, v0, s[0:3], s4 offen offset:2
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: v_mov_b32_e32 v0, v1
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
define <2 x i16> @load_private_v2i16_split(i16* %in) #0 {
|
||||
entry:
|
||||
%gep = getelementptr inbounds i16, i16* %in, i32 1
|
||||
%load0 = load volatile i16, i16* %in
|
||||
%load1 = load volatile i16, i16* %gep
|
||||
%build0 = insertelement <2 x i16> undef, i16 %load0, i32 0
|
||||
%build1 = insertelement <2 x i16> %build0, i16 %load1, i32 1
|
||||
ret <2 x i16> %build1
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
|
||||
591
test/CodeGen/AMDGPU/load-lo16.ll
Normal file
591
test/CodeGen/AMDGPU/load-lo16.ll
Normal file
@ -0,0 +1,591 @@
|
||||
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s
|
||||
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s
|
||||
|
||||
; GCN-LABEL: {{^}}load_local_lo_v2i16_undeflo:
|
||||
; GCN: s_waitcnt
|
||||
; GFX9-NEXT: ds_read_u16_d16 v0, v0
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
|
||||
; VI: ds_read_u16
|
||||
define <2 x i16> @load_local_lo_v2i16_undeflo(i16 addrspace(3)* %in) #0 {
|
||||
entry:
|
||||
%load = load i16, i16 addrspace(3)* %in
|
||||
%build = insertelement <2 x i16> undef, i16 %load, i32 0
|
||||
ret <2 x i16> %build
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_local_lo_v2i16_reglo:
|
||||
; GCN: s_waitcnt
|
||||
; GFX9-NEXT: ds_read_u16_d16 v0, v0
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
|
||||
; VI: ds_read_u16
|
||||
define <2 x i16> @load_local_lo_v2i16_reglo(i16 addrspace(3)* %in, i16 %reg) #0 {
|
||||
entry:
|
||||
%load = load i16, i16 addrspace(3)* %in
|
||||
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
|
||||
%build1 = insertelement <2 x i16> %build0, i16 %load, i32 0
|
||||
ret <2 x i16> %build1
|
||||
}
|
||||
|
||||
; Show that we get reasonable regalloc without physreg constraints.
|
||||
; GCN-LABEL: {{^}}load_local_lo_v2i16_reglo_vreg:
|
||||
; GCN: s_waitcnt
|
||||
; GFX9-NEXT: ds_read_u16_d16 v0, v0
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: global_store_dword v[0:1], v0, off{{$}}
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
|
||||
; VI: ds_read_u16
|
||||
define void @load_local_lo_v2i16_reglo_vreg(i16 addrspace(3)* %in, i16 %reg) #0 {
|
||||
entry:
|
||||
%load = load i16, i16 addrspace(3)* %in
|
||||
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
|
||||
%build1 = insertelement <2 x i16> %build0, i16 %load, i32 0
|
||||
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_local_lo_v2i16_zerolo:
|
||||
; GCN: s_waitcnt
|
||||
; GFX9-NEXT: v_mov_b32_e32 v1, 0
|
||||
; GFX9-NEXT: ds_read_u16_d16 v1, v0
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: v_mov_b32_e32 v0, v1
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
|
||||
; VI: ds_read_u16 v
|
||||
define <2 x i16> @load_local_lo_v2i16_zerolo(i16 addrspace(3)* %in) #0 {
|
||||
entry:
|
||||
%load = load i16, i16 addrspace(3)* %in
|
||||
%build = insertelement <2 x i16> zeroinitializer, i16 %load, i32 0
|
||||
ret <2 x i16> %build
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_local_lo_v2f16_fpimm:
|
||||
; GCN: s_waitcnt
|
||||
; GFX9-NEXT: v_mov_b32_e32 v1, 2.0
|
||||
; GFX9-NEXT: ds_read_u16_d16 v1, v0
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: v_mov_b32_e32 v0, v1
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
|
||||
; VI: ds_read_u16 v
|
||||
define <2 x half> @load_local_lo_v2f16_fpimm(half addrspace(3)* %in) #0 {
|
||||
entry:
|
||||
%load = load half, half addrspace(3)* %in
|
||||
%build = insertelement <2 x half> <half 0.0, half 2.0>, half %load, i32 0
|
||||
ret <2 x half> %build
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_local_lo_v2f16_reghi_vreg:
|
||||
; GCN: s_waitcnt
|
||||
; GFX9-NEXT: ds_read_u16_d16 v1, v0
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: global_store_dword v[0:1], v1, off{{$}}
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
|
||||
; VI: ds_read_u16 v
|
||||
define void @load_local_lo_v2f16_reghi_vreg(half addrspace(3)* %in, i32 %reg) #0 {
|
||||
entry:
|
||||
%reg.bc = bitcast i32 %reg to <2 x half>
|
||||
%load = load half, half addrspace(3)* %in
|
||||
%build1 = insertelement <2 x half> %reg.bc, half %load, i32 0
|
||||
store <2 x half> %build1, <2 x half> addrspace(1)* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_local_lo_v2f16_reglo_vreg:
|
||||
|
||||
; GFX9: ds_read_u16 v
|
||||
; GFX9: v_and_b32_e32 v{{[0-9]+}}, 0xffff, v{{[0-9]+}}
|
||||
; GFX9: v_lshl_or_b32 v{{[0-9]+}}, v{{[0-9]+}}, 16, v{{[0-9]+}}
|
||||
; GFX9: global_store_dword
|
||||
|
||||
; VI: ds_read_u16 v
|
||||
define void @load_local_lo_v2f16_reglo_vreg(half addrspace(3)* %in, half %reg) #0 {
|
||||
entry:
|
||||
%load = load half, half addrspace(3)* %in
|
||||
%build0 = insertelement <2 x half> undef, half %reg, i32 1
|
||||
%build1 = insertelement <2 x half> %build0, half %load, i32 0
|
||||
store <2 x half> %build1, <2 x half> addrspace(1)* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_local_lo_v2i16_reghi_vreg_zexti8:
|
||||
; GCN: s_waitcnt
|
||||
; GFX9-NEXT: ds_read_u8_d16 v1, v0
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: global_store_dword v[0:1], v1, off{{$}}
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
|
||||
; VI: ds_read_u8 v
|
||||
define void @load_local_lo_v2i16_reghi_vreg_zexti8(i8 addrspace(3)* %in, i32 %reg) #0 {
|
||||
entry:
|
||||
%reg.bc = bitcast i32 %reg to <2 x i16>
|
||||
%load = load i8, i8 addrspace(3)* %in
|
||||
%ext = zext i8 %load to i16
|
||||
%build1 = insertelement <2 x i16> %reg.bc, i16 %ext, i32 0
|
||||
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_local_lo_v2i16_reglo_vreg_zexti8:
|
||||
; GCN: s_waitcnt
|
||||
; GFX9: ds_read_u8 v
|
||||
; GFX9: global_store_dword
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
|
||||
; VI: ds_read_u8 v
|
||||
define void @load_local_lo_v2i16_reglo_vreg_zexti8(i8 addrspace(3)* %in, i16 %reg) #0 {
|
||||
entry:
|
||||
%load = load i8, i8 addrspace(3)* %in
|
||||
%ext = zext i8 %load to i16
|
||||
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 1
|
||||
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 0
|
||||
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_local_lo_v2i16_reghi_vreg_sexti8:
|
||||
; GCN: s_waitcnt
|
||||
; GFX9-NEXT: ds_read_i8_d16 v1, v0
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: global_store_dword v[0:1], v1, off{{$}}
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
|
||||
; VI: ds_read_i8 v
|
||||
define void @load_local_lo_v2i16_reghi_vreg_sexti8(i8 addrspace(3)* %in, i32 %reg) #0 {
|
||||
entry:
|
||||
%reg.bc = bitcast i32 %reg to <2 x i16>
|
||||
%load = load i8, i8 addrspace(3)* %in
|
||||
%ext = sext i8 %load to i16
|
||||
%build1 = insertelement <2 x i16> %reg.bc, i16 %ext, i32 0
|
||||
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_local_lo_v2i16_reglo_vreg_sexti8:
|
||||
; GCN: s_waitcnt
|
||||
; GFX9: ds_read_i8 v
|
||||
; GFX9: v_and_b32_e32 v{{[0-9]+}}, 0xffff, v{{[0-9]+}}
|
||||
; GFX9: v_lshl_or_b32 v{{[0-9]+}}, v{{[0-9]+}}, 16, v{{[0-9]+}}
|
||||
|
||||
; VI: ds_read_i8 v
|
||||
define void @load_local_lo_v2i16_reglo_vreg_sexti8(i8 addrspace(3)* %in, i16 %reg) #0 {
|
||||
entry:
|
||||
%load = load i8, i8 addrspace(3)* %in
|
||||
%ext = sext i8 %load to i16
|
||||
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 1
|
||||
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 0
|
||||
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_global_lo_v2i16_reglo_vreg:
|
||||
; GCN: s_waitcnt
|
||||
; GFX9-NEXT: global_load_short_d16 v2, v[0:1], off offset:-4094
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: global_store_dword
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
define void @load_global_lo_v2i16_reglo_vreg(i16 addrspace(1)* %in, i32 %reg) #0 {
|
||||
entry:
|
||||
%reg.bc = bitcast i32 %reg to <2 x i16>
|
||||
%gep = getelementptr inbounds i16, i16 addrspace(1)* %in, i64 -2047
|
||||
%load = load i16, i16 addrspace(1)* %gep
|
||||
%build1 = insertelement <2 x i16> %reg.bc, i16 %load, i32 0
|
||||
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_global_lo_v2f16_reglo_vreg:
|
||||
; GCN: s_waitcnt
|
||||
; GFX9-NEXT: global_load_short_d16 v2, v[0:1], off offset:-4094
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: global_store_dword
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
define void @load_global_lo_v2f16_reglo_vreg(half addrspace(1)* %in, i32 %reg) #0 {
|
||||
entry:
|
||||
%reg.bc = bitcast i32 %reg to <2 x half>
|
||||
%gep = getelementptr inbounds half, half addrspace(1)* %in, i64 -2047
|
||||
%load = load half, half addrspace(1)* %gep
|
||||
%build1 = insertelement <2 x half> %reg.bc, half %load, i32 0
|
||||
store <2 x half> %build1, <2 x half> addrspace(1)* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_global_lo_v2i16_reglo_vreg_zexti8:
|
||||
; GCN: s_waitcnt
|
||||
; GFX9-NEXT: global_load_ubyte_d16 v2, v[0:1], off offset:-4095
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: global_store_dword
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
define void @load_global_lo_v2i16_reglo_vreg_zexti8(i8 addrspace(1)* %in, i32 %reg) #0 {
|
||||
entry:
|
||||
%reg.bc = bitcast i32 %reg to <2 x i16>
|
||||
%gep = getelementptr inbounds i8, i8 addrspace(1)* %in, i64 -4095
|
||||
%load = load i8, i8 addrspace(1)* %gep
|
||||
%ext = zext i8 %load to i16
|
||||
%build1 = insertelement <2 x i16> %reg.bc, i16 %ext, i32 0
|
||||
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_global_lo_v2i16_reglo_vreg_sexti8:
|
||||
; GCN: s_waitcnt
|
||||
; GFX9-NEXT: global_load_sbyte_d16 v2, v[0:1], off offset:-4095
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: global_store_dword
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
define void @load_global_lo_v2i16_reglo_vreg_sexti8(i8 addrspace(1)* %in, i32 %reg) #0 {
|
||||
entry:
|
||||
%reg.bc = bitcast i32 %reg to <2 x i16>
|
||||
%gep = getelementptr inbounds i8, i8 addrspace(1)* %in, i64 -4095
|
||||
%load = load i8, i8 addrspace(1)* %gep
|
||||
%ext = sext i8 %load to i16
|
||||
%build1 = insertelement <2 x i16> %reg.bc, i16 %ext, i32 0
|
||||
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_flat_lo_v2i16_reghi_vreg:
|
||||
; GCN: s_waitcnt
|
||||
; GFX9-NEXT: flat_load_short_d16 v2, v[0:1]
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: global_store_dword v[0:1], v2
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
|
||||
; VI: flat_load_ushort v{{[0-9]+}}
|
||||
; VI: v_or_b32_e32
|
||||
define void @load_flat_lo_v2i16_reghi_vreg(i16 addrspace(4)* %in, i32 %reg) #0 {
|
||||
entry:
|
||||
%reg.bc = bitcast i32 %reg to <2 x i16>
|
||||
%load = load i16, i16 addrspace(4)* %in
|
||||
%build1 = insertelement <2 x i16> %reg.bc, i16 %load, i32 0
|
||||
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_flat_lo_v2f16_reghi_vreg:
|
||||
; GCN: s_waitcnt
|
||||
; GFX9-NEXT: flat_load_short_d16 v2, v[0:1]
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: global_store_dword v[0:1], v2
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
|
||||
; VI: flat_load_ushort v{{[0-9]+}}
|
||||
; VI: v_or_b32_e32
|
||||
define void @load_flat_lo_v2f16_reghi_vreg(half addrspace(4)* %in, i32 %reg) #0 {
|
||||
entry:
|
||||
%reg.bc = bitcast i32 %reg to <2 x half>
|
||||
%load = load half, half addrspace(4)* %in
|
||||
%build1 = insertelement <2 x half> %reg.bc, half %load, i32 0
|
||||
store <2 x half> %build1, <2 x half> addrspace(1)* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_flat_lo_v2i16_reglo_vreg_zexti8:
|
||||
; GCN: s_waitcnt
|
||||
; GFX9-NEXT: flat_load_ubyte_d16 v2, v[0:1]
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: global_store_dword v[0:1], v2
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
|
||||
; VI: flat_load_ubyte v{{[0-9]+}}
|
||||
; VI: v_or_b32_e32
|
||||
define void @load_flat_lo_v2i16_reglo_vreg_zexti8(i8 addrspace(4)* %in, i32 %reg) #0 {
|
||||
entry:
|
||||
%reg.bc = bitcast i32 %reg to <2 x i16>
|
||||
%load = load i8, i8 addrspace(4)* %in
|
||||
%ext = zext i8 %load to i16
|
||||
%build1 = insertelement <2 x i16> %reg.bc, i16 %ext, i32 0
|
||||
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_flat_lo_v2i16_reglo_vreg_sexti8:
|
||||
; GCN: s_waitcnt
|
||||
; GFX9-NEXT: flat_load_sbyte_d16 v2, v[0:1]
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: global_store_dword v[0:1], v2
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
|
||||
; VI: flat_load_sbyte v{{[0-9]+}}
|
||||
; VI: v_or_b32_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
||||
|
||||
define void @load_flat_lo_v2i16_reglo_vreg_sexti8(i8 addrspace(4)* %in, i32 %reg) #0 {
|
||||
entry:
|
||||
%reg.bc = bitcast i32 %reg to <2 x i16>
|
||||
%load = load i8, i8 addrspace(4)* %in
|
||||
%ext = sext i8 %load to i16
|
||||
%build1 = insertelement <2 x i16> %reg.bc, i16 %ext, i32 0
|
||||
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_private_lo_v2i16_reglo_vreg:
|
||||
; GCN: s_waitcnt
|
||||
; GFX9-NEXT: buffer_load_short_d16 v1, v0, s[0:3], s4 offen offset:4094{{$}}
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
|
||||
; VI: buffer_load_ushort v{{[0-9]+}}, v0, s[0:3], s4 offen offset:4094{{$}}
|
||||
define void @load_private_lo_v2i16_reglo_vreg(i16* %in, i32 %reg) #0 {
|
||||
entry:
|
||||
%reg.bc = bitcast i32 %reg to <2 x i16>
|
||||
%gep = getelementptr inbounds i16, i16* %in, i64 2047
|
||||
%load = load i16, i16* %gep
|
||||
%build1 = insertelement <2 x i16> %reg.bc, i16 %load, i32 0
|
||||
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_private_lo_v2i16_reghi_vreg:
|
||||
; GCN: s_waitcnt
|
||||
; GFX9-NEXT: buffer_load_ushort v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], s4 offen offset:4094{{$}}
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9: v_and_b32
|
||||
; GFX9: v_lshl_or_b32
|
||||
|
||||
; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
|
||||
; VI: buffer_load_ushort v{{[0-9]+}}, v0, s[0:3], s4 offen offset:4094{{$}}
|
||||
define void @load_private_lo_v2i16_reghi_vreg(i16* %in, i16 %reg) #0 {
|
||||
entry:
|
||||
%gep = getelementptr inbounds i16, i16* %in, i64 2047
|
||||
%load = load i16, i16* %gep
|
||||
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 1
|
||||
%build1 = insertelement <2 x i16> %build0, i16 %load, i32 0
|
||||
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_private_lo_v2f16_reglo_vreg:
|
||||
; GCN: s_waitcnt
|
||||
; GFX9-NEXT: buffer_load_short_d16 v1, v0, s[0:3], s4 offen offset:4094{{$}}
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
|
||||
; VI: buffer_load_ushort v{{[0-9]+}}, v0, s[0:3], s4 offen offset:4094{{$}}
|
||||
define void @load_private_lo_v2f16_reglo_vreg(half* %in, i32 %reg) #0 {
|
||||
entry:
|
||||
%reg.bc = bitcast i32 %reg to <2 x half>
|
||||
%gep = getelementptr inbounds half, half* %in, i64 2047
|
||||
%load = load half, half* %gep
|
||||
%build1 = insertelement <2 x half> %reg.bc, half %load, i32 0
|
||||
store <2 x half> %build1, <2 x half> addrspace(1)* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_private_lo_v2i16_reglo_vreg_nooff:
|
||||
; GCN: s_waitcnt
|
||||
; GFX9-NEXT: buffer_load_short_d16 v1, off, s[0:3], s4 offset:4094{{$}}
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
|
||||
; VI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s4 offset:4094{{$}}
|
||||
define void @load_private_lo_v2i16_reglo_vreg_nooff(i16* %in, i32 %reg) #0 {
|
||||
entry:
|
||||
%reg.bc = bitcast i32 %reg to <2 x i16>
|
||||
%load = load volatile i16, i16* inttoptr (i32 4094 to i16*)
|
||||
%build1 = insertelement <2 x i16> %reg.bc, i16 %load, i32 0
|
||||
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_private_lo_v2i16_reghi_vreg_nooff:
|
||||
; GCN: s_waitcnt
|
||||
; GFX9-NEXT: buffer_load_short_d16 v1, off, s[0:3], s4 offset:4094{{$}}
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
|
||||
; VI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s4 offset:4094{{$}}
|
||||
define void @load_private_lo_v2i16_reghi_vreg_nooff(i16* %in, i32 %reg) #0 {
|
||||
entry:
|
||||
%reg.bc = bitcast i32 %reg to <2 x i16>
|
||||
%load = load volatile i16, i16* inttoptr (i32 4094 to i16*)
|
||||
%build1 = insertelement <2 x i16> %reg.bc, i16 %load, i32 0
|
||||
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_private_lo_v2f16_reglo_vreg_nooff:
|
||||
; GCN: s_waitcnt
|
||||
; GFX9-NEXT: buffer_load_short_d16 v1, off, s[0:3], s4 offset:4094{{$}}
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
|
||||
; VI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s4 offset:4094{{$}}
|
||||
define void @load_private_lo_v2f16_reglo_vreg_nooff(half* %in, i32 %reg) #0 {
|
||||
entry:
|
||||
%reg.bc = bitcast i32 %reg to <2 x half>
|
||||
%load = load volatile half, half* inttoptr (i32 4094 to half*)
|
||||
%build1 = insertelement <2 x half> %reg.bc, half %load, i32 0
|
||||
store <2 x half> %build1, <2 x half> addrspace(1)* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_private_lo_v2i16_reglo_vreg_zexti8:
|
||||
; GCN: s_waitcnt
|
||||
; GFX9-NEXT: buffer_load_ubyte_d16 v1, v0, s[0:3], s4 offen offset:2047{{$}}
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
|
||||
; VI: buffer_load_ubyte v{{[0-9]+}}, v0, s[0:3], s4 offen offset:2047{{$}}
|
||||
define void @load_private_lo_v2i16_reglo_vreg_zexti8(i8* %in, i32 %reg) #0 {
|
||||
entry:
|
||||
%reg.bc = bitcast i32 %reg to <2 x i16>
|
||||
%gep = getelementptr inbounds i8, i8* %in, i64 2047
|
||||
%load = load i8, i8* %gep
|
||||
%ext = zext i8 %load to i16
|
||||
%build1 = insertelement <2 x i16> %reg.bc, i16 %ext, i32 0
|
||||
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_private_lo_v2i16_reglo_vreg_sexti8:
|
||||
; GCN: s_waitcnt
|
||||
; GFX9-NEXT: buffer_load_sbyte_d16 v1, v0, s[0:3], s4 offen offset:2047{{$}}
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
|
||||
; VI: buffer_load_sbyte v{{[0-9]+}}, v0, s[0:3], s4 offen offset:2047{{$}}
|
||||
define void @load_private_lo_v2i16_reglo_vreg_sexti8(i8* %in, i32 %reg) #0 {
|
||||
entry:
|
||||
%reg.bc = bitcast i32 %reg to <2 x i16>
|
||||
%gep = getelementptr inbounds i8, i8* %in, i64 2047
|
||||
%load = load i8, i8* %gep
|
||||
%ext = sext i8 %load to i16
|
||||
%build1 = insertelement <2 x i16> %reg.bc, i16 %ext, i32 0
|
||||
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_private_lo_v2i16_reglo_vreg_nooff_zexti8:
|
||||
; GCN: s_waitcnt
|
||||
; GFX9-NEXT: buffer_load_ubyte_d16 v1, off, s[0:3], s4 offset:4094{{$}}
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
|
||||
; VI: buffer_load_ubyte v0, off, s[0:3], s4 offset:4094{{$}}
|
||||
define void @load_private_lo_v2i16_reglo_vreg_nooff_zexti8(i8* %in, i32 %reg) #0 {
|
||||
entry:
|
||||
%reg.bc = bitcast i32 %reg to <2 x i16>
|
||||
%load = load volatile i8, i8* inttoptr (i32 4094 to i8*)
|
||||
%ext = zext i8 %load to i16
|
||||
%build1 = insertelement <2 x i16> %reg.bc, i16 %ext, i32 0
|
||||
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_private_lo_v2i16_reglo_vreg_nooff_sexti8:
|
||||
; GCN: s_waitcnt
|
||||
; GFX9-NEXT: buffer_load_sbyte_d16 v1, off, s[0:3], s4 offset:4094{{$}}
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
|
||||
; VI: buffer_load_sbyte v0, off, s[0:3], s4 offset:4094{{$}}
|
||||
define void @load_private_lo_v2i16_reglo_vreg_nooff_sexti8(i8* %in, i32 %reg) #0 {
|
||||
entry:
|
||||
%reg.bc = bitcast i32 %reg to <2 x i16>
|
||||
%load = load volatile i8, i8* inttoptr (i32 4094 to i8*)
|
||||
%ext = sext i8 %load to i16
|
||||
%build1 = insertelement <2 x i16> %reg.bc, i16 %ext, i32 0
|
||||
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_private_lo_v2f16_reglo_vreg_nooff_zexti8:
|
||||
; GCN: s_waitcnt
|
||||
; GFX9-NEXT: buffer_load_ubyte_d16 v1, off, s[0:3], s4 offset:4094{{$}}
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
|
||||
; VI: buffer_load_ubyte v0, off, s[0:3], s4 offset:4094{{$}}
|
||||
define void @load_private_lo_v2f16_reglo_vreg_nooff_zexti8(i8* %in, i32 %reg) #0 {
|
||||
entry:
|
||||
%reg.bc = bitcast i32 %reg to <2 x half>
|
||||
%load = load volatile i8, i8* inttoptr (i32 4094 to i8*)
|
||||
%ext = zext i8 %load to i16
|
||||
%bc.ext = bitcast i16 %ext to half
|
||||
%build1 = insertelement <2 x half> %reg.bc, half %bc.ext, i32 0
|
||||
store <2 x half> %build1, <2 x half> addrspace(1)* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_constant_lo_v2i16_reglo_vreg:
|
||||
; GCN: s_waitcnt
|
||||
; GFX9-NEXT: global_load_short_d16 v2, v[0:1], off offset:-4094
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: global_store_dword
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
|
||||
; VI: flat_load_ushort
|
||||
define void @load_constant_lo_v2i16_reglo_vreg(i16 addrspace(2)* %in, i32 %reg) #0 {
|
||||
entry:
|
||||
%reg.bc = bitcast i32 %reg to <2 x i16>
|
||||
%gep = getelementptr inbounds i16, i16 addrspace(2)* %in, i64 -2047
|
||||
%load = load i16, i16 addrspace(2)* %gep
|
||||
%build1 = insertelement <2 x i16> %reg.bc, i16 %load, i32 0
|
||||
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: load_constant_lo_v2f16_reglo_vreg
|
||||
; GCN: s_waitcnt
|
||||
; GFX9-NEXT: global_load_short_d16 v2, v[0:1], off offset:-4094
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: global_store_dword
|
||||
; GFX9-NEXT: s_waitcnt
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
|
||||
; VI: flat_load_ushort
|
||||
define void @load_constant_lo_v2f16_reglo_vreg(half addrspace(2)* %in, i32 %reg) #0 {
|
||||
entry:
|
||||
%reg.bc = bitcast i32 %reg to <2 x half>
|
||||
%gep = getelementptr inbounds half, half addrspace(2)* %in, i64 -2047
|
||||
%load = load half, half addrspace(2)* %gep
|
||||
%build1 = insertelement <2 x half> %reg.bc, half %load, i32 0
|
||||
store <2 x half> %build1, <2 x half> addrspace(1)* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
Loading…
Reference in New Issue
Block a user