RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-22 18:54:02 +01:00
Code Issues Projects Releases Wiki Activity

[AMDGPU] Pre-commit global-isel test case for D106451

Browse Source 
This test case shows the scheduler wrongly reordering two buffer
accesses that might alias.
This commit is contained in:
Jay Foad 2021-07-21 11:29:04 +01:00
parent 7f0f3d6b7b
commit eaeb8d4f70
1 changed files with 22 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
test/CodeGen/AMDGPU/GlobalISel/buffer-schedule.ll Normal file
View File

@ -0,0 +1,22 @@
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s
; FIXME: the first load and store should not be reordered because they might
; alias depending on the value of %off
; GCN-LABEL: {{^}}test1:
; GCN: buffer_load_dword
; GCN: buffer_store_dword
; GCN: buffer_store_dword
define amdgpu_cs void @test1(<4 x i32> inreg %buf, i32 %off) {
.entry:
call void @llvm.amdgcn.raw.buffer.store.i32(i32 0, <4 x i32> %buf, i32 8, i32 0, i32 0)
%val = call i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32> %buf, i32 %off, i32 0, i32 0)
call void @llvm.amdgcn.raw.buffer.store.i32(i32 %val, <4 x i32> %buf, i32 0, i32 0, i32 0)
ret void
}
declare i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32>, i32, i32, i32) #2
declare void @llvm.amdgcn.raw.buffer.store.i32(i32, <4 x i32>, i32, i32, i32) #3
attributes #2 = { nounwind readonly }
attributes #3 = { nounwind writeonly }