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Add latency info for Exynos interleaved Load/Store instructions.
llvm-svn: 304259
This commit is contained in:
Abderrazek Zaafrani
parent
3ec46e95c4
commit
eb1c576449
@ -23,7 +23,7 @@ def ExynosM1Model : SchedMachineModel {
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let LoopMicroOpBufferSize = 24; // Based on the instruction queue size.
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let LoadLatency = 4; // Optimistic load cases.
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let MispredictPenalty = 14; // Minimum branch misprediction penalty.
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let CompleteModel = 0; // Use the default model otherwise.
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let CompleteModel = 1; // Use the default model otherwise.
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}
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//===----------------------------------------------------------------------===//
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@ -72,14 +72,14 @@ def M1WriteC2 : SchedWriteRes<[M1UnitC]> { let Latency = 2; }
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def M1WriteB1 : SchedWriteRes<[M1UnitB]> { let Latency = 1; }
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def M1WriteL5 : SchedWriteRes<[M1UnitL]> { let Latency = 5; }
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def M1WriteLA : SchedWriteVariant<[SchedVar<ScaledIdxPred, [M1WriteL5,
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def M1WriteLX : SchedWriteVariant<[SchedVar<ScaledIdxPred, [M1WriteL5,
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M1WriteA1]>,
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SchedVar<NoSchedPred, [M1WriteL5]>]>;
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def M1WriteS1 : SchedWriteRes<[M1UnitS]> { let Latency = 1; }
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def M1WriteS2 : SchedWriteRes<[M1UnitS]> { let Latency = 2; }
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def M1WriteS4 : SchedWriteRes<[M1UnitS]> { let Latency = 4; }
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def M1WriteSA : SchedWriteVariant<[SchedVar<ScaledIdxPred, [M1WriteS2,
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def M1WriteSX : SchedWriteVariant<[SchedVar<ScaledIdxPred, [M1WriteS2,
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M1WriteA1]>,
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SchedVar<NoSchedPred, [M1WriteS1]>]>;
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@ -125,13 +125,13 @@ def : WriteRes<WriteAdr, []> { let Latency = 0; }
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// Load instructions.
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def : WriteRes<WriteLD, [M1UnitL]> { let Latency = 4; }
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def : WriteRes<WriteLDHi, [M1UnitALU]> { let Latency = 4; }
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def : SchedAlias<WriteLDIdx, M1WriteLA>;
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def : SchedAlias<WriteLDIdx, M1WriteLX>;
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// Store instructions.
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def : WriteRes<WriteST, [M1UnitS]> { let Latency = 1; }
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def : WriteRes<WriteSTP, [M1UnitS]> { let Latency = 1; }
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def : WriteRes<WriteSTX, [M1UnitS]> { let Latency = 1; }
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def : SchedAlias<WriteSTIdx, M1WriteSA>;
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def : SchedAlias<WriteSTIdx, M1WriteSX>;
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// FP data instructions.
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def : WriteRes<WriteF, [M1UnitFADD]> { let Latency = 3; }
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@ -231,6 +231,111 @@ def M1WriteNMISC3 : SchedWriteRes<[M1UnitNMISC]> { let Latency = 3; }
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def M1WriteNMISC4 : SchedWriteRes<[M1UnitNMISC]> { let Latency = 4; }
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def M1WriteTB : SchedWriteRes<[M1UnitC,
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M1UnitALU]> { let Latency = 2; }
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def M1WriteVLDA : SchedWriteRes<[M1UnitL,
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M1UnitL]> { let Latency = 6; }
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def M1WriteVLDB : SchedWriteRes<[M1UnitL,
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M1UnitL,
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M1UnitL]> { let Latency = 7; }
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def M1WriteVLDC : SchedWriteRes<[M1UnitL,
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M1UnitL,
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M1UnitL,
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M1UnitL]> { let Latency = 8; }
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def M1WriteVLDD : SchedWriteRes<[M1UnitL,
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M1UnitNALU]> { let Latency = 7;
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let ResourceCycles = [2]; }
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def M1WriteVLDE : SchedWriteRes<[M1UnitL,
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M1UnitNALU]> { let Latency = 6; }
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def M1WriteVLDF : SchedWriteRes<[M1UnitL,
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M1UnitL]> { let Latency = 10;
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let ResourceCycles = [5]; }
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def M1WriteVLDG : SchedWriteRes<[M1UnitL,
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M1UnitNALU,
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M1UnitNALU]> { let Latency = 7;
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let ResourceCycles = [2]; }
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def M1WriteVLDH : SchedWriteRes<[M1UnitL,
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M1UnitNALU,
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M1UnitNALU]> { let Latency = 6; }
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def M1WriteVLDI : SchedWriteRes<[M1UnitL,
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M1UnitL,
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M1UnitL]> { let Latency = 12;
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let ResourceCycles = [6]; }
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def M1WriteVLDJ : SchedWriteRes<[M1UnitL,
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M1UnitNALU,
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M1UnitNALU,
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M1UnitNALU]> { let Latency = 9;
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let ResourceCycles = [4]; }
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def M1WriteVLDK : SchedWriteRes<[M1UnitL,
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M1UnitNALU,
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M1UnitNALU,
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M1UnitNALU,
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M1UnitNALU]> { let Latency = 9;
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let ResourceCycles = [4]; }
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def M1WriteVLDL : SchedWriteRes<[M1UnitL,
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M1UnitNALU,
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M1UnitNALU,
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M1UnitNALU]> { let Latency = 7;
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let ResourceCycles = [2]; }
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def M1WriteVLDM : SchedWriteRes<[M1UnitL,
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M1UnitNALU,
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M1UnitNALU,
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M1UnitNALU,
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M1UnitNALU]> { let Latency = 7;
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let ResourceCycles = [2]; }
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def M1WriteVLDN : SchedWriteRes<[M1UnitL,
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M1UnitL,
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M1UnitL,
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M1UnitL]> { let Latency = 14;
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let ResourceCycles = [7]; }
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def M1WriteVSTA : WriteSequence<[WriteVST], 2>;
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def M1WriteVSTB : WriteSequence<[WriteVST], 3>;
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def M1WriteVSTC : WriteSequence<[WriteVST], 4>;
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def M1WriteVSTD : SchedWriteRes<[M1UnitS,
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M1UnitFST,
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M1UnitFST]> { let Latency = 7;
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let ResourceCycles = [7]; }
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def M1WriteVSTE : SchedWriteRes<[M1UnitS,
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M1UnitFST,
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M1UnitS,
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M1UnitFST,
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M1UnitFST]> { let Latency = 8;
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let ResourceCycles = [8]; }
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def M1WriteVSTF : SchedWriteRes<[M1UnitNALU,
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M1UnitS,
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M1UnitFST,
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M1UnitS,
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M1UnitFST,
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M1UnitFST,
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M1UnitFST]> { let Latency = 15;
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let ResourceCycles = [15]; }
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def M1WriteVSTG : SchedWriteRes<[M1UnitNALU,
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M1UnitS,
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M1UnitFST,
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M1UnitS,
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M1UnitFST,
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M1UnitS,
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M1UnitFST,
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M1UnitFST,
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M1UnitFST]> { let Latency = 16;
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let ResourceCycles = [16]; }
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def M1WriteVSTH : SchedWriteRes<[M1UnitNALU,
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M1UnitS,
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M1UnitFST,
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M1UnitFST,
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M1UnitFST]> { let Latency = 14;
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let ResourceCycles = [14]; }
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def M1WriteVSTI : SchedWriteRes<[M1UnitNALU,
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M1UnitS,
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M1UnitFST,
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M1UnitS,
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M1UnitFST,
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M1UnitS,
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M1UnitFST,
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M1UnitS,
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M1UnitFST,
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M1UnitFST,
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M1UnitFST]> { let Latency = 17;
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let ResourceCycles = [17]; }
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// Branch instructions
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def : InstRW<[M1WriteB1], (instrs Bcc)>;
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@ -360,8 +465,233 @@ def : InstRW<[M1WriteNALU2], (instregex "^(TRN|UZP)[12](v16i8|v8i16|v4i32|v2i64
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def : InstRW<[M1WriteNALU1], (instregex "^ZIP[12]v")>;
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// ASIMD load instructions.
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def : InstRW<[M1WriteVLDD], (instregex "LD1i(8|16|32)$")>;
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def : InstRW<[M1WriteVLDD,
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WriteAdr], (instregex "LD1i(8|16|32)_POST$")>;
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def : InstRW<[M1WriteVLDE], (instregex "LD1i(64)$")>;
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def : InstRW<[M1WriteVLDE,
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WriteAdr], (instregex "LD1i(64)_POST$")>;
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def : InstRW<[M1WriteL5], (instregex "LD1Rv(8b|4h|2s)$")>;
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def : InstRW<[M1WriteL5,
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WriteAdr], (instregex "LD1Rv(8b|4h|2s)_POST$")>;
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def : InstRW<[M1WriteL5], (instregex "LD1Rv(1d)$")>;
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def : InstRW<[M1WriteL5,
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WriteAdr], (instregex "LD1Rv(1d)_POST$")>;
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def : InstRW<[M1WriteL5], (instregex "LD1Rv(16b|8h|4s|2d)$")>;
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def : InstRW<[M1WriteL5,
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WriteAdr], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>;
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def : InstRW<[M1WriteL5], (instregex "LD1Onev(8b|4h|2s|1d)$")>;
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def : InstRW<[M1WriteL5,
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WriteAdr], (instregex "LD1Onev(8b|4h|2s|1d)_POST$")>;
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def : InstRW<[M1WriteL5], (instregex "LD1Onev(16b|8h|4s|2d)$")>;
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def : InstRW<[M1WriteL5,
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WriteAdr], (instregex "LD1Onev(16b|8h|4s|2d)_POST$")>;
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def : InstRW<[M1WriteVLDA], (instregex "LD1Twov(8b|4h|2s|1d)$")>;
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def : InstRW<[M1WriteVLDA,
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WriteAdr], (instregex "LD1Twov(8b|4h|2s|1d)_POST$")>;
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def : InstRW<[M1WriteVLDA], (instregex "LD1Twov(16b|8h|4s|2d)$")>;
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def : InstRW<[M1WriteVLDA,
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WriteAdr], (instregex "LD1Twov(16b|8h|4s|2d)_POST$")>;
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def : InstRW<[M1WriteVLDB], (instregex "LD1Threev(8b|4h|2s|1d)$")>;
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def : InstRW<[M1WriteVLDB,
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WriteAdr], (instregex "LD1Threev(8b|4h|2s|1d)_POST$")>;
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def : InstRW<[M1WriteVLDB], (instregex "LD1Threev(16b|8h|4s|2d)$")>;
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def : InstRW<[M1WriteVLDB,
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WriteAdr], (instregex "LD1Threev(16b|8h|4s|2d)_POST$")>;
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def : InstRW<[M1WriteVLDC], (instregex "LD1Fourv(8b|4h|2s|1d)$")>;
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def : InstRW<[M1WriteVLDC,
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WriteAdr], (instregex "LD1Fourv(8b|4h|2s|1d)_POST$")>;
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def : InstRW<[M1WriteVLDC], (instregex "LD1Fourv(16b|8h|4s|2d)$")>;
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def : InstRW<[M1WriteVLDC,
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WriteAdr], (instregex "LD1Fourv(16b|8h|4s|2d)_POST$")>;
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def : InstRW<[M1WriteVLDG], (instregex "LD2i(8|16)$")>;
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def : InstRW<[M1WriteVLDG,
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WriteAdr], (instregex "LD2i(8|16)_POST$")>;
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def : InstRW<[M1WriteVLDG], (instregex "LD2i(32)$")>;
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def : InstRW<[M1WriteVLDG,
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WriteAdr], (instregex "LD2i(32)_POST$")>;
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def : InstRW<[M1WriteVLDH], (instregex "LD2i(64)$")>;
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def : InstRW<[M1WriteVLDH,
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WriteAdr], (instregex "LD2i(64)_POST$")>;
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def : InstRW<[M1WriteVLDA], (instregex "LD2Rv(8b|4h|2s)$")>;
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def : InstRW<[M1WriteVLDA,
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WriteAdr], (instregex "LD2Rv(8b|4h|2s)_POST$")>;
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def : InstRW<[M1WriteVLDA], (instregex "LD2Rv(1d)$")>;
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def : InstRW<[M1WriteVLDA,
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WriteAdr], (instregex "LD2Rv(1d)_POST$")>;
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def : InstRW<[M1WriteVLDA], (instregex "LD2Rv(16b|8h|4s|2d)$")>;
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def : InstRW<[M1WriteVLDA,
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WriteAdr], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>;
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def : InstRW<[M1WriteVLDF], (instregex "LD2Twov(8b|4h|2s)$")>;
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def : InstRW<[M1WriteVLDF,
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WriteAdr], (instregex "LD2Twov(8b|4h|2s)_POST$")>;
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def : InstRW<[M1WriteVLDF], (instregex "LD2Twov(16b|8h|4s)$")>;
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def : InstRW<[M1WriteVLDF,
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WriteAdr], (instregex "LD2Twov(16b|8h|4s)_POST$")>;
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def : InstRW<[M1WriteVLDF], (instregex "LD2Twov(2d)$")>;
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def : InstRW<[M1WriteVLDF,
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WriteAdr], (instregex "LD2Twov(2d)_POST$")>;
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def : InstRW<[M1WriteVLDJ], (instregex "LD3i(8|16)$")>;
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def : InstRW<[M1WriteVLDJ,
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WriteAdr], (instregex "LD3i(8|16)_POST$")>;
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def : InstRW<[M1WriteVLDJ], (instregex "LD3i(32)$")>;
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def : InstRW<[M1WriteVLDJ,
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WriteAdr], (instregex "LD3i(32)_POST$")>;
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def : InstRW<[M1WriteVLDL], (instregex "LD3i(64)$")>;
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def : InstRW<[M1WriteVLDL,
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WriteAdr], (instregex "LD3i(64)_POST$")>;
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def : InstRW<[M1WriteVLDB], (instregex "LD3Rv(8b|4h|2s)$")>;
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def : InstRW<[M1WriteVLDB,
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WriteAdr], (instregex "LD3Rv(8b|4h|2s)_POST$")>;
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def : InstRW<[M1WriteVLDB], (instregex "LD3Rv(1d)$")>;
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def : InstRW<[M1WriteVLDB,
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WriteAdr], (instregex "LD3Rv(1d)_POST$")>;
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def : InstRW<[M1WriteVLDB], (instregex "LD3Rv(16b|8h|4s)$")>;
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def : InstRW<[M1WriteVLDB,
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WriteAdr], (instregex "LD3Rv(16b|8h|4s)_POST$")>;
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def : InstRW<[M1WriteVLDB], (instregex "LD3Rv(2d)$")>;
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def : InstRW<[M1WriteVLDB,
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WriteAdr], (instregex "LD3Rv(2d)_POST$")>;
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def : InstRW<[M1WriteVLDI], (instregex "LD3Threev(8b|4h|2s)$")>;
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def : InstRW<[M1WriteVLDI,
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WriteAdr], (instregex "LD3Threev(8b|4h|2s)_POST$")>;
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def : InstRW<[M1WriteVLDI], (instregex "LD3Threev(16b|8h|4s)$")>;
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def : InstRW<[M1WriteVLDI,
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WriteAdr], (instregex "LD3Threev(16b|8h|4s)_POST$")>;
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def : InstRW<[M1WriteVLDI], (instregex "LD3Threev(2d)$")>;
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def : InstRW<[M1WriteVLDI,
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WriteAdr], (instregex "LD3Threev(2d)_POST$")>;
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def : InstRW<[M1WriteVLDK], (instregex "LD4i(8|16)$")>;
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def : InstRW<[M1WriteVLDK,
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WriteAdr], (instregex "LD4i(8|16)_POST$")>;
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def : InstRW<[M1WriteVLDK], (instregex "LD4i(32)$")>;
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def : InstRW<[M1WriteVLDK,
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WriteAdr], (instregex "LD4i(32)_POST$")>;
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def : InstRW<[M1WriteVLDM], (instregex "LD4i(64)$")>;
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def : InstRW<[M1WriteVLDM,
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WriteAdr], (instregex "LD4i(64)_POST$")>;
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def : InstRW<[M1WriteVLDC], (instregex "LD4Rv(8b|4h|2s)$")>;
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def : InstRW<[M1WriteVLDC,
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WriteAdr], (instregex "LD4Rv(8b|4h|2s)_POST$")>;
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def : InstRW<[M1WriteVLDC], (instregex "LD4Rv(1d)$")>;
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def : InstRW<[M1WriteVLDC,
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WriteAdr], (instregex "LD4Rv(1d)_POST$")>;
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def : InstRW<[M1WriteVLDC], (instregex "LD4Rv(16b|8h|4s)$")>;
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def : InstRW<[M1WriteVLDC,
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WriteAdr], (instregex "LD4Rv(16b|8h|4s)_POST$")>;
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def : InstRW<[M1WriteVLDC], (instregex "LD4Rv(2d)$")>;
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def : InstRW<[M1WriteVLDC,
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WriteAdr], (instregex "LD4Rv(2d)_POST$")>;
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def : InstRW<[M1WriteVLDN], (instregex "LD4Fourv(8b|4h|2s)$")>;
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def : InstRW<[M1WriteVLDN,
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WriteAdr], (instregex "LD4Fourv(8b|4h|2s)_POST$")>;
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def : InstRW<[M1WriteVLDN], (instregex "LD4Fourv(16b|8h|4s)$")>;
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def : InstRW<[M1WriteVLDN,
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WriteAdr], (instregex "LD4Fourv(16b|8h|4s)_POST$")>;
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def : InstRW<[M1WriteVLDN], (instregex "LD4Fourv(2d)$")>;
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def : InstRW<[M1WriteVLDN,
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WriteAdr], (instregex "LD4Fourv(2d)_POST$")>;
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// ASIMD store instructions.
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def : InstRW<[M1WriteVSTD], (instregex "ST1i(8|16|32)$")>;
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def : InstRW<[M1WriteVSTD,
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WriteAdr], (instregex "ST1i(8|16|32)_POST$")>;
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def : InstRW<[M1WriteVSTD], (instregex "ST1i(64)$")>;
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def : InstRW<[M1WriteVSTD,
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WriteAdr], (instregex "ST1i(64)_POST$")>;
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def : InstRW<[WriteVST], (instregex "ST1Onev(8b|4h|2s|1d)$")>;
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def : InstRW<[WriteVST,
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WriteAdr], (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>;
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def : InstRW<[WriteVST], (instregex "ST1Onev(16b|8h|4s|2d)$")>;
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def : InstRW<[WriteVST,
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WriteAdr], (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>;
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def : InstRW<[M1WriteVSTA], (instregex "ST1Twov(8b|4h|2s|1d)$")>;
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def : InstRW<[M1WriteVSTA,
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WriteAdr], (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>;
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def : InstRW<[M1WriteVSTA], (instregex "ST1Twov(16b|8h|4s|2d)$")>;
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def : InstRW<[M1WriteVSTA,
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WriteAdr], (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>;
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def : InstRW<[M1WriteVSTB], (instregex "ST1Threev(8b|4h|2s|1d)$")>;
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def : InstRW<[M1WriteVSTB,
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WriteAdr], (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>;
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def : InstRW<[M1WriteVSTB], (instregex "ST1Threev(16b|8h|4s|2d)$")>;
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def : InstRW<[M1WriteVSTB,
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WriteAdr], (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>;
|
||||
def : InstRW<[M1WriteVSTC], (instregex "ST1Fourv(8b|4h|2s|1d)$")>;
|
||||
def : InstRW<[M1WriteVSTC,
|
||||
WriteAdr], (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>;
|
||||
def : InstRW<[M1WriteVSTC], (instregex "ST1Fourv(16b|8h|4s|2d)$")>;
|
||||
def : InstRW<[M1WriteVSTC,
|
||||
WriteAdr], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>;
|
||||
|
||||
def : InstRW<[M1WriteVSTD], (instregex "ST2i(8|16|32)$")>;
|
||||
def : InstRW<[M1WriteVSTD,
|
||||
WriteAdr], (instregex "ST2i(8|16|32)_POST$")>;
|
||||
def : InstRW<[M1WriteVSTD], (instregex "ST2i(64)$")>;
|
||||
def : InstRW<[M1WriteVSTD,
|
||||
WriteAdr], (instregex "ST2i(64)_POST$")>;
|
||||
|
||||
def : InstRW<[M1WriteVSTD], (instregex "ST2Twov(8b|4h|2s)$")>;
|
||||
def : InstRW<[M1WriteVSTD,
|
||||
WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST$")>;
|
||||
def : InstRW<[M1WriteVSTE], (instregex "ST2Twov(16b|8h|4s)$")>;
|
||||
def : InstRW<[M1WriteVSTE,
|
||||
WriteAdr], (instregex "ST2Twov(16b|8h|4s)_POST$")>;
|
||||
def : InstRW<[M1WriteVSTE], (instregex "ST2Twov(2d)$")>;
|
||||
def : InstRW<[M1WriteVSTE,
|
||||
WriteAdr], (instregex "ST2Twov(2d)_POST$")>;
|
||||
|
||||
def : InstRW<[M1WriteVSTH], (instregex "ST3i(8|16)$")>;
|
||||
def : InstRW<[M1WriteVSTH,
|
||||
WriteAdr], (instregex "ST3i(8|16)_POST$")>;
|
||||
def : InstRW<[M1WriteVSTH], (instregex "ST3i(32)$")>;
|
||||
def : InstRW<[M1WriteVSTH,
|
||||
WriteAdr], (instregex "ST3i(32)_POST$")>;
|
||||
def : InstRW<[M1WriteVSTF], (instregex "ST3i(64)$")>;
|
||||
def : InstRW<[M1WriteVSTF,
|
||||
WriteAdr], (instregex "ST3i(64)_POST$")>;
|
||||
|
||||
def : InstRW<[M1WriteVSTF], (instregex "ST3Threev(8b|4h|2s)$")>;
|
||||
def : InstRW<[M1WriteVSTF,
|
||||
WriteAdr], (instregex "ST3Threev(8b|4h|2s)_POST$")>;
|
||||
def : InstRW<[M1WriteVSTG], (instregex "ST3Threev(16b|8h|4s)$")>;
|
||||
def : InstRW<[M1WriteVSTG,
|
||||
WriteAdr], (instregex "ST3Threev(16b|8h|4s)_POST$")>;
|
||||
def : InstRW<[M1WriteVSTG], (instregex "ST3Threev(2d)$")>;
|
||||
def : InstRW<[M1WriteVSTG,
|
||||
WriteAdr], (instregex "ST3Threev(2d)_POST$")>;
|
||||
|
||||
def : InstRW<[M1WriteVSTH], (instregex "ST4i(8|16)$")>;
|
||||
def : InstRW<[M1WriteVSTH,
|
||||
WriteAdr], (instregex "ST4i(8|16)_POST$")>;
|
||||
def : InstRW<[M1WriteVSTH], (instregex "ST4i(32)$")>;
|
||||
def : InstRW<[M1WriteVSTH,
|
||||
WriteAdr], (instregex "ST4i(32)_POST$")>;
|
||||
def : InstRW<[M1WriteVSTF], (instregex "ST4i(64)$")>;
|
||||
def : InstRW<[M1WriteVSTF,
|
||||
WriteAdr], (instregex "ST4i(64)_POST$")>;
|
||||
|
||||
def : InstRW<[M1WriteVSTF], (instregex "ST4Fourv(8b|4h|2s)$")>;
|
||||
def : InstRW<[M1WriteVSTF,
|
||||
WriteAdr], (instregex "ST4Fourv(8b|4h|2s)_POST$")>;
|
||||
def : InstRW<[M1WriteVSTI], (instregex "ST4Fourv(16b|8h|4s)$")>;
|
||||
def : InstRW<[M1WriteVSTI,
|
||||
WriteAdr], (instregex "ST4Fourv(16b|8h|4s)_POST$")>;
|
||||
def : InstRW<[M1WriteVSTI], (instregex "ST4Fourv(2d)$")>;
|
||||
def : InstRW<[M1WriteVSTI,
|
||||
WriteAdr], (instregex "ST4Fourv(2d)_POST$")>;
|
||||
|
||||
// Cryptography instructions.
|
||||
def M1WriteAES : SchedWriteRes<[M1UnitNCRYPT]> { let Latency = 1; }
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user