diff --git a/lib/Target/Sparc/LeonFeatures.td b/lib/Target/Sparc/LeonFeatures.td index e0ea4e9c764..75273eff186 100644 --- a/lib/Target/Sparc/LeonFeatures.td +++ b/lib/Target/Sparc/LeonFeatures.td @@ -16,9 +16,9 @@ //support to casa instruction; for leon3 subtarget only def UMACSMACSupport : SubtargetFeature< - "hasumacsmac", - "HasUmacSmac", - "true", + "hasumacsmac", + "HasUmacSmac", + "true", "Enable UMAC and SMAC for LEON3 and LEON4 processors" >; @@ -30,9 +30,9 @@ def UMACSMACSupport : SubtargetFeature< //support to casa instruction; for leon3 subtarget only def LeonCASA : SubtargetFeature< - "hasleoncasa", - "HasLeonCasa", - "true", + "hasleoncasa", + "HasLeonCasa", + "true", "Enable CASA instruction for LEON3 and LEON4 processors" >; @@ -40,7 +40,7 @@ def InsertNOPLoad: SubtargetFeature< "insertnopload", "InsertNOPLoad", "true", - "LEON3 erratum fix: Insert a NOP instruction after every single-cycle load instruction when the next instruction is another load/store instruction" + "LEON3 erratum fix: Insert a NOP instruction after every single-cycle load instruction when the next instruction is another load/store instruction" >; def DetectRoundChange : SubtargetFeature< @@ -55,7 +55,7 @@ def FixAllFDIVSQRT : SubtargetFeature< "fixallfdivsqrt", "FixAllFDIVSQRT", "true", - "LEON erratum fix: Fix FDIVS/FDIVD/FSQRTS/FSQRTD instructions with NOPs and floating-point store" + "LEON erratum fix: Fix FDIVS/FDIVD/FSQRTS/FSQRTD instructions with NOPs and floating-point store" >; def LeonCycleCounter diff --git a/lib/Target/Sparc/Sparc.td b/lib/Target/Sparc/Sparc.td index ca6147edc46..da95602309a 100644 --- a/lib/Target/Sparc/Sparc.td +++ b/lib/Target/Sparc/Sparc.td @@ -150,7 +150,7 @@ def : Processor<"ut699", LEON3Itineraries, [FeatureLeon, InsertNOPLoad, FeatureNoFSMULD, FeatureNoFMULS, FixAllFDIVSQRT]>; // LEON3 FT (GR712RC). Provides features for the GR712RC processor. -// - covers all the erratum fixed for LEON3 and support for the CASA instruction. +// - covers all the erratum fixed for LEON3 and support for the CASA instruction. def : Processor<"gr712rc", LEON3Itineraries, [FeatureLeon, LeonCASA]>; @@ -158,9 +158,9 @@ def : Processor<"gr712rc", LEON3Itineraries, def : Processor<"leon4", LEON4Itineraries, [FeatureLeon, UMACSMACSupport, LeonCASA]>; -// LEON 4 FT (GR740) +// LEON 4 FT (GR740) // TO DO: Place-holder: Processor specific features will be added *very* soon here. -def : Processor<"gr740", LEON4Itineraries, +def : Processor<"gr740", LEON4Itineraries, [FeatureLeon, UMACSMACSupport, LeonCASA, LeonCycleCounter, FeaturePWRPSR]>; diff --git a/lib/Target/Sparc/SparcInstrAliases.td b/lib/Target/Sparc/SparcInstrAliases.td index d4d056ea0af..4a0e8c856f2 100644 --- a/lib/Target/Sparc/SparcInstrAliases.td +++ b/lib/Target/Sparc/SparcInstrAliases.td @@ -281,7 +281,7 @@ defm : int_cond_alias<"pos", 0b1110>; defm : int_cond_alias<"neg", 0b0110>; defm : int_cond_alias<"vc", 0b1111>; defm : int_cond_alias<"vs", 0b0111>; -let EmitPriority = 0 in +let EmitPriority = 0 in { defm : int_cond_alias<"", 0b1000>; // same as a; gnu asm, not in manual defm : int_cond_alias<"nz", 0b1001>; // same as ne @@ -306,7 +306,7 @@ defm : fp_cond_alias<"uge", 0b1100>; defm : fp_cond_alias<"le", 0b1101>; defm : fp_cond_alias<"ule", 0b1110>; defm : fp_cond_alias<"o", 0b1111>; -let EmitPriority = 0 in +let EmitPriority = 0 in { defm : fp_cond_alias<"", 0b1000>; // same as a; gnu asm, not in manual defm : fp_cond_alias<"nz", 0b0001>; // same as ne diff --git a/lib/Target/Sparc/SparcInstrFormats.td b/lib/Target/Sparc/SparcInstrFormats.td index fbf08b49d60..2d8f063f7ed 100644 --- a/lib/Target/Sparc/SparcInstrFormats.td +++ b/lib/Target/Sparc/SparcInstrFormats.td @@ -24,7 +24,7 @@ class InstSP pattern, let DecoderNamespace = "Sparc"; field bits<32> SoftFail = 0; - + let Itinerary = itin; } diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td index f26f4a1c1a8..e2bf647d37e 100644 --- a/lib/Target/Sparc/SparcInstrInfo.td +++ b/lib/Target/Sparc/SparcInstrInfo.td @@ -529,7 +529,7 @@ let DecoderMethod = "DecodeLoadCP", Defs = [CPSR] in { "ld [$addr], %csr", []>; } } - + let DecoderMethod = "DecodeLoadFP" in let Defs = [FSR] in { let rd = 0 in { @@ -571,12 +571,12 @@ let DecoderMethod = "DecodeStoreQFP" in defm STQF : StoreA<"stq", 0b100110, 0b110110, store, QFPRegs, f128>, Requires<[HasV9, HasHardQuad]>; -let DecoderMethod = "DecodeStoreCP" in - defm STC : Store<"st", 0b110100, store, CoprocRegs, i32>; - -let DecoderMethod = "DecodeStoreCPPair" in +let DecoderMethod = "DecodeStoreCP" in + defm STC : Store<"st", 0b110100, store, CoprocRegs, i32>; + +let DecoderMethod = "DecodeStoreCPPair" in defm STDC : Store<"std", 0b110111, store, CoprocPair, v2i32, IIC_std>; - + let DecoderMethod = "DecodeStoreCP", rd = 0 in { let Defs = [CPSR] in { def STCSRrr : F3_1<3, 0b110101, (outs MEMrr:$addr), (ins), @@ -897,7 +897,7 @@ def CBCOND : CPBranchSP<(ins brtarget:$imm22, CCOp:$cond), [(SPbrfcc bb:$imm22, imm:$cond)]>; def CBCONDA : CPBranchSPA<(ins brtarget:$imm22, CCOp:$cond), "cb$cond,a $imm22", []>; - + // Section B.24 - Call and Link Instruction, p. 125 // This is the only Format 1 instruction let Uses = [O6], @@ -1186,7 +1186,7 @@ def FABSS : F3_3u<2, 0b110100, 0b000001001, // Floating-point Square Root Instructions, p.145 // FSQRTS generates an erratum on LEON processors, so by disabling this instruction // this will be promoted to use FSQRTD with doubles instead. -let Predicates = [HasNoFdivSqrtFix] in +let Predicates = [HasNoFdivSqrtFix] in def FSQRTS : F3_3u<2, 0b110100, 0b000101001, (outs FPRegs:$rd), (ins FPRegs:$rs2), "fsqrts $rs2, $rd", @@ -1515,8 +1515,8 @@ let Predicates = [HasV9], hasSideEffects = 1, rd = 0, rs1 = 0b01111 in def MEMBARi : F3_2<2, 0b101000, (outs), (ins MembarTag:$simm13), "membar $simm13", []>; -// The CAS instruction, unlike other instructions, only comes in a -// form which requires an ASI be provided. The ASI value hardcoded +// The CAS instruction, unlike other instructions, only comes in a +// form which requires an ASI be provided. The ASI value hardcoded // here is ASI_PRIMARY, the default unprivileged ASI for SparcV9. let Predicates = [HasV9], Constraints = "$swap = $rd", asi = 0b10000000 in def CASrr: F3_1_asi<3, 0b111100, @@ -1536,18 +1536,18 @@ let Predicates = [HasLeonCASA], Constraints = "$swap = $rd", asi = 0b00001010 in "casa [$rs1] 10, $rs2, $rd", [(set i32:$rd, (atomic_cmp_swap_32 iPTR:$rs1, i32:$rs2, i32:$swap))]>; - + // CASA supported on some LEON3 and all LEON4 processors. Same pattern as // CASrr, above, but with a different ASI. This version is supported for -// inline assembly lowering only. +// inline assembly lowering only. let Predicates = [HasLeonCASA], Constraints = "$swap = $rd" in def CASArr: F3_1_asi<3, 0b111100, (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, IntRegs:$swap, i8imm:$asi), "casa [$rs1] $asi, $rs2, $rd", []>; - + // TODO: Add DAG sequence to lower these instructions. Currently, only provided -// as inline assembler-supported instructions. +// as inline assembler-supported instructions. let Predicates = [HasUMAC_SMAC], Defs = [Y, ASR18], Uses = [Y, ASR18] in { def SMACrr : F3_1<2, 0b111111, (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, ASRRegs:$asr18), @@ -1558,12 +1558,12 @@ let Predicates = [HasUMAC_SMAC], Defs = [Y, ASR18], Uses = [Y, ASR18] in { (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13, ASRRegs:$asr18), "smac $rs1, $simm13, $rd", [], IIC_smac_umac>; - + def UMACrr : F3_1<2, 0b111110, (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, ASRRegs:$asr18), "umac $rs1, $rs2, $rd", [], IIC_smac_umac>; - + def UMACri : F3_2<2, 0b111110, (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13, ASRRegs:$asr18), "umac $rs1, $simm13, $rd", diff --git a/lib/Target/Sparc/SparcRegisterInfo.td b/lib/Target/Sparc/SparcRegisterInfo.td index 98959d51295..8225bc21e8f 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.td +++ b/lib/Target/Sparc/SparcRegisterInfo.td @@ -359,14 +359,14 @@ let isAllocatable = 0 in { // Ancillary state registers def ASRRegs : RegisterClass<"SP", [i32], 32, (add Y, (sequence "ASR%u", 1, 31))>; - + // This register class should not be used to hold i64 values. def CoprocRegs : RegisterClass<"SP", [i32], 32, (add (sequence "C%u", 0, 31))>; // Should be in the same order as CoprocRegs. def CoprocPair : RegisterClass<"SP", [v2i32], 64, - (add C0_C1, C2_C3, C4_C5, C6_C7, + (add C0_C1, C2_C3, C4_C5, C6_C7, C8_C9, C10_C11, C12_C13, C14_C15, C16_C17, C18_C19, C20_C21, C22_C23, C24_C25, C26_C27, C28_C29, C30_C31)>;