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[ValueTracking] Handle more non-trivial conditions in isKnownNonZero()

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In 35676a4f9a536a2aab768af63ddbb15bc722d7f9 I've added handling for
non-trivial dominating conditions that imply non-zero on the true
branch. This adds the same support for the false branch.

The changes in pr45360.ll change block ordering and naming, but
don't change the control flow. The urem is still guaraded by a
non-zero check correctly.
This commit is contained in:
Nikita Popov 2020-12-26 15:22:20 +01:00
parent baf08259be
commit ebc3162468
3 changed files with 16 additions and 16 deletions
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2
lib/Analysis/ValueTracking.cpp
View File

@ -2111,7 +2111,7 @@ static bool isKnownNonNullFromDominatingCondition(const Value *V,
bool NonNullIfTrue;
if (cmpExcludesZero(Pred, RHS))
NonNullIfTrue = true;
else if (Pred == ICmpInst::ICMP_EQ && match(RHS, m_Zero()))
else if (cmpExcludesZero(CmpInst::getInversePredicate(Pred), RHS))
NonNullIfTrue = false;
else
continue;

26
test/Transforms/IndVarSimplify/X86/pr45360.ll
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@ -21,29 +21,29 @@ define dso_local i32 @main() {
; CHECK-NEXT: bb:
; CHECK-NEXT: [[I6:%.*]] = load i32, i32* @a, align 4
; CHECK-NEXT: [[I24:%.*]] = load i32, i32* @b, align 4
; CHECK-NEXT: [[D_PROMOTED8:%.*]] = load i32, i32* @d, align 4
; CHECK-NEXT: br label [[BB19:%.*]]
; CHECK: bb19:
; CHECK-NEXT: [[I8_LCSSA9:%.*]] = phi i32 [ [[D_PROMOTED8]], [[BB:%.*]] ], [ [[I8:%.*]], [[BB27:%.*]] ]
; CHECK-NEXT: [[I8]] = and i32 [[I8_LCSSA9]], [[I6]]
; CHECK-NEXT: [[D_PROMOTED9:%.*]] = load i32, i32* @d, align 4
; CHECK-NEXT: br label [[BB1:%.*]]
; CHECK: bb1:
; CHECK-NEXT: [[I8_LCSSA10:%.*]] = phi i32 [ [[D_PROMOTED9]], [[BB:%.*]] ], [ [[I8:%.*]], [[BB19_PREHEADER:%.*]] ]
; CHECK-NEXT: [[I8]] = and i32 [[I8_LCSSA10]], [[I6]]
; CHECK-NEXT: [[I21:%.*]] = icmp eq i32 [[I8]], 0
; CHECK-NEXT: br i1 [[I21]], label [[BB27_THREAD:%.*]], label [[BB27]]
; CHECK: bb27.thread:
; CHECK-NEXT: br i1 [[I21]], label [[BB13_PREHEADER_BB27_THREAD_SPLIT_CRIT_EDGE:%.*]], label [[BB19_PREHEADER]]
; CHECK: bb19.preheader:
; CHECK-NEXT: [[I26:%.*]] = urem i32 [[I24]], [[I8]]
; CHECK-NEXT: store i32 [[I26]], i32* @e, align 4
; CHECK-NEXT: [[I30_NOT:%.*]] = icmp eq i32 [[I26]], 0
; CHECK-NEXT: br i1 [[I30_NOT]], label [[BB32_LOOPEXIT:%.*]], label [[BB1]]
; CHECK: bb13.preheader.bb27.thread.split_crit_edge:
; CHECK-NEXT: store i32 -1, i32* @f, align 4
; CHECK-NEXT: store i32 0, i32* @d, align 4
; CHECK-NEXT: store i32 0, i32* @c, align 4
; CHECK-NEXT: br label [[BB32:%.*]]
; CHECK: bb27:
; CHECK-NEXT: [[I26:%.*]] = urem i32 [[I24]], [[I8]]
; CHECK-NEXT: store i32 [[I26]], i32* @e, align 4
; CHECK-NEXT: [[I30:%.*]] = icmp eq i32 [[I26]], 0
; CHECK-NEXT: br i1 [[I30]], label [[BB32_LOOPEXIT:%.*]], label [[BB19]]
; CHECK: bb32.loopexit:
; CHECK-NEXT: store i32 -1, i32* @f, align 4
; CHECK-NEXT: store i32 [[I8]], i32* @d, align 4
; CHECK-NEXT: br label [[BB32]]
; CHECK: bb32:
; CHECK-NEXT: [[C_SINK:%.*]] = phi i32* [ @c, [[BB32_LOOPEXIT]] ], [ @e, [[BB27_THREAD]] ]
; CHECK-NEXT: [[C_SINK:%.*]] = phi i32* [ @c, [[BB32_LOOPEXIT]] ], [ @e, [[BB13_PREHEADER_BB27_THREAD_SPLIT_CRIT_EDGE]] ]
; CHECK-NEXT: store i32 0, i32* [[C_SINK]], align 4
; CHECK-NEXT: ret i32 0
;

4
test/Transforms/InstCombine/known-non-zero.ll
View File

@ -232,7 +232,7 @@ define i64 @test_sle_zero(i64 %x) {
; CHECK-NEXT: [[C:%.*]] = icmp slt i64 [[X:%.*]], 1
; CHECK-NEXT: br i1 [[C]], label [[EXIT:%.*]], label [[NON_ZERO:%.*]]
; CHECK: non_zero:
; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 false), [[RNG0]]
; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 true), [[RNG0]]
; CHECK-NEXT: ret i64 [[CTZ]]
; CHECK: exit:
; CHECK-NEXT: ret i64 -1
@ -255,7 +255,7 @@ define i64 @test_sge_neg_ten(i64 %x) {
; CHECK-NEXT: [[C:%.*]] = icmp sgt i64 [[X:%.*]], -11
; CHECK-NEXT: br i1 [[C]], label [[EXIT:%.*]], label [[NON_ZERO:%.*]]
; CHECK: non_zero:
; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 false), [[RNG0]]
; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 true), [[RNG0]]
; CHECK-NEXT: ret i64 [[CTZ]]
; CHECK: exit:
; CHECK-NEXT: ret i64 -1