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[PowerPC] Don't miscompile rotate+mask into an ANDIo if it can't recreate the immediate
I'm not even sure if this transform is ever worth it, but this at least stops the bleeding. llvm-svn: 322373
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b728e61465
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@ -2444,6 +2444,8 @@ bool PPCInstrInfo::convertToImmediateForm(MachineInstr &MI,
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Is64BitLI = Opc != PPC::RLDICL_32;
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NewImm = InVal.getSExtValue();
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SetCR = Opc == PPC::RLDICLo;
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if (SetCR && (SExtImm & NewImm) != NewImm)
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return false;
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break;
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}
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return false;
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@ -2471,6 +2473,8 @@ bool PPCInstrInfo::convertToImmediateForm(MachineInstr &MI,
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Is64BitLI = Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8o;
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NewImm = InVal.getSExtValue();
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SetCR = Opc == PPC::RLWINMo || Opc == PPC::RLWINM8o;
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if (SetCR && (SExtImm & NewImm) != NewImm)
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return false;
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break;
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}
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return false;
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@ -560,6 +560,16 @@
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ret i64 %cond
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @testRLDICLo2(i64 %a, i64 %b) local_unnamed_addr #0 {
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entry:
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%shr = lshr i64 %a, 11
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%and = and i64 %shr, 16777215
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%tobool = icmp eq i64 %and, 0
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%cond = select i1 %tobool, i64 %b, i64 %and
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ret i64 %cond
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i32 @testRLWINM(i32 zeroext %a) local_unnamed_addr #0 {
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entry:
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@ -601,6 +611,15 @@
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ret i32 %cond
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i32 @testRLWINMo2(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
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entry:
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%and = and i32 %a, 255
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%tobool = icmp eq i32 %and, 0
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%cond = select i1 %tobool, i32 %b, i32 %a
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ret i32 %cond
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @testRLWINM8o(i64 %a, i64 %b) local_unnamed_addr #0 {
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entry:
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@ -3902,6 +3921,59 @@ body: |
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%x3 = COPY %4
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BLR8 implicit %lr8, implicit %rm, implicit %x3
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...
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---
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name: testRLDICLo2
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# CHECK-ALL: name: testRLDICLo2
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: g8rc, preferred-register: '' }
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- { id: 1, class: g8rc_and_g8rc_nox0, preferred-register: '' }
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- { id: 2, class: g8rc_and_g8rc_nox0, preferred-register: '' }
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- { id: 3, class: crrc, preferred-register: '' }
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- { id: 4, class: g8rc, preferred-register: '' }
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liveins:
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- { reg: '%x3', virtual-reg: '%0' }
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- { reg: '%x4', virtual-reg: '%1' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 4294967295
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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savePoint: ''
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restorePoint: ''
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fixedStack:
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stack:
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constants:
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body: |
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bb.0.entry:
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liveins: %x3, %x4
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%1 = COPY %x4
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%0 = LI8 200
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%2 = RLDICLo %0, 61, 3, implicit-def %cr0
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; CHECK-NOT: ANDI
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; CHECK-LATE-NOT: andi.
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%3 = COPY killed %cr0
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%4 = ISEL8 %1, %2, %3.sub_eq
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%x3 = COPY %4
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BLR8 implicit %lr8, implicit %rm, implicit %x3
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...
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---
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name: testRLWINM
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@ -4168,6 +4240,69 @@ body: |
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%x3 = COPY %9
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BLR8 implicit %lr8, implicit %rm, implicit %x3
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...
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---
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name: testRLWINMo2
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# CHECK-ALL: name: testRLWINMo2
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: g8rc, preferred-register: '' }
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- { id: 1, class: g8rc, preferred-register: '' }
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- { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' }
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- { id: 3, class: gprc_and_gprc_nor0, preferred-register: '' }
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- { id: 4, class: gprc, preferred-register: '' }
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- { id: 5, class: crrc, preferred-register: '' }
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- { id: 6, class: gprc, preferred-register: '' }
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- { id: 7, class: g8rc, preferred-register: '' }
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- { id: 8, class: g8rc, preferred-register: '' }
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- { id: 9, class: g8rc, preferred-register: '' }
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liveins:
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- { reg: '%x3', virtual-reg: '%0' }
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- { reg: '%x4', virtual-reg: '%1' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 4294967295
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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savePoint: ''
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restorePoint: ''
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fixedStack:
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stack:
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constants:
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body: |
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bb.0.entry:
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liveins: %x3, %x4
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%1 = COPY %x4
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%0 = COPY %x3
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%2 = COPY %1.sub_32
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%3 = LI -22
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%4 = RLWINMo %3, 5, 24, 31, implicit-def %cr0
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; CHECK-NOT: ANDI
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; CHECK-LATE-NOT: andi.
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%5 = COPY killed %cr0
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%6 = ISEL %2, %3, %5.sub_eq
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%8 = IMPLICIT_DEF
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%7 = INSERT_SUBREG %8, killed %6, 1
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%9 = RLDICL killed %7, 0, 32
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%x3 = COPY %9
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BLR8 implicit %lr8, implicit %rm, implicit %x3
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...
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---
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name: testRLWINM8o
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