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[ARM] Emit clrex in the expanded cmpxchg fail block.
ARM counterpart to r248291: In the comparison failure block of a cmpxchg expansion, the initial ldrex/ldxr will not be followed by a matching strex/stxr. On ARM/AArch64, this unnecessarily ties up the execution monitor, which might have a negative performance impact on some uarchs. Instead, release the monitor in the failure block. The clrex instruction was designed for this: use it. Also see ARMARM v8-A B2.10.2: "Exclusive access instructions and Shareable memory locations". Differential Revision: http://reviews.llvm.org/D13033 llvm-svn: 248294
This commit is contained in:
Ahmed Bougacha
parent
5f15f97d4c
commit
ec3a12595c
@ -11614,6 +11614,12 @@ Value *ARMTargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
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cast<PointerType>(Addr->getType())->getElementType());
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}
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void ARMTargetLowering::emitAtomicCmpXchgNoStoreLLBalance(
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IRBuilder<> &Builder) const {
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Module *M = Builder.GetInsertBlock()->getParent()->getParent();
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Builder.CreateCall(llvm::Intrinsic::getDeclaration(M, Intrinsic::arm_clrex));
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}
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Value *ARMTargetLowering::emitStoreConditional(IRBuilder<> &Builder, Value *Val,
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Value *Addr,
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AtomicOrdering Ord) const {
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@ -421,6 +421,8 @@ namespace llvm {
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Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
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Value *Addr, AtomicOrdering Ord) const override;
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void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override;
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Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
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bool IsStore, bool IsLoad) const override;
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Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
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@ -6,10 +6,12 @@ define i8 @t(i8* %a, i8 %b, i8 %c) nounwind {
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; ARM-LABEL: t:
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; ARM: ldrexb
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; ARM: strexb
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; ARM: clrex
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; T2-LABEL: t:
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; T2: ldrexb
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; T2: strexb
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; T2: ldrexb
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; T2: clrex
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%tmp0 = cmpxchg i8* %a, i8 %b, i8 %c monotonic monotonic
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%tmp1 = extractvalue { i8, i1 } %tmp0, 0
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ret i8 %tmp1
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@ -1,8 +1,8 @@
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; RUN: llc < %s -mtriple=arm-linux-gnueabi -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-ARM
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; RUN: llc < %s -mtriple=thumb-linux-gnueabi -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-THUMB
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; RUN: llc < %s -mtriple=arm-linux-gnueabi -asm-verbose=false -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-ARM
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; RUN: llc < %s -mtriple=thumb-linux-gnueabi -asm-verbose=false -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-THUMB
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; RUN: llc < %s -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-ARMV7
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; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-THUMBV7
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; RUN: llc < %s -mtriple=armv7-linux-gnueabi -asm-verbose=false -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-ARMV7
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; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -asm-verbose=false -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-THUMBV7
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define zeroext i1 @test_cmpxchg_res_i8(i8* %addr, i8 %desired, i8 zeroext %new) {
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entry:
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@ -30,24 +30,39 @@ entry:
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; CHECK-THUMB: push {[[R2]]}
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; CHECK-THUMB: pop {r0}
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; CHECK-ARMV7-LABEL: test_cmpxchg_res_i8
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; CHECK-ARMV7: ldrexb [[R3:r[0-9]+]], [r0]
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; CHECK-ARMV7: mov [[R1:r[0-9]+]], #0
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; CHECK-ARMV7: cmp [[R3]], {{r[0-9]+}}
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; CHECK-ARMV7: bne
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; CHECK-ARMV7: strexb [[R3]], {{r[0-9]+}}, [{{r[0-9]+}}]
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; CHECK-ARMV7: mov [[R1]], #1
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; CHECK-ARMV7: cmp [[R3]], #0
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; CHECK-ARMV7: bne
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; CHECK-ARMV7: mov r0, [[R1]]
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; CHECK-ARMV7-LABEL: test_cmpxchg_res_i8:
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; CHECK-ARMV7-NEXT: .fnstart
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; CHECK-ARMV7-NEXT: uxtb [[DESIRED:r[0-9]+]], r1
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; CHECK-ARMV7-NEXT: [[TRY:.LBB[0-9_]+]]:
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; CHECK-ARMV7-NEXT: ldrexb [[LD:r[0-9]+]], [r0]
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; CHECK-ARMV7-NEXT: cmp [[LD]], [[DESIRED]]
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; CHECK-ARMV7-NEXT: bne [[FAIL:.LBB[0-9_]+]]
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; CHECK-ARMV7-NEXT: strexb [[SUCCESS:r[0-9]+]], r2, [r0]
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; CHECK-ARMV7-NEXT: mov [[RES:r[0-9]+]], #1
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; CHECK-ARMV7-NEXT: cmp [[SUCCESS]], #0
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; CHECK-ARMV7-NEXT: bne [[TRY]]
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; CHECK-ARMV7-NEXT: b [[END:.LBB[0-9_]+]]
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; CHECK-ARMV7-NEXT: [[FAIL]]:
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; CHECK-ARMV7-NEXT: clrex
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; CHECK-ARMV7-NEXT: mov [[RES]], #0
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; CHECK-ARMV7-NEXT: [[END]]:
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; CHECK-ARMV7-NEXT: mov r0, [[RES]]
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; CHECK-ARMV7-NEXT: bx lr
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; CHECK-THUMBV7-LABEL: test_cmpxchg_res_i8
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; CHECK-THUMBV7: ldrexb [[R3:r[0-9]+]], [r0]
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; CHECK-THUMBV7: cmp [[R3]], {{r[0-9]+}}
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; CHECK-THUMBV7: movne r0, #0
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; CHECK-THUMBV7: bxne lr
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; CHECK-THUMBV7: strexb [[R3]], {{r[0-9]+}}, [{{r[0-9]+}}]
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; CHECK-THUMBV7: cmp [[R3]], #0
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; CHECK-THUMBV7: itt eq
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; CHECK-THUMBV7: moveq r0, #1
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; CHECK-THUMBV7: bxeq lr
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; CHECK-THUMBV7-LABEL: test_cmpxchg_res_i8:
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; CHECK-THUMBV7-NEXT: .fnstart
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; CHECK-THUMBV7-NEXT: uxtb [[DESIRED:r[0-9]+]], r1
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; CHECK-THUMBV7-NEXT: b [[TRYLD:.LBB[0-9_]+]]
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; CHECK-THUMBV7-NEXT: [[TRYST:.LBB[0-9_]+]]:
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; CHECK-THUMBV7-NEXT: strexb [[SUCCESS:r[0-9]+]], r2, [r0]
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; CHECK-THUMBV7-NEXT: cmp [[SUCCESS]], #0
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; CHECK-THUMBV7-NEXT: itt eq
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; CHECK-THUMBV7-NEXT: moveq r0, #1
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; CHECK-THUMBV7-NEXT: bxeq lr
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; CHECK-THUMBV7-NEXT: [[TRYLD]]:
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; CHECK-THUMBV7-NEXT: ldrexb [[LD:r[0-9]+]], [r0]
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; CHECK-THUMBV7-NEXT: cmp [[LD]], [[DESIRED]]
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; CHECK-THUMBV7-NEXT: beq [[TRYST:.LBB[0-9_]+]]
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; CHECK-THUMBV7-NEXT: clrex
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; CHECK-THUMBV7-NEXT: movs r0, #0
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; CHECK-THUMBV7-NEXT: bx lr
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@ -1,5 +1,5 @@
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; RUN: llc < %s -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s
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; RUN: llc < %s -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s
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; RUN: llc < %s -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix CHECK-ARMV7
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; RUN: llc < %s -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-T2
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; RUN: llc < %s -mtriple=thumbv6-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-T1
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; RUN: llc < %s -mtriple=thumbv6-apple-ios -verify-machineinstrs -mcpu=cortex-m0 | FileCheck %s --check-prefix=CHECK-M0
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; RUN: llc < %s -mtriple=thumbv7--none-eabi -thread-model single -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-BAREMETAL
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@ -272,16 +272,31 @@ define i32 @test_cmpxchg_fail_order(i32 *%addr, i32 %desired, i32 %new) {
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%pair = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst monotonic
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%oldval = extractvalue { i32, i1 } %pair, 0
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; CHECK: dmb ish
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; CHECK: [[LOOP_BB:\.?LBB[0-9]+_1]]:
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; CHECK: ldrex [[OLDVAL:r[0-9]+]], [r[[ADDR:[0-9]+]]]
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; CHECK: cmp [[OLDVAL]], r1
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; CHECK: bxne lr
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; CHECK: strex [[SUCCESS:r[0-9]+]], r2, [r[[ADDR]]]
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; CHECK: cmp [[SUCCESS]], #0
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; CHECK: bne [[LOOP_BB]]
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; CHECK: dmb ish
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; CHECK: bx lr
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; CHECK-ARMV7: dmb ish
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; CHECK-ARMV7: [[LOOP_BB:\.?LBB[0-9]+_1]]:
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; CHECK-ARMV7: ldrex [[OLDVAL:r[0-9]+]], [r[[ADDR:[0-9]+]]]
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; CHECK-ARMV7: cmp [[OLDVAL]], r1
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; CHECK-ARMV7: bne [[FAIL_BB:\.?LBB[0-9]+_[0-9]+]]
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; CHECK-ARMV7: strex [[SUCCESS:r[0-9]+]], r2, [r[[ADDR]]]
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; CHECK-ARMV7: cmp [[SUCCESS]], #0
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; CHECK-ARMV7: bne [[LOOP_BB]]
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; CHECK-ARMV7: dmb ish
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; CHECK-ARMV7: bx lr
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; CHECK-ARMV7: [[FAIL_BB]]:
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; CHECK-ARMV7: clrex
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; CHECK-ARMV7: bx lr
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; CHECK-T2: dmb ish
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; CHECK-T2: [[LOOP_BB:\.?LBB[0-9]+_1]]:
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; CHECK-T2: ldrex [[OLDVAL:r[0-9]+]], [r[[ADDR:[0-9]+]]]
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; CHECK-T2: cmp [[OLDVAL]], r1
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; CHECK-T2: clrexne
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; CHECK-T2: bxne lr
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; CHECK-T2: strex [[SUCCESS:r[0-9]+]], r2, [r[[ADDR]]]
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; CHECK-T2: cmp [[SUCCESS]], #0
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; CHECK-T2: dmbeq ish
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; CHECK-T2: bxeq lr
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; CHECK-T2: b [[LOOP_BB]]
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ret i32 %oldval
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}
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@ -295,11 +310,14 @@ define i32 @test_cmpxchg_fail_order1(i32 *%addr, i32 %desired, i32 %new) {
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; CHECK: [[LOOP_BB:\.?LBB[0-9]+_1]]:
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; CHECK: ldrex [[OLDVAL:r[0-9]+]], [r[[ADDR:[0-9]+]]]
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; CHECK: cmp [[OLDVAL]], r1
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; CHECK: bne [[END_BB:\.?LBB[0-9]+_[0-9]+]]
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; CHECK: bne [[FAIL_BB:\.?LBB[0-9]+_[0-9]+]]
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; CHECK: strex [[SUCCESS:r[0-9]+]], r2, [r[[ADDR]]]
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; CHECK: cmp [[SUCCESS]], #0
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; CHECK: bne [[LOOP_BB]]
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; CHECK: [[END_BB]]:
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; CHECK: b [[END_BB:\.?LBB[0-9]+_[0-9]+]]
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; CHECK: [[FAIL_BB]]:
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; CHECK-NEXT: clrex
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; CHECK-NEXT: [[END_BB]]:
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; CHECK: dmb ish
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; CHECK: bx lr
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@ -1055,24 +1055,30 @@ define i8 @test_atomic_cmpxchg_i8(i8 zeroext %wanted, i8 zeroext %new) nounwind
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%old = extractvalue { i8, i1 } %pair, 0
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; CHECK-NOT: dmb
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; CHECK-NOT: mcr
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; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8
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; CHECK: movt r[[ADDR]], :upper16:var8
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; CHECK-DAG: movw r[[ADDR:[0-9]+]], :lower16:var8
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; CHECK-DAG: movt r[[ADDR]], :upper16:var8
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; CHECK-THUMB-DAG: mov r[[WANTED:[0-9]+]], r0
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; CHECK: .LBB{{[0-9]+}}_1:
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; CHECK: ldaexb r[[OLD:[0-9]+]], [r[[ADDR]]]
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; r0 below is a reasonable guess but could change: it certainly comes into the
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; function there.
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; CHECK-NEXT: cmp r[[OLD]], r0
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; CHECK-ARM-NEXT: cmp r[[OLD]], r0
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; CHECK-THUMB-NEXT: cmp r[[OLD]], r[[WANTED]]
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; CHECK-NEXT: bne .LBB{{[0-9]+}}_3
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; CHECK-NEXT: BB#2:
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; As above, r1 is a reasonable guess.
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; CHECK: strexb [[STATUS:r[0-9]+]], r1, {{.*}}[[ADDR]]
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; CHECK: strexb [[STATUS:r[0-9]+]], r1, [r[[ADDR]]]
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; CHECK-NEXT: cmp [[STATUS]], #0
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; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
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; CHECK-NEXT: b .LBB{{[0-9]+}}_4
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; CHECK-NEXT: .LBB{{[0-9]+}}_3:
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; CHECK-NEXT: clrex
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; CHECK-NEXT: .LBB{{[0-9]+}}_4:
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; CHECK-NOT: dmb
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; CHECK-NOT: mcr
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; CHECK: mov r0, r[[OLD]]
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; CHECK-ARM: mov r0, r[[OLD]]
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ret i8 %old
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}
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@ -1082,24 +1088,30 @@ define i16 @test_atomic_cmpxchg_i16(i16 zeroext %wanted, i16 zeroext %new) nounw
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%old = extractvalue { i16, i1 } %pair, 0
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; CHECK-NOT: dmb
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; CHECK-NOT: mcr
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; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16
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; CHECK: movt r[[ADDR]], :upper16:var16
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; CHECK-DAG: movw r[[ADDR:[0-9]+]], :lower16:var16
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; CHECK-DAG: movt r[[ADDR]], :upper16:var16
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; CHECK-THUMB-DAG: mov r[[WANTED:[0-9]+]], r0
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; CHECK: .LBB{{[0-9]+}}_1:
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; CHECK: ldaexh r[[OLD:[0-9]+]], [r[[ADDR]]]
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; r0 below is a reasonable guess but could change: it certainly comes into the
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; function there.
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; CHECK-NEXT: cmp r[[OLD]], r0
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; CHECK-ARM-NEXT: cmp r[[OLD]], r0
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; CHECK-THUMB-NEXT: cmp r[[OLD]], r[[WANTED]]
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; CHECK-NEXT: bne .LBB{{[0-9]+}}_3
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; CHECK-NEXT: BB#2:
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; As above, r1 is a reasonable guess.
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; CHECK: stlexh [[STATUS:r[0-9]+]], r1, [r[[ADDR]]]
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; CHECK-NEXT: cmp [[STATUS]], #0
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; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
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; CHECK-NEXT: b .LBB{{[0-9]+}}_4
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; CHECK-NEXT: .LBB{{[0-9]+}}_3:
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; CHECK-NEXT: clrex
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; CHECK-NEXT: .LBB{{[0-9]+}}_4:
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; CHECK-NOT: dmb
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; CHECK-NOT: mcr
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; CHECK: mov r0, r[[OLD]]
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; CHECK-ARM: mov r0, r[[OLD]]
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ret i16 %old
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}
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@ -1124,6 +1136,10 @@ define void @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind {
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; CHECK: stlex [[STATUS:r[0-9]+]], r1, [r[[ADDR]]]
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; CHECK-NEXT: cmp [[STATUS]], #0
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; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
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; CHECK-NEXT: b .LBB{{[0-9]+}}_4
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; CHECK-NEXT: .LBB{{[0-9]+}}_3:
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; CHECK-NEXT: clrex
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; CHECK-NEXT: .LBB{{[0-9]+}}_4:
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; CHECK-NOT: dmb
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; CHECK-NOT: mcr
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@ -1158,6 +1174,10 @@ define void @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind {
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; CHECK: strexd [[STATUS:r[0-9]+]], r2, r3, [r[[ADDR]]]
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; CHECK-NEXT: cmp [[STATUS]], #0
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; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
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; CHECK-NEXT: b .LBB{{[0-9]+}}_4
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; CHECK-NEXT: .LBB{{[0-9]+}}_3:
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; CHECK-NEXT: clrex
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; CHECK-NEXT: .LBB{{[0-9]+}}_4:
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; CHECK-NOT: dmb
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; CHECK-NOT: mcr
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@ -5,16 +5,24 @@ define void @test_cmpxchg_weak(i32 *%addr, i32 %desired, i32 %new) {
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%pair = cmpxchg weak i32* %addr, i32 %desired, i32 %new seq_cst monotonic
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%oldval = extractvalue { i32, i1 } %pair, 0
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; CHECK: dmb ish
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; CHECK: ldrex [[LOADED:r[0-9]+]], [r0]
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; CHECK: cmp [[LOADED]], r1
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; CHECK: strexeq [[SUCCESS:r[0-9]+]], r2, [r0]
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; CHECK: cmpeq [[SUCCESS]], #0
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; CHECK: bne [[DONE:LBB[0-9]+_[0-9]+]]
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; CHECK: dmb ish
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; CHECK: [[DONE]]:
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; CHECK: str r3, [r0]
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; CHECK: bx lr
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; CHECK-NEXT: BB#0:
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; CHECK-NEXT: dmb ish
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; CHECK-NEXT: ldrex [[LOADED:r[0-9]+]], [r0]
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; CHECK-NEXT: cmp [[LOADED]], r1
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; CHECK-NEXT: bne [[LDFAILBB:LBB[0-9]+_[0-9]+]]
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; CHECK-NEXT: BB#1:
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; CHECK-NEXT: strex [[SUCCESS:r[0-9]+]], r2, [r0]
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; CHECK-NEXT: cmp [[SUCCESS]], #0
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; CHECK-NEXT: bne [[FAILBB:LBB[0-9]+_[0-9]+]]
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; CHECK-NEXT: BB#2:
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; CHECK-NEXT: dmb ish
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; CHECK-NEXT: str r3, [r0]
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; CHECK-NEXT: bx lr
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; CHECK-NEXT: [[LDFAILBB]]:
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; CHECK-NEXT: clrex
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; CHECK-NEXT: [[FAILBB]]:
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; CHECK-NEXT: str r3, [r0]
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; CHECK-NEXT: bx lr
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store i32 %oldval, i32* %addr
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ret void
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@ -27,17 +35,23 @@ define i1 @test_cmpxchg_weak_to_bool(i32, i32 *%addr, i32 %desired, i32 %new) {
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%pair = cmpxchg weak i32* %addr, i32 %desired, i32 %new seq_cst monotonic
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%success = extractvalue { i32, i1 } %pair, 1
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; CHECK: dmb ish
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; CHECK: mov r0, #0
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; CHECK: ldrex [[LOADED:r[0-9]+]], [r1]
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; CHECK: cmp [[LOADED]], r2
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; CHECK: strexeq [[STATUS:r[0-9]+]], r3, [r1]
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; CHECK: cmpeq [[STATUS]], #0
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; CHECK: bne [[DONE:LBB[0-9]+_[0-9]+]]
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; CHECK: dmb ish
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; CHECK: mov r0, #1
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; CHECK: [[DONE]]:
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||||
; CHECK: bx lr
|
||||
; CHECK-NEXT: BB#0:
|
||||
; CHECK-NEXT: dmb ish
|
||||
; CHECK-NEXT: ldrex [[LOADED:r[0-9]+]], [r1]
|
||||
; CHECK-NEXT: cmp [[LOADED]], r2
|
||||
; CHECK-NEXT: bne [[LDFAILBB:LBB[0-9]+_[0-9]+]]
|
||||
; CHECK-NEXT: BB#1:
|
||||
; CHECK-NEXT: strex [[SUCCESS:r[0-9]+]], r3, [r1]
|
||||
; CHECK-NEXT: mov r0, #0
|
||||
; CHECK-NEXT: cmp [[SUCCESS]], #0
|
||||
; CHECK-NEXT: bxne lr
|
||||
; CHECK-NEXT: dmb ish
|
||||
; CHECK-NEXT: mov r0, #1
|
||||
; CHECK-NEXT: bx lr
|
||||
; CHECK-NEXT: [[LDFAILBB]]:
|
||||
; CHECK-NEXT: clrex
|
||||
; CHECK-NEXT: mov r0, #0
|
||||
; CHECK-NEXT: bx lr
|
||||
|
||||
ret i1 %success
|
||||
}
|
||||
|
||||
@ -229,7 +229,7 @@ define i8 @test_cmpxchg_i8_seqcst_seqcst(i8* %ptr, i8 %desired, i8 %newval) {
|
||||
; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr)
|
||||
; CHECK: [[OLDVAL:%.*]] = trunc i32 %1 to i8
|
||||
; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i8 [[OLDVAL]], %desired
|
||||
; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[FAILURE_BB:.*]]
|
||||
; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[NO_STORE_BB:.*]]
|
||||
|
||||
; CHECK: [[TRY_STORE]]:
|
||||
; CHECK: [[NEWVAL32:%.*]] = zext i8 %newval to i32
|
||||
@ -241,6 +241,10 @@ define i8 @test_cmpxchg_i8_seqcst_seqcst(i8* %ptr, i8 %desired, i8 %newval) {
|
||||
; CHECK: call void @llvm.arm.dmb(i32 11)
|
||||
; CHECK: br label %[[DONE:.*]]
|
||||
|
||||
; CHECK: [[NO_STORE_BB]]:
|
||||
; CHECK-NEXT: call void @llvm.arm.clrex()
|
||||
; CHECK-NEXT: br label %[[FAILURE_BB:.*]]
|
||||
|
||||
; CHECK: [[FAILURE_BB]]:
|
||||
; CHECK: call void @llvm.arm.dmb(i32 11)
|
||||
; CHECK: br label %[[DONE]]
|
||||
@ -263,7 +267,7 @@ define i16 @test_cmpxchg_i16_seqcst_monotonic(i16* %ptr, i16 %desired, i16 %newv
|
||||
; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i16(i16* %ptr)
|
||||
; CHECK: [[OLDVAL:%.*]] = trunc i32 %1 to i16
|
||||
; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i16 [[OLDVAL]], %desired
|
||||
; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[FAILURE_BB:.*]]
|
||||
; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[NO_STORE_BB:.*]]
|
||||
|
||||
; CHECK: [[TRY_STORE]]:
|
||||
; CHECK: [[NEWVAL32:%.*]] = zext i16 %newval to i32
|
||||
@ -275,6 +279,10 @@ define i16 @test_cmpxchg_i16_seqcst_monotonic(i16* %ptr, i16 %desired, i16 %newv
|
||||
; CHECK: call void @llvm.arm.dmb(i32 11)
|
||||
; CHECK: br label %[[DONE:.*]]
|
||||
|
||||
; CHECK: [[NO_STORE_BB]]:
|
||||
; CHECK-NEXT: call void @llvm.arm.clrex()
|
||||
; CHECK-NEXT: br label %[[FAILURE_BB:.*]]
|
||||
|
||||
; CHECK: [[FAILURE_BB]]:
|
||||
; CHECK-NOT: dmb
|
||||
; CHECK: br label %[[DONE]]
|
||||
@ -296,7 +304,7 @@ define i32 @test_cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %desired, i32 %newva
|
||||
; CHECK: [[LOOP]]:
|
||||
; CHECK: [[OLDVAL:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* %ptr)
|
||||
; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[OLDVAL]], %desired
|
||||
; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[FAILURE_BB:.*]]
|
||||
; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[NO_STORE_BB:.*]]
|
||||
|
||||
; CHECK: [[TRY_STORE]]:
|
||||
; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %newval, i32* %ptr)
|
||||
@ -307,6 +315,10 @@ define i32 @test_cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %desired, i32 %newva
|
||||
; CHECK: call void @llvm.arm.dmb(i32 11)
|
||||
; CHECK: br label %[[DONE:.*]]
|
||||
|
||||
; CHECK: [[NO_STORE_BB]]:
|
||||
; CHECK-NEXT: call void @llvm.arm.clrex()
|
||||
; CHECK-NEXT: br label %[[FAILURE_BB:.*]]
|
||||
|
||||
; CHECK: [[FAILURE_BB]]:
|
||||
; CHECK: call void @llvm.arm.dmb(i32 11)
|
||||
; CHECK: br label %[[DONE]]
|
||||
@ -335,7 +347,7 @@ define i64 @test_cmpxchg_i64_monotonic_monotonic(i64* %ptr, i64 %desired, i64 %n
|
||||
; CHECK: [[HI64:%.*]] = shl i64 [[HI64_TMP]], 32
|
||||
; CHECK: [[OLDVAL:%.*]] = or i64 [[LO64]], [[HI64]]
|
||||
; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i64 [[OLDVAL]], %desired
|
||||
; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[FAILURE_BB:.*]]
|
||||
; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[NO_STORE_BB:.*]]
|
||||
|
||||
; CHECK: [[TRY_STORE]]:
|
||||
; CHECK: [[NEWLO:%.*]] = trunc i64 %newval to i32
|
||||
@ -350,6 +362,10 @@ define i64 @test_cmpxchg_i64_monotonic_monotonic(i64* %ptr, i64 %desired, i64 %n
|
||||
; CHECK-NOT: dmb
|
||||
; CHECK: br label %[[DONE:.*]]
|
||||
|
||||
; CHECK: [[NO_STORE_BB]]:
|
||||
; CHECK-NEXT: call void @llvm.arm.clrex()
|
||||
; CHECK-NEXT: br label %[[FAILURE_BB:.*]]
|
||||
|
||||
; CHECK: [[FAILURE_BB]]:
|
||||
; CHECK-NOT: dmb
|
||||
; CHECK: br label %[[DONE]]
|
||||
|
||||
@ -91,7 +91,7 @@ define i8 @test_cmpxchg_i8_seqcst_seqcst(i8* %ptr, i8 %desired, i8 %newval) {
|
||||
; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldaex.p0i8(i8* %ptr)
|
||||
; CHECK: [[OLDVAL:%.*]] = trunc i32 %1 to i8
|
||||
; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i8 [[OLDVAL]], %desired
|
||||
; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[FAILURE_BB:.*]]
|
||||
; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[NO_STORE_BB:.*]]
|
||||
|
||||
; CHECK: [[TRY_STORE]]:
|
||||
; CHECK: [[NEWVAL32:%.*]] = zext i8 %newval to i32
|
||||
@ -103,6 +103,10 @@ define i8 @test_cmpxchg_i8_seqcst_seqcst(i8* %ptr, i8 %desired, i8 %newval) {
|
||||
; CHECK-NOT: fence_cst
|
||||
; CHECK: br label %[[DONE:.*]]
|
||||
|
||||
; CHECK: [[NO_STORE_BB]]:
|
||||
; CHECK-NEXT: call void @llvm.arm.clrex()
|
||||
; CHECK-NEXT: br label %[[FAILURE_BB:.*]]
|
||||
|
||||
; CHECK: [[FAILURE_BB]]:
|
||||
; CHECK-NOT: fence_cst
|
||||
; CHECK: br label %[[DONE]]
|
||||
@ -125,7 +129,7 @@ define i16 @test_cmpxchg_i16_seqcst_monotonic(i16* %ptr, i16 %desired, i16 %newv
|
||||
; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldaex.p0i16(i16* %ptr)
|
||||
; CHECK: [[OLDVAL:%.*]] = trunc i32 %1 to i16
|
||||
; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i16 [[OLDVAL]], %desired
|
||||
; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[FAILURE_BB:.*]]
|
||||
; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[NO_STORE_BB:.*]]
|
||||
|
||||
; CHECK: [[TRY_STORE]]:
|
||||
; CHECK: [[NEWVAL32:%.*]] = zext i16 %newval to i32
|
||||
@ -137,6 +141,10 @@ define i16 @test_cmpxchg_i16_seqcst_monotonic(i16* %ptr, i16 %desired, i16 %newv
|
||||
; CHECK-NOT: fence
|
||||
; CHECK: br label %[[DONE:.*]]
|
||||
|
||||
; CHECK: [[NO_STORE_BB]]:
|
||||
; CHECK-NEXT: call void @llvm.arm.clrex()
|
||||
; CHECK-NEXT: br label %[[FAILURE_BB:.*]]
|
||||
|
||||
; CHECK: [[FAILURE_BB]]:
|
||||
; CHECK-NOT: fence
|
||||
; CHECK: br label %[[DONE]]
|
||||
@ -158,7 +166,7 @@ define i32 @test_cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %desired, i32 %newva
|
||||
; CHECK: [[LOOP]]:
|
||||
; CHECK: [[OLDVAL:%.*]] = call i32 @llvm.arm.ldaex.p0i32(i32* %ptr)
|
||||
; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[OLDVAL]], %desired
|
||||
; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[FAILURE_BB:.*]]
|
||||
; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[NO_STORE_BB:.*]]
|
||||
|
||||
; CHECK: [[TRY_STORE]]:
|
||||
; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %newval, i32* %ptr)
|
||||
@ -169,6 +177,10 @@ define i32 @test_cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %desired, i32 %newva
|
||||
; CHECK-NOT: fence_cst
|
||||
; CHECK: br label %[[DONE:.*]]
|
||||
|
||||
; CHECK: [[NO_STORE_BB]]:
|
||||
; CHECK-NEXT: call void @llvm.arm.clrex()
|
||||
; CHECK-NEXT: br label %[[FAILURE_BB:.*]]
|
||||
|
||||
; CHECK: [[FAILURE_BB]]:
|
||||
; CHECK-NOT: fence_cst
|
||||
; CHECK: br label %[[DONE]]
|
||||
@ -197,7 +209,7 @@ define i64 @test_cmpxchg_i64_monotonic_monotonic(i64* %ptr, i64 %desired, i64 %n
|
||||
; CHECK: [[HI64:%.*]] = shl i64 [[HI64_TMP]], 32
|
||||
; CHECK: [[OLDVAL:%.*]] = or i64 [[LO64]], [[HI64]]
|
||||
; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i64 [[OLDVAL]], %desired
|
||||
; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[FAILURE_BB:.*]]
|
||||
; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[NO_STORE_BB:.*]]
|
||||
|
||||
; CHECK: [[TRY_STORE]]:
|
||||
; CHECK: [[NEWLO:%.*]] = trunc i64 %newval to i32
|
||||
@ -212,6 +224,10 @@ define i64 @test_cmpxchg_i64_monotonic_monotonic(i64* %ptr, i64 %desired, i64 %n
|
||||
; CHECK-NOT: fence_cst
|
||||
; CHECK: br label %[[DONE:.*]]
|
||||
|
||||
; CHECK: [[NO_STORE_BB]]:
|
||||
; CHECK-NEXT: call void @llvm.arm.clrex()
|
||||
; CHECK-NEXT: br label %[[FAILURE_BB:.*]]
|
||||
|
||||
; CHECK: [[FAILURE_BB]]:
|
||||
; CHECK-NOT: fence_cst
|
||||
; CHECK: br label %[[DONE]]
|
||||
|
||||
@ -9,17 +9,21 @@ define i32 @test_cmpxchg_seq_cst(i32* %addr, i32 %desired, i32 %new) {
|
||||
; CHECK: [[START]]:
|
||||
; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* %addr)
|
||||
; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[LOADED]], %desired
|
||||
; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[FAILURE_BB:.*]]
|
||||
; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[NO_STORE_BB:.*]]
|
||||
|
||||
; CHECK: [[TRY_STORE]]:
|
||||
; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %new, i32* %addr)
|
||||
; CHECK: [[SUCCESS:%.*]] = icmp eq i32 [[STREX]], 0
|
||||
; CHECK: br i1 [[SUCCESS]], label %[[SUCCESS_BB:.*]], label %[[FAILURE_BB]]
|
||||
; CHECK: br i1 [[SUCCESS]], label %[[SUCCESS_BB:.*]], label %[[FAILURE_BB:.*]]
|
||||
|
||||
; CHECK: [[SUCCESS_BB]]:
|
||||
; CHECK: call void @llvm.arm.dmb(i32 11)
|
||||
; CHECK: br label %[[END:.*]]
|
||||
|
||||
; CHECK: [[NO_STORE_BB]]:
|
||||
; CHECK: call void @llvm.arm.clrex()
|
||||
; CHECK: br label %[[FAILURE_BB]]
|
||||
|
||||
; CHECK: [[FAILURE_BB]]:
|
||||
; CHECK: call void @llvm.arm.dmb(i32 11)
|
||||
; CHECK: br label %[[END]]
|
||||
@ -41,7 +45,7 @@ define i1 @test_cmpxchg_weak_fail(i32* %addr, i32 %desired, i32 %new) {
|
||||
; CHECK: [[START]]:
|
||||
; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* %addr)
|
||||
; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[LOADED]], %desired
|
||||
; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[FAILURE_BB:.*]]
|
||||
; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[NO_STORE_BB:.*]]
|
||||
|
||||
; CHECK: [[TRY_STORE]]:
|
||||
; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %new, i32* %addr)
|
||||
@ -52,6 +56,10 @@ define i1 @test_cmpxchg_weak_fail(i32* %addr, i32 %desired, i32 %new) {
|
||||
; CHECK: call void @llvm.arm.dmb(i32 11)
|
||||
; CHECK: br label %[[END:.*]]
|
||||
|
||||
; CHECK: [[NO_STORE_BB]]:
|
||||
; CHECK: call void @llvm.arm.clrex()
|
||||
; CHECK: br label %[[FAILURE_BB]]
|
||||
|
||||
; CHECK: [[FAILURE_BB]]:
|
||||
; CHECK-NOT: dmb
|
||||
; CHECK: br label %[[END]]
|
||||
@ -73,7 +81,7 @@ define i32 @test_cmpxchg_monotonic(i32* %addr, i32 %desired, i32 %new) {
|
||||
; CHECK: [[START]]:
|
||||
; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* %addr)
|
||||
; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[LOADED]], %desired
|
||||
; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[FAILURE_BB:.*]]
|
||||
; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[NO_STORE_BB:.*]]
|
||||
|
||||
; CHECK: [[TRY_STORE]]:
|
||||
; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %new, i32* %addr)
|
||||
@ -84,6 +92,10 @@ define i32 @test_cmpxchg_monotonic(i32* %addr, i32 %desired, i32 %new) {
|
||||
; CHECK-NOT: dmb
|
||||
; CHECK: br label %[[END:.*]]
|
||||
|
||||
; CHECK: [[NO_STORE_BB]]:
|
||||
; CHECK: call void @llvm.arm.clrex()
|
||||
; CHECK: br label %[[FAILURE_BB]]
|
||||
|
||||
; CHECK: [[FAILURE_BB]]:
|
||||
; CHECK-NOT: dmb
|
||||
; CHECK: br label %[[END]]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user