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Add patterns to define 'combine', 'tstbit', 'ct0/cl0' (count trailing/leading zeros)
instructions. llvm-svn: 169287
This commit is contained in:
Jyotsna Verma
parent
0dd9064b5a
commit
ec3f676ca1
@ -50,6 +50,15 @@ namespace llvm {
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BARRIER, // Memory barrier.
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WrapperJT,
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WrapperCP,
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WrapperCombineII,
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WrapperCombineRR,
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WrapperPackhl,
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WrapperSplatB,
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WrapperSplatH,
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WrapperShuffEB,
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WrapperShuffEH,
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WrapperShuffOB,
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WrapperShuffOH,
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TC_RETURN
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};
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}
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@ -334,17 +334,50 @@ def TFCR : CRInst<(outs CRRegs:$dst), (ins IntRegs:$src1),
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//===----------------------------------------------------------------------===//
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// Combine.
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let isPredicable = 1, neverHasSideEffects = 1 in
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def COMBINE_rr : ALU32_rr<(outs DoubleRegs:$dst),
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(ins IntRegs:$src1, IntRegs:$src2),
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"$dst = combine($src1, $src2)",
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[]>;
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let neverHasSideEffects = 1 in
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def COMBINE_ii : ALU32_ii<(outs DoubleRegs:$dst),
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(ins s8Imm:$src1, s8Imm:$src2),
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"$dst = combine(#$src1, #$src2)",
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[]>;
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def SDTHexagonI64I32I32 : SDTypeProfile<1, 2,
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[SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
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def HexagonWrapperCombineII :
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SDNode<"HexagonISD::WrapperCombineII", SDTHexagonI64I32I32>;
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def HexagonWrapperCombineRR :
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SDNode<"HexagonISD::WrapperCombineRR", SDTHexagonI64I32I32>;
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// Combines the two integer registers SRC1 and SRC2 into a double register.
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let isPredicable = 1 in
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def COMBINE_rr : ALU32_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1,
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IntRegs:$src2),
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"$dst = combine($src1, $src2)",
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[(set (i64 DoubleRegs:$dst),
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(i64 (HexagonWrapperCombineRR (i32 IntRegs:$src1),
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(i32 IntRegs:$src2))))]>;
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// Rd=combine(Rt.[HL], Rs.[HL])
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class COMBINE_halves<string A, string B>: ALU32_rr<(outs IntRegs:$dst),
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(ins IntRegs:$src1,
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IntRegs:$src2),
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"$dst = combine($src1."# A #", $src2."# B #")", []>;
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let isPredicable = 1 in {
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def COMBINE_hh : COMBINE_halves<"H", "H">;
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def COMBINE_hl : COMBINE_halves<"H", "L">;
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def COMBINE_lh : COMBINE_halves<"L", "H">;
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def COMBINE_ll : COMBINE_halves<"L", "L">;
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}
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def : Pat<(i32 (trunc (i64 (srl (i64 DoubleRegs:$a), (i32 16))))),
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(COMBINE_lh (EXTRACT_SUBREG (i64 DoubleRegs:$a), subreg_hireg),
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(EXTRACT_SUBREG (i64 DoubleRegs:$a), subreg_loreg))>;
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// Combines the two immediates SRC1 and SRC2 into a double register.
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class COMBINE_imm<Operand imm1, Operand imm2, PatLeaf pat1, PatLeaf pat2> :
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ALU32_ii<(outs DoubleRegs:$dst), (ins imm1:$src1, imm2:$src2),
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"$dst = combine(#$src1, #$src2)",
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[(set (i64 DoubleRegs:$dst),
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(i64 (HexagonWrapperCombineII (i32 pat1:$src1), (i32 pat2:$src2))))]>;
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let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 8 in
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def COMBINE_Ii : COMBINE_imm<s8Ext, s8Imm, s8ExtPred, s8ImmPred>;
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// Mux.
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def VMUX_prr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
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@ -429,7 +462,6 @@ def ZXTH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
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//===----------------------------------------------------------------------===//
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// Conditional combine.
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let neverHasSideEffects = 1, isPredicated = 1 in
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def COMBINE_rr_cPt : ALU32_rr<(outs DoubleRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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@ -462,6 +494,33 @@ defm CMPLTU : CMP32_rr<"cmp.ltu", setult>;
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defm CMPEQ : CMP32_rr_ri_s10<"cmp.eq", "CMPEQ", seteq>, ImmRegRel;
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defm CMPGE : CMP32_ri_s8<"cmp.ge", setge>;
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defm CMPGEU : CMP32_ri_u8<"cmp.geu", setuge>;
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def CTLZ_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
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"$dst = cl0($src1)",
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[(set (i32 IntRegs:$dst), (ctlz (i32 IntRegs:$src1)))]>;
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def CTTZ_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
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"$dst = ct0($src1)",
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[(set (i32 IntRegs:$dst), (cttz (i32 IntRegs:$src1)))]>;
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def CTLZ64_rr : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
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"$dst = cl0($src1)",
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[(set (i32 IntRegs:$dst), (i32 (trunc (ctlz (i64 DoubleRegs:$src1)))))]>;
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def CTTZ64_rr : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
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"$dst = ct0($src1)",
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[(set (i32 IntRegs:$dst), (i32 (trunc (cttz (i64 DoubleRegs:$src1)))))]>;
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def TSTBIT_rr : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
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"$dst = tstbit($src1, $src2)",
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[(set (i1 PredRegs:$dst),
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(setne (and (shl 1, (i32 IntRegs:$src2)), (i32 IntRegs:$src1)), 0))]>;
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def TSTBIT_ri : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
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"$dst = tstbit($src1, $src2)",
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[(set (i1 PredRegs:$dst),
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(setne (and (shl 1, (u5ImmPred:$src2)), (i32 IntRegs:$src1)), 0))]>;
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//===----------------------------------------------------------------------===//
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// ALU32/PRED -
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//===----------------------------------------------------------------------===//
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@ -276,19 +276,31 @@ def TFR_FI_immext_V4 : ALU32_ri<(outs IntRegs:$dst),
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// Combine
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// Rdd=combine(Rs, #s8)
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let neverHasSideEffects = 1 in
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def COMBINE_ri_V4 : ALU32_ri<(outs DoubleRegs:$dst),
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(ins IntRegs:$src1, s8Imm:$src2),
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let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8,
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neverHasSideEffects = 1, validSubTargets = HasV4SubT in
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def COMBINE_rI_V4 : ALU32_ri<(outs DoubleRegs:$dst),
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(ins IntRegs:$src1, s8Ext:$src2),
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"$dst = combine($src1, #$src2)",
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[]>,
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Requires<[HasV4T]>;
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// Rdd=combine(#s8, Rs)
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let neverHasSideEffects = 1 in
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def COMBINE_ir_V4 : ALU32_ir<(outs DoubleRegs:$dst),
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(ins s8Imm:$src1, IntRegs:$src2),
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let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 8,
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neverHasSideEffects = 1, validSubTargets = HasV4SubT in
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def COMBINE_Ir_V4 : ALU32_ir<(outs DoubleRegs:$dst),
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(ins s8Ext:$src1, IntRegs:$src2),
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"$dst = combine(#$src1, $src2)",
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[]>,
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Requires<[HasV4T]>;
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let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 6,
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neverHasSideEffects = 1, validSubTargets = HasV4SubT in
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def COMBINE_iI_V4 : ALU32_ii<(outs DoubleRegs:$dst),
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(ins s8Imm:$src1, u6Ext:$src2),
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"$dst = combine(#$src1, #$src2)",
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[]>,
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Requires<[HasV4T]>;
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//===----------------------------------------------------------------------===//
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// ALU32/PERM +
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//===----------------------------------------------------------------------===//
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