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[AArch64] Adjust the scheduling model for Exynos M1.

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Further refine the model for stores.

llvm-svn: 280735
This commit is contained in:
Evandro Menezes 2016-09-06 19:22:27 +00:00
parent c51cc4ee30
commit ec72a0be08
1 changed files with 7 additions and 2 deletions
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9
lib/Target/AArch64/AArch64SchedM1.td
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@ -71,6 +71,12 @@ def M1WriteLA : SchedWriteVariant<[SchedVar<ScaledIdxPred, [M1WriteL5,
M1WriteA1]>,
SchedVar<NoSchedPred, [M1WriteL5]>]>;
def M1WriteS1 : SchedWriteRes<[M1UnitS]> { let Latency = 1; }
def M1WriteS2 : SchedWriteRes<[M1UnitS]> { let Latency = 2; }
def M1WriteSA : SchedWriteVariant<[SchedVar<ScaledIdxPred, [M1WriteS2,
M1WriteA1]>,
SchedVar<NoSchedPred, [M1WriteS1]>]>;
def M1ReadAdrBase : SchedReadVariant<[SchedVar<ScaledIdxPred, [ReadDefault]>,
SchedVar<NoSchedPred, [ReadDefault]>]>;
def : SchedAlias<ReadAdrBase, M1ReadAdrBase>;
@ -117,10 +123,9 @@ def : SchedAlias<WriteLDIdx, M1WriteLA>;
// Store instructions.
def : WriteRes<WriteST, [M1UnitS]> { let Latency = 1; }
// TODO: Extended address requires also the ALU.
def : WriteRes<WriteSTIdx, [M1UnitS]> { let Latency = 1; }
def : WriteRes<WriteSTP, [M1UnitS]> { let Latency = 1; }
def : WriteRes<WriteSTX, [M1UnitS]> { let Latency = 1; }
def : SchedAlias<WriteSTIdx, M1WriteSA>;
// FP data instructions.
def : WriteRes<WriteF, [M1UnitFADD]> { let Latency = 3; }