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TLI: Allow using PSV for intrinsic mem operands

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llvm-svn: 320756
This commit is contained in:
Matt Arsenault 2017-12-14 22:34:10 +00:00
parent 7655f081e8
commit ec7e75e600
18 changed files with 38 additions and 5 deletions
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15
include/llvm/CodeGen/MachineMemOperand.h
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@ -47,7 +47,7 @@ struct MachinePointerInfo {
uint8_t StackID;
unsigned AddrSpace;
unsigned AddrSpace = 0;
explicit MachinePointerInfo(const Value *v, int64_t offset = 0,
uint8_t ID = 0)
@ -65,6 +65,19 @@ struct MachinePointerInfo {
: V((const Value *)nullptr), Offset(0), StackID(0),
AddrSpace(AddressSpace) {}
explicit MachinePointerInfo(
PointerUnion<const Value *, const PseudoSourceValue *> v,
int64_t offset = 0,
uint8_t ID = 0)
: V(v), Offset(offset), StackID(ID) {
if (V) {
if (const auto *ValPtr = V.dyn_cast<const Value*>())
AddrSpace = ValPtr->getType()->getPointerAddressSpace();
else
AddrSpace = V.get<const PseudoSourceValue*>()->getAddressSpace();
}
}
MachinePointerInfo getWithOffset(int64_t O) const {
if (V.isNull())
return MachinePointerInfo(AddrSpace);

6
include/llvm/CodeGen/TargetLowering.h
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@ -702,7 +702,10 @@ public:
struct IntrinsicInfo {
unsigned opc = 0; // target opcode
EVT memVT; // memory VT
const Value* ptrVal = nullptr; // value representing memory location
// value representing memory location
PointerUnion<const Value *, const PseudoSourceValue *> ptrVal;
int offset = 0; // offset off of ptrVal
unsigned size = 0; // the size of the memory location
// (taken from memVT if zero)
@ -717,6 +720,7 @@ public:
/// true and store the intrinsic information into the IntrinsicInfo that was
/// passed to the function.
virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
MachineFunction &,
unsigned /*Intrinsic*/) const {
return false;
}

2
lib/CodeGen/GlobalISel/IRTranslator.cpp
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@ -851,7 +851,7 @@ bool IRTranslator::translateCall(const User &U, MachineIRBuilder &MIRBuilder) {
const TargetLowering &TLI = *MF->getSubtarget().getTargetLowering();
TargetLowering::IntrinsicInfo Info;
// TODO: Add a GlobalISel version of getTgtMemIntrinsic.
if (TLI.getTgtMemIntrinsic(Info, CI, ID)) {
if (TLI.getTgtMemIntrinsic(Info, CI, *MF, ID)) {
uint64_t Size = Info.memVT.getStoreSize();
MIB.addMemOperand(MF->getMachineMemOperand(MachinePointerInfo(Info.ptrVal),
Info.flags, Size, Info.align));

4
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
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@ -4214,7 +4214,9 @@ void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
// Info is set by getTgtMemInstrinsic
TargetLowering::IntrinsicInfo Info;
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I,
DAG.getMachineFunction(),
Intrinsic);
// Add the intrinsic ID as an integer operand if it's not a target intrinsic.
if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||

1
lib/Target/AArch64/AArch64ISelLowering.cpp
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@ -7371,6 +7371,7 @@ SDValue AArch64TargetLowering::LowerVECREDUCE(SDValue Op,
/// specified in the intrinsic calls.
bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
const CallInst &I,
MachineFunction &MF,
unsigned Intrinsic) const {
auto &DL = I.getModule()->getDataLayout();
switch (Intrinsic) {

1
lib/Target/AArch64/AArch64ISelLowering.h
View File

@ -306,6 +306,7 @@ public:
MachineBasicBlock *MBB) const override;
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
MachineFunction &MF,
unsigned Intrinsic) const override;
bool isTruncateFree(Type *Ty1, Type *Ty2) const override;

1
lib/Target/AMDGPU/SIISelLowering.cpp
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@ -558,6 +558,7 @@ bool SITargetLowering::isShuffleMaskLegal(ArrayRef<int>, EVT) const {
bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
const CallInst &CI,
MachineFunction &MF,
unsigned IntrID) const {
switch (IntrID) {
case Intrinsic::amdgcn_atomic_inc:

1
lib/Target/AMDGPU/SIISelLowering.h
View File

@ -152,6 +152,7 @@ public:
bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override;
bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
MachineFunction &MF,
unsigned IntrinsicID) const override;
bool getAddrModeArguments(IntrinsicInst * /*I*/,

1
lib/Target/ARM/ARMISelLowering.cpp
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@ -13588,6 +13588,7 @@ bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
/// specified in the intrinsic calls.
bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
const CallInst &I,
MachineFunction &MF,
unsigned Intrinsic) const {
switch (Intrinsic) {
case Intrinsic::arm_neon_vld1:

1
lib/Target/ARM/ARMISelLowering.h
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@ -470,6 +470,7 @@ class VectorType;
bool getTgtMemIntrinsic(IntrinsicInfo &Info,
const CallInst &I,
MachineFunction &MF,
unsigned Intrinsic) const override;
/// \brief Returns true if it is beneficial to convert a load of a constant

1
lib/Target/Hexagon/HexagonISelLowering.cpp
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@ -2261,6 +2261,7 @@ const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
/// passed to the function.
bool HexagonTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
const CallInst &I,
MachineFunction &MF,
unsigned Intrinsic) const {
switch (Intrinsic) {
case Intrinsic::hexagon_V6_vgathermw:

1
lib/Target/Hexagon/HexagonISelLowering.h
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@ -103,6 +103,7 @@ namespace HexagonISD {
const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const;
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
MachineFunction &MF,
unsigned Intrinsic) const override;
bool isTruncateFree(Type *Ty1, Type *Ty2) const override;

3
lib/Target/NVPTX/NVPTXISelLowering.cpp
View File

@ -3314,7 +3314,8 @@ static unsigned getOpcForSurfaceInstr(unsigned Intrinsic) {
// of destination
// pointer. In particular, the address space information.
bool NVPTXTargetLowering::getTgtMemIntrinsic(
IntrinsicInfo &Info, const CallInst &I, unsigned Intrinsic) const {
IntrinsicInfo &Info, const CallInst &I,
MachineFunction &MF, unsigned Intrinsic) const {
switch (Intrinsic) {
default:
return false;

1
lib/Target/NVPTX/NVPTXISelLowering.h
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@ -448,6 +448,7 @@ public:
const char *getTargetNodeName(unsigned Opcode) const override;
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
MachineFunction &MF,
unsigned Intrinsic) const override;
/// isLegalAddressingMode - Return true if the addressing mode represented

1
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -13295,6 +13295,7 @@ PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
const CallInst &I,
MachineFunction &MF,
unsigned Intrinsic) const {
switch (Intrinsic) {
case Intrinsic::ppc_qpx_qvlfd:

1
lib/Target/PowerPC/PPCISelLowering.h
View File

@ -773,6 +773,7 @@ namespace llvm {
bool getTgtMemIntrinsic(IntrinsicInfo &Info,
const CallInst &I,
MachineFunction &MF,
unsigned Intrinsic) const override;
/// getOptimalMemOpType - Returns the target specific optimal type for load

1
lib/Target/X86/X86ISelLowering.cpp
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@ -4483,6 +4483,7 @@ static bool hasFPCMov(unsigned X86CC) {
bool X86TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
const CallInst &I,
MachineFunction &MF,
unsigned Intrinsic) const {
const IntrinsicData* IntrData = getIntrinsicWithChain(Intrinsic);

1
lib/Target/X86/X86ISelLowering.h
View File

@ -965,6 +965,7 @@ namespace llvm {
/// true and stores the intrinsic information into the IntrinsicInfo that was
/// passed to the function.
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
MachineFunction &MF,
unsigned Intrinsic) const override;
/// Returns true if the target can instruction select the