diff --git a/test/CodeGen/AVR/ctlz.ll b/test/CodeGen/AVR/ctlz.ll
new file mode 100644
index 00000000000..a49e80bd7ab
--- /dev/null
+++ b/test/CodeGen/AVR/ctlz.ll
@@ -0,0 +1,48 @@
+; RUN: llc < %s -march=avr | FileCheck %s
+
+define i8 @count_leading_zeros(i8) unnamed_addr {
+entry-block:
+  %1 = tail call i8 @llvm.ctlz.i8(i8 %0)
+  ret i8 %1
+}
+
+declare i8 @llvm.ctlz.i8(i8)
+
+; CHECK-LABEL: count_leading_zeros:
+; CHECK: cpi    [[RESULT:r[0-9]+]], 0
+; CHECK: breq   LBB0_2
+; CHECK: mov    [[SCRATCH:r[0-9]+]], {{.*}}[[RESULT]]
+; CHECK: lsr    {{.*}}[[SCRATCH]]
+; CHECK: or     {{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
+; CHECK: mov    {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
+; CHECK: lsr    {{.*}}[[RESULT]]
+; CHECK: lsr    {{.*}}[[RESULT]]
+; CHECK: or     {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
+; CHECK: mov    {{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
+; CHECK: lsr    {{.*}}[[SCRATCH]]
+; CHECK: lsr    {{.*}}[[SCRATCH]]
+; CHECK: lsr    {{.*}}[[SCRATCH]]
+; CHECK: lsr    {{.*}}[[SCRATCH]]
+; CHECK: or     {{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
+; CHECK: com    {{.*}}[[SCRATCH]]
+; CHECK: mov    {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
+; CHECK: lsr    {{.*}}[[RESULT]]
+; CHECK: andi   {{.*}}[[RESULT]], 85
+; CHECK: sub    {{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
+; CHECK: mov    {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
+; CHECK: andi   {{.*}}[[RESULT]], 51
+; CHECK: lsr    {{.*}}[[SCRATCH]]
+; CHECK: lsr    {{.*}}[[SCRATCH]]
+; CHECK: andi   {{.*}}[[SCRATCH]], 51
+; CHECK: add    {{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
+; CHECK: mov    {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
+; CHECK: lsr    {{.*}}[[RESULT]]
+; CHECK: lsr    {{.*}}[[RESULT]]
+; CHECK: lsr    {{.*}}[[RESULT]]
+; CHECK: lsr    {{.*}}[[RESULT]]
+; CHECK: add    {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
+; CHECK: andi   {{.*}}[[RESULT]], 15
+; CHECK: ret
+; CHECK: LBB0_2:
+; CHECK: ldi    {{.*}}[[RESULT]], 8
+; CHECK: ret
diff --git a/test/CodeGen/AVR/cttz.ll b/test/CodeGen/AVR/cttz.ll
new file mode 100644
index 00000000000..61f2e69d241
--- /dev/null
+++ b/test/CodeGen/AVR/cttz.ll
@@ -0,0 +1,40 @@
+; RUN: llc < %s -march=avr | FileCheck %s
+
+define i8 @count_trailing_zeros(i8) unnamed_addr {
+entry-block:
+  %1 = tail call i8 @llvm.cttz.i8(i8 %0)
+  ret i8 %1
+}
+
+declare i8 @llvm.cttz.i8(i8)
+
+; CHECK-LABEL: count_trailing_zeros:
+; CHECK: cpi    [[RESULT:r[0-9]+]], 0
+; CHECK: breq   LBB0_2
+; CHECK: mov    [[SCRATCH:r[0-9]+]], {{.*}}[[RESULT]]
+; CHECK: dec    {{.*}}[[SCRATCH]]
+; CHECK: com    {{.*}}[[RESULT]]
+; CHECK: and    {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
+; CHECK: mov    {{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
+; CHECK: lsr    {{.*}}[[SCRATCH]]
+; CHECK: andi   {{.*}}[[SCRATCH]], 85
+; CHECK: sub    {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
+; CHECK: mov    {{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
+; CHECK: andi   {{.*}}[[SCRATCH]], 51
+; CHECK: lsr    {{.*}}[[RESULT]]
+; CHECK: lsr    {{.*}}[[RESULT]]
+; CHECK: andi   {{.*}}[[RESULT]], 51
+; CHECK: add    {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
+; CHECK: mov    {{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
+; CHECK: lsr    {{.*}}[[SCRATCH]]
+; CHECK: lsr    {{.*}}[[SCRATCH]]
+; CHECK: lsr    {{.*}}[[SCRATCH]]
+; CHECK: lsr    {{.*}}[[SCRATCH]]
+; CHECK: add    {{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
+; CHECK: andi   {{.*}}[[SCRATCH]], 15
+; CHECK: mov    {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
+; CHECK: ret
+; CHECK: LBB0_2:
+; CHECK: ldi    {{.*}}[[SCRATCH]], 8
+; CHECK: mov    {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
+; CHECK: ret