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[mips] Optimize materialization of i64 constants

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Avoid MipsAnalyzeImmediate usage if the constant fits in an 32-bit
integer. This allows us to generate the same instructions for the
materialization of the same constants regardless the width of their
type.

Patch by: Vasileios Kalintiris

Contributions by: Simon Dardis

Reviewers: Daniel Sanders

Differential Review: https://reviews.llvm.org/D21689

llvm-svn: 276628
This commit is contained in:
Simon Dardis 2016-07-25 09:57:28 +00:00
parent 4b055f7546
commit ec8cfdd35b
14 changed files with 134 additions and 93 deletions
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3
lib/Target/Mips/MicroMips64r6InstrInfo.td
View File

@ -414,6 +414,9 @@ let DecoderNamespace = "MicroMipsR6" in {
ISA_MICROMIPS64R6;
}
let AdditionalPredicates = [InMicroMips] in
defm : MaterializeImms<i64, ZERO_64, DADDIU_MM64R6, LUi64, ORi64>;
//===----------------------------------------------------------------------===//
//
// Arbitrary patterns that map to one or more instructions

6
lib/Target/Mips/MicroMipsInstrInfo.td
View File

@ -981,6 +981,12 @@ let DecoderNamespace = "MicroMips" in {
// MicroMips arbitrary patterns that map to one or more instructions
//===----------------------------------------------------------------------===//
def : MipsPat<(i32 immLi16:$imm),
(LI16_MM immLi16:$imm)>;
let AdditionalPredicates = [InMicroMips] in
defm : MaterializeImms<i32, ZERO, ADDiu_MM, LUi_MM, ORi_MM>;
let Predicates = [InMicroMips] in {
def : MipsPat<(i32 immLi16:$imm),
(LI16_MM immLi16:$imm)>;

10
lib/Target/Mips/Mips64InstrInfo.td
View File

@ -494,6 +494,16 @@ def DMTC2 : MTC3OP<"dmtc2", COP2Opnd, GPR64Opnd, II_DMTC2>, MFC3OP_FM<0x12, 5>,
// Arbitrary patterns that map to one or more instructions
//===----------------------------------------------------------------------===//
// Materialize i64 constants.
defm : MaterializeImms<i64, ZERO_64, DADDiu, LUi64, ORi64>;
def : MipsPat<(i64 immZExt32Low16Zero:$imm),
(DSLL (ORi64 ZERO_64, (HI16 imm:$imm)), 16)>;
def : MipsPat<(i64 immZExt32:$imm),
(ORi64 (DSLL (ORi64 ZERO_64, (HI16 imm:$imm)), 16),
(LO16 imm:$imm))>;
// extended loads
def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>;
def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>;

39
lib/Target/Mips/MipsInstrInfo.td
View File

@ -1052,11 +1052,23 @@ def immZExt16 : PatLeaf<(imm), [{
}], LO16>;
// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
def immLow16Zero : PatLeaf<(imm), [{
def immSExt32Low16Zero : PatLeaf<(imm), [{
int64_t Val = N->getSExtValue();
return isInt<32>(Val) && !(Val & 0xffff);
}]>;
// Zero-extended 32-bit unsigned int with lower 16-bit cleared.
def immZExt32Low16Zero : PatLeaf<(imm), [{
uint64_t Val = N->getZExtValue();
return isUInt<32>(Val) && !(Val & 0xffff);
}]>;
// Note immediate fits as a 32 bit signed extended on target immediate.
def immSExt32 : PatLeaf<(imm), [{ return isInt<32>(N->getSExtValue()); }]>;
// Note immediate fits as a 32 bit zero extended on target immediate.
def immZExt32 : PatLeaf<(imm), [{ return isUInt<32>(N->getZExtValue()); }]>;
// shamt field must fit in 5 bits.
def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
@ -2454,19 +2466,24 @@ class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
// Materialize constants.
multiclass MaterializeImms<ValueType VT, Register ZEROReg,
Instruction ADDiuOp, Instruction LUiOp,
Instruction ORiOp> {
// Small immediates
let AdditionalPredicates = [NotInMicroMips] in {
def : MipsPat<(i32 immSExt16:$in),
(ADDiu ZERO, imm:$in)>;
def : MipsPat<(i32 immZExt16:$in),
(ORi ZERO, imm:$in)>;
}
def : MipsPat<(i32 immLow16Zero:$in),
(LUi (HI16 imm:$in))>;
def : MipsPat<(VT immSExt16:$imm), (ADDiuOp ZEROReg, imm:$imm)>;
def : MipsPat<(VT immZExt16:$imm), (ORiOp ZEROReg, imm:$imm)>;
// Bits 32-16 set, sign/zero extended.
def : MipsPat<(VT immSExt32Low16Zero:$imm), (LUiOp (HI16 imm:$imm))>;
// Arbitrary immediates
def : MipsPat<(i32 imm:$imm),
(ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
def : MipsPat<(VT immSExt32:$imm), (ORiOp (LUiOp (HI16 imm:$imm)), (LO16 imm:$imm))>;
}
let AdditionalPredicates = [NotInMicroMips] in
defm : MaterializeImms<i32, ZERO, ADDiu, LUi, ORi>;
// Carry MipsPatterns
let AdditionalPredicates = [NotInMicroMips] in {

4
lib/Target/Mips/MipsSEISelDAGToDAG.cpp
View File

@ -771,13 +771,13 @@ bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) {
case ISD::Constant: {
const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
int64_t Imm = CN->getSExtValue();
unsigned Size = CN->getValueSizeInBits(0);
if (Size == 32)
if (isInt<32>(Imm))
break;
MipsAnalyzeImmediate AnalyzeImm;
int64_t Imm = CN->getSExtValue();
const MipsAnalyzeImmediate::InstSeq &Seq =
AnalyzeImm.Analyze(Imm, Size, false);

25
test/CodeGen/Mips/cmov.ll
View File

@ -517,18 +517,23 @@ entry:
; 64-CMOV-DAG: daddiu $[[I5:[0-9]+]], $zero, 5
; 64-CMOV-DAG: daddiu $[[I4:2]], $zero, 4
; 64-CMOV-DAG: daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, 32766
; 64-CMOV-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4
; 64-CMOV-DAG: movn $[[I4]], $[[I5]], $[[R0]]
; 64-CMP-DAG: daddiu $[[I4:[0-9]+]], $zero, 4
; 64-CMP-DAG: daddiu $[[I5:2]], $zero, 5
; 64-CMP-DAG: daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, 32766
; 64-CMP-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4
; 64-CMOV-DAG: lui $[[R1:[0-9]+]], 65535
; 64-CMOV-DAG: ori $[[R2:[0-9]+]], $[[R1]], 32766
; 64-CMOV-DAG: slt $[[R3:[0-9]+]], $[[R2]], $4
; 64-CMOV-DAG: movn $[[I4]], $[[I5]], $[[R3]]
; 64-CMP-DAG: daddiu $[[I5:[0-9]+]], $zero, 5
; 64-CMP-DAG: daddiu $[[I4:2]], $zero, 4
; 64-CMP-DAG: lui $[[R1:[0-9]+]], 65535
; 64-CMP-DAG: ori $[[R2:[0-9]+]], $[[R1]], 32766
; 64-CMP-DAG: slt $[[R3:[0-9]+]], $[[R2]], $4
; FIXME: We can do better than this by using selccz to choose between -0 and -2
; 64-CMP-DAG: seleqz $[[T0:[0-9]+]], $[[I4]], $[[R0]]
; 64-CMP-DAG: selnez $[[T1:[0-9]+]], $[[I5]], $[[R0]]
; 64-CMP-DAG: or $2, $[[T1]], $[[T0]]
; 64-CMP-DAG: seleqz $[[T1:[0-9]+]], $[[I4]], $[[R3]]
; 64-CMP-DAG: selnez $[[T0:[0-9]+]], $[[I5]], $[[R3]]
; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]
define i64 @slti64_3(i64 %a) {
entry:

60
test/CodeGen/Mips/fcmp.ll
View File

@ -29,7 +29,7 @@ define i32 @false_f32(float %a, float %b) nounwind {
; 64-CMP: addiu $2, $zero, 0
; MM-DAG: lui $2, 0
; MM-DAG: li16 $2, 0
%1 = fcmp false float %a, %b
%2 = zext i1 %1 to i32
@ -55,7 +55,7 @@ define i32 @oeq_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.eq.s $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
@ -89,7 +89,7 @@ define i32 @ogt_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ule.s $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
@ -123,7 +123,7 @@ define i32 @oge_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ult.s $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
@ -157,7 +157,7 @@ define i32 @olt_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.olt.s $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
@ -191,7 +191,7 @@ define i32 @ole_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ole.s $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
@ -227,7 +227,7 @@ define i32 @one_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ueq.s $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
@ -264,7 +264,7 @@ define i32 @ord_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.un.s $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
@ -299,7 +299,7 @@ define i32 @ueq_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ueq.s $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
@ -333,7 +333,7 @@ define i32 @ugt_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ole.s $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
@ -367,7 +367,7 @@ define i32 @uge_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.olt.s $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
@ -401,7 +401,7 @@ define i32 @ult_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ult.s $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
@ -435,7 +435,7 @@ define i32 @ule_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ule.s $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
@ -471,7 +471,7 @@ define i32 @une_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.eq.s $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
@ -506,7 +506,7 @@ define i32 @uno_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.un.s $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
@ -548,7 +548,7 @@ define i32 @false_f64(double %a, double %b) nounwind {
; 64-CMP: addiu $2, $zero, 0
; MM-DAG: lui $2, 0
; MM-DAG: li16 $2, 0
%1 = fcmp false double %a, %b
%2 = zext i1 %1 to i32
@ -574,7 +574,7 @@ define i32 @oeq_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.eq.d $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
@ -608,7 +608,7 @@ define i32 @ogt_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ule.d $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
@ -642,7 +642,7 @@ define i32 @oge_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ult.d $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
@ -676,7 +676,7 @@ define i32 @olt_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.olt.d $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
@ -710,7 +710,7 @@ define i32 @ole_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ole.d $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
@ -746,7 +746,7 @@ define i32 @one_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ueq.d $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
@ -783,7 +783,7 @@ define i32 @ord_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.un.d $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
@ -818,7 +818,7 @@ define i32 @ueq_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ueq.d $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
@ -852,7 +852,7 @@ define i32 @ugt_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ole.d $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
@ -886,7 +886,7 @@ define i32 @uge_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.olt.d $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
@ -920,7 +920,7 @@ define i32 @ult_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ult.d $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
@ -954,7 +954,7 @@ define i32 @ule_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ule.d $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
@ -990,7 +990,7 @@ define i32 @une_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.eq.d $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
@ -1025,7 +1025,7 @@ define i32 @uno_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.un.d $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0

4
test/CodeGen/Mips/llvm-ir/add.ll
View File

@ -284,7 +284,7 @@ define signext i128 @add_i128_4(i128 signext %a) {
; MM32: li16 $[[T1:[0-9]+]], 4
; MM32: sltu $[[T1]], $[[T0]], $[[T1]]
; MM32: addu $[[T2:[0-9]+]], $6, $[[T1]]
; MM32: lui $[[T1]], 0
; MM32: li16 $[[T1]], 0
; MM32: sltu $[[T3:[0-9]+]], $[[T2]], $[[T1]]
; MM32: addu $[[T3]], $5, $[[T3]]
; MM32: sltu $[[T1]], $[[T3]], $[[T1]]
@ -414,7 +414,7 @@ define signext i128 @add_i128_3(i128 signext %a) {
; MM32: li16 $[[T1:[0-9]+]], 3
; MM32: sltu $[[T1]], $[[T0]], $[[T1]]
; MM32: addu $[[T2:[0-9]+]], $6, $[[T1]]
; MM32: lui $[[T3:[0-9]+]], 0
; MM32: li16 $[[T3:[0-9]+]], 0
; MM32: sltu $[[T4:[0-9]+]], $[[T2]], $[[T3]]
; MM32: addu $[[T4]], $5, $[[T4]]
; MM32: sltu $[[T5:[0-9]+]], $[[T4]], $[[T3]]

66
test/CodeGen/Mips/llvm-ir/and.ll
View File

@ -155,7 +155,7 @@ entry:
; GP64: addiu $2, $zero, 0
; MM: lui $2, 0
; MM: li16 $2, 0
%r = and i1 4, %b
ret i1 %r
@ -213,7 +213,7 @@ entry:
; GP64: andi $2, $4, 4
; MM32: andi16 $3, $5, 4
; MM32: lui $2, 0
; MM32: li16 $2, 0
; MM64: andi $2, $4, 4
@ -234,9 +234,9 @@ entry:
; GP64: daddiu $2, $zero, 0
; MM32: andi16 $5, $7, 4
; MM32: lui $2, 0
; MM32: lui $3, 0
; MM32: lui $4, 0
; MM32: li16 $2, 0
; MM32: li16 $3, 0
; MM32: li16 $4, 0
; MM64: andi $3, $5, 4
; MM64: daddiu $2, $zero, 0
@ -307,7 +307,7 @@ entry:
; GP64: andi $2, $4, 31
; MM32: andi16 $3, $5, 31
; MM32: lui $2, 0
; MM32: li16 $2, 0
; MM64: andi $2, $4, 31
@ -328,9 +328,9 @@ entry:
; GP64: daddiu $2, $zero, 0
; MM32: andi16 $5, $7, 31
; MM32: lui $2, 0
; MM32: lui $3, 0
; MM32: lui $4, 0
; MM32: li16 $2, 0
; MM32: li16 $3, 0
; MM32: li16 $4, 0
; MM64: andi $3, $5, 31
; MM64: daddiu $2, $zero, 0
@ -397,7 +397,7 @@ entry:
; GP64: andi $2, $4, 255
; MM32: andi16 $3, $5, 255
; MM32: lui $2, 0
; MM32: li16 $2, 0
; MM64: andi $2, $4, 255
@ -418,9 +418,9 @@ entry:
; GP64: daddiu $2, $zero, 0
; MM32: andi16 $5, $7, 255
; MM32: lui $2, 0
; MM32: lui $3, 0
; MM32: lui $4, 0
; MM32: li16 $2, 0
; MM32: li16 $3, 0
; MM32: li16 $4, 0
; MM64: andi $3, $5, 255
; MM64: daddiu $2, $zero, 0
@ -437,7 +437,7 @@ entry:
; GP64: addiu $2, $zero, 0
; MM: lui $2, 0
; MM: li16 $2, 0
%r = and i1 32768, %b
ret i1 %r
@ -451,7 +451,7 @@ entry:
; GP64: addiu $2, $zero, 0
; MM: lui $2, 0
; MM: li16 $2, 0
%r = and i8 32768, %b
ret i8 %r
@ -498,7 +498,7 @@ entry:
; GP64: andi $2, $4, 32768
; MM32: andi16 $3, $5, 32768
; MM32: lui $2, 0
; MM32: li16 $2, 0
; MM64: andi $2, $4, 32768
@ -519,9 +519,9 @@ entry:
; GP64: daddiu $2, $zero, 0
; MM32: andi16 $5, $7, 32768
; MM32: lui $2, 0
; MM32: lui $3, 0
; MM32: lui $4, 0
; MM32: li16 $2, 0
; MM32: li16 $3, 0
; MM32: li16 $4, 0
; MM64: andi $3, $5, 32768
; MM64: daddiu $2, $zero, 0
@ -579,8 +579,8 @@ entry:
; GP64: andi $2, $4, 65
; MM32: andi $3, $5, 65
; MM32: lui $2, 0
; MM32-DAG: andi $3, $5, 65
; MM32-DAG: li16 $2, 0
; MM64: andi $2, $4, 65
@ -600,10 +600,10 @@ entry:
; GP64: andi $3, $5, 65
; GP64: daddiu $2, $zero, 0
; MM32: andi $5, $7, 65
; MM32: lui $2, 0
; MM32: lui $3, 0
; MM32: lui $4, 0
; MM32-DAG: andi $5, $7, 65
; MM32-DAG: li16 $2, 0
; MM32-DAG: li16 $3, 0
; MM32-DAG: li16 $4, 0
; MM64: andi $3, $5, 65
; MM64: daddiu $2, $zero, 0
@ -620,7 +620,7 @@ entry:
; GP64: addiu $2, $zero, 0
; MM: lui $2, 0
; MM: li16 $2, 0
%r = and i1 256, %b
ret i1 %r
@ -634,7 +634,7 @@ entry:
; GP64: addiu $2, $zero, 0
; MM: lui $2, 0
; MM: li16 $2, 0
%r = and i8 256, %b
ret i8 %r
@ -669,8 +669,8 @@ entry:
; GP64: andi $2, $4, 256
; MM32: andi $3, $5, 256
; MM32: lui $2, 0
; MM32-DAG: andi $3, $5, 256
; MM32-DAG: li16 $2, 0
; MM64: andi $2, $4, 256
@ -690,10 +690,10 @@ entry:
; GP64: andi $3, $5, 256
; GP64: daddiu $2, $zero, 0
; MM32: andi $5, $7, 256
; MM32: lui $2, 0
; MM32: lui $3, 0
; MM32: lui $4, 0
; MM32-DAG: andi $5, $7, 256
; MM32-DAG: li16 $2, 0
; MM32-DAG: li16 $3, 0
; MM32-DAG: li16 $4, 0
; MM64: andi $3, $5, 256
; MM64: daddiu $2, $zero, 0

2
test/CodeGen/Mips/llvm-ir/lshr.ll
View File

@ -130,7 +130,7 @@ entry:
; MMR3: srlv $[[T5:[0-9]+]], $4, $7
; MMR3: andi16 $[[T6:[0-9]+]], $7, 32
; MMR3: movn $[[T7:[0-9]+]], $[[T5]], $[[T6]]
; MMR3: lui $[[T8:[0-9]+]], 0
; MMR3: li16 $[[T8:[0-9]+]], 0
; MMR3: movn $2, $[[T8]], $[[T6]]
; MMR6: srlv $[[T0:[0-9]+]], $5, $7

2
test/CodeGen/Mips/llvm-ir/ret.ll
View File

@ -113,7 +113,7 @@ define i64 @ret_i64_65537() {
; GPR32-DAG: ori $3, $[[T0]], 1
; GPR32-DAG: addiu $2, $zero, 0
; GPR64-DAG: daddiu $2, $[[T0]], 1
; GPR64-DAG: ori $2, $[[T0]], 1
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR

2
test/CodeGen/Mips/llvm-ir/select-int.ll
View File

@ -258,7 +258,7 @@ define i8* @tst_select_word_cst(i8* %a, i8* %b) {
; MM32R3: li16 $[[T0:[0-9]+]], -1
; MM32R3: xor $[[T1:[0-9]+]], $5, $[[T0]]
; MM32R3: lui $[[T2:[0-9]+]], 0
; MM32R3: li16 $[[T2:[0-9]+]], 0
; MM32R3: movn $[[T3:[0-9]+]], $[[T2]], $[[T1]]
; MM32R3: move $2, $[[T3]]

2
test/CodeGen/Mips/llvm-ir/shl.ll
View File

@ -146,7 +146,7 @@ entry:
; MMR3: sllv $[[T5:[0-9]+]], $5, $7
; MMR3: andi16 $[[T6:[0-9]+]], $7, 32
; MMR3: movn $[[T7:[0-9]+]], $[[T5]], $[[T6]]
; MMR3: lui $[[T8:[0-9]+]], 0
; MMR3: li16 $[[T8:[0-9]+]], 0
; MMR3: movn $3, $[[T8]], $[[T6]]
; MMR6: sllv $[[T0:[0-9]+]], $4, $7

2
test/CodeGen/Mips/mips64imm.ll
View File

@ -13,7 +13,7 @@ define i64 @foo3() nounwind readnone {
entry:
; CHECK: foo3
; CHECK: lui $[[R0:[0-9]+]], 4660
; CHECK: daddiu ${{[0-9]+}}, $[[R0]], 22136
; CHECK: ori ${{[0-9]+}}, $[[R0]], 22136
ret i64 305419896
}