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Thumb2 LDM instructions can target PC. Make sure to encode it.

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PR11220

llvm-svn: 142801
This commit is contained in:
Jim Grosbach 2011-10-24 17:16:24 +00:00
parent 077c57fc9d
commit eceea163ef
1 changed files with 4 additions and 8 deletions
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12
lib/Target/ARM/ARMInstrThumb2.td
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@ -1543,8 +1543,7 @@ multiclass thumb2_ld_mult<string asm, InstrItinClass itin,
let Inst{21} = 0; // No writeback
let Inst{20} = L_bit;
let Inst{19-16} = Rn;
let Inst{15} = 0;
let Inst{14-0} = regs{14-0};
let Inst{15-0} = regs;
}
def IA_UPD :
T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
@ -1559,8 +1558,7 @@ multiclass thumb2_ld_mult<string asm, InstrItinClass itin,
let Inst{21} = 1; // Writeback
let Inst{20} = L_bit;
let Inst{19-16} = Rn;
let Inst{15} = 0;
let Inst{14-0} = regs{14-0};
let Inst{15-0} = regs;
}
def DB :
T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
@ -1575,8 +1573,7 @@ multiclass thumb2_ld_mult<string asm, InstrItinClass itin,
let Inst{21} = 0; // No writeback
let Inst{20} = L_bit;
let Inst{19-16} = Rn;
let Inst{15} = 0;
let Inst{14-0} = regs{14-0};
let Inst{15-0} = regs;
}
def DB_UPD :
T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
@ -1591,8 +1588,7 @@ multiclass thumb2_ld_mult<string asm, InstrItinClass itin,
let Inst{21} = 1; // Writeback
let Inst{20} = L_bit;
let Inst{19-16} = Rn;
let Inst{15} = 0;
let Inst{14-0} = regs{14-0};
let Inst{15-0} = regs;
}
}