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https://github.com/RPCS3/llvm-mirror.git
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Add and adjust saturating tests. NFC
This adds some extra testing to the existing [su][add/sub]_sat X86 and AArch64 tests and adds equivalent tests for ARM. llvm-svn: 374169
This commit is contained in:
David Green
parent
7a73112681
commit
ed6415380f
@ -1,10 +1,12 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
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declare i4 @llvm.sadd.sat.i4 (i4, i4)
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declare i32 @llvm.sadd.sat.i32 (i32, i32)
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declare i64 @llvm.sadd.sat.i64 (i64, i64)
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declare <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32>, <4 x i32>)
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declare i4 @llvm.sadd.sat.i4(i4, i4)
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declare i8 @llvm.sadd.sat.i8(i8, i8)
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declare i16 @llvm.sadd.sat.i16(i16, i16)
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declare i32 @llvm.sadd.sat.i32(i32, i32)
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declare i64 @llvm.sadd.sat.i64(i64, i64)
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declare <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32>, <4 x i32>)
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define i32 @func(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: func:
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@ -34,6 +36,38 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
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ret i64 %tmp;
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}
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define i16 @func16(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: func16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl w8, w0, #16
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; CHECK-NEXT: adds w10, w8, w1, lsl #16
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; CHECK-NEXT: mov w9, #2147483647
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; CHECK-NEXT: cmp w10, #0 // =0
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; CHECK-NEXT: cinv w9, w9, ge
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; CHECK-NEXT: adds w8, w8, w1, lsl #16
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; CHECK-NEXT: csel w8, w9, w8, vs
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; CHECK-NEXT: asr w0, w8, #16
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; CHECK-NEXT: ret
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%tmp = call i16 @llvm.sadd.sat.i16(i16 %x, i16 %y);
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ret i16 %tmp;
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}
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define i8 @func8(i8 %x, i8 %y) nounwind {
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; CHECK-LABEL: func8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl w8, w0, #24
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; CHECK-NEXT: adds w10, w8, w1, lsl #24
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; CHECK-NEXT: mov w9, #2147483647
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; CHECK-NEXT: cmp w10, #0 // =0
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; CHECK-NEXT: cinv w9, w9, ge
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; CHECK-NEXT: adds w8, w8, w1, lsl #24
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; CHECK-NEXT: csel w8, w9, w8, vs
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; CHECK-NEXT: asr w0, w8, #24
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; CHECK-NEXT: ret
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%tmp = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %y);
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ret i8 %tmp;
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}
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define i4 @func3(i4 %x, i4 %y) nounwind {
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; CHECK-LABEL: func3:
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; CHECK: // %bb.0:
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@ -1,10 +1,12 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
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declare i4 @llvm.ssub.sat.i4 (i4, i4)
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declare i32 @llvm.ssub.sat.i32 (i32, i32)
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declare i64 @llvm.ssub.sat.i64 (i64, i64)
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declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32>, <4 x i32>)
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declare i4 @llvm.ssub.sat.i4(i4, i4)
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declare i8 @llvm.ssub.sat.i8(i8, i8)
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declare i16 @llvm.ssub.sat.i16(i16, i16)
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declare i32 @llvm.ssub.sat.i32(i32, i32)
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declare i64 @llvm.ssub.sat.i64(i64, i64)
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declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32>, <4 x i32>)
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define i32 @func(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: func:
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@ -34,6 +36,38 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
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ret i64 %tmp;
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}
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define i16 @func16(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: func16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl w8, w0, #16
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; CHECK-NEXT: subs w10, w8, w1, lsl #16
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; CHECK-NEXT: mov w9, #2147483647
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; CHECK-NEXT: cmp w10, #0 // =0
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; CHECK-NEXT: cinv w9, w9, ge
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; CHECK-NEXT: subs w8, w8, w1, lsl #16
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; CHECK-NEXT: csel w8, w9, w8, vs
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; CHECK-NEXT: asr w0, w8, #16
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; CHECK-NEXT: ret
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%tmp = call i16 @llvm.ssub.sat.i16(i16 %x, i16 %y);
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ret i16 %tmp;
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}
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define i8 @func8(i8 %x, i8 %y) nounwind {
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; CHECK-LABEL: func8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl w8, w0, #24
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; CHECK-NEXT: subs w10, w8, w1, lsl #24
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; CHECK-NEXT: mov w9, #2147483647
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; CHECK-NEXT: cmp w10, #0 // =0
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; CHECK-NEXT: cinv w9, w9, ge
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; CHECK-NEXT: subs w8, w8, w1, lsl #24
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; CHECK-NEXT: csel w8, w9, w8, vs
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; CHECK-NEXT: asr w0, w8, #24
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; CHECK-NEXT: ret
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%tmp = call i8 @llvm.ssub.sat.i8(i8 %x, i8 %y);
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ret i8 %tmp;
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}
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define i4 @func3(i4 %x, i4 %y) nounwind {
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; CHECK-LABEL: func3:
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; CHECK: // %bb.0:
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@ -1,9 +1,11 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
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declare i4 @llvm.uadd.sat.i4 (i4, i4)
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declare i32 @llvm.uadd.sat.i32 (i32, i32)
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declare i64 @llvm.uadd.sat.i64 (i64, i64)
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declare i4 @llvm.uadd.sat.i4(i4, i4)
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declare i8 @llvm.uadd.sat.i8(i8, i8)
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declare i16 @llvm.uadd.sat.i16(i16, i16)
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declare i32 @llvm.uadd.sat.i32(i32, i32)
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declare i64 @llvm.uadd.sat.i64(i64, i64)
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define i32 @func(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: func:
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@ -25,6 +27,30 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
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ret i64 %tmp;
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}
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define i16 @func16(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: func16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl w8, w0, #16
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; CHECK-NEXT: adds w8, w8, w1, lsl #16
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; CHECK-NEXT: csinv w8, w8, wzr, lo
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; CHECK-NEXT: lsr w0, w8, #16
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; CHECK-NEXT: ret
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%tmp = call i16 @llvm.uadd.sat.i16(i16 %x, i16 %y);
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ret i16 %tmp;
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}
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define i8 @func8(i8 %x, i8 %y) nounwind {
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; CHECK-LABEL: func8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl w8, w0, #24
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; CHECK-NEXT: adds w8, w8, w1, lsl #24
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; CHECK-NEXT: csinv w8, w8, wzr, lo
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; CHECK-NEXT: lsr w0, w8, #24
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; CHECK-NEXT: ret
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%tmp = call i8 @llvm.uadd.sat.i8(i8 %x, i8 %y);
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ret i8 %tmp;
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}
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define i4 @func3(i4 %x, i4 %y) nounwind {
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; CHECK-LABEL: func3:
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; CHECK: // %bb.0:
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@ -1,9 +1,11 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
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declare i4 @llvm.usub.sat.i4 (i4, i4)
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declare i32 @llvm.usub.sat.i32 (i32, i32)
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declare i64 @llvm.usub.sat.i64 (i64, i64)
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declare i4 @llvm.usub.sat.i4(i4, i4)
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declare i8 @llvm.usub.sat.i8(i8, i8)
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declare i16 @llvm.usub.sat.i16(i16, i16)
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declare i32 @llvm.usub.sat.i32(i32, i32)
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declare i64 @llvm.usub.sat.i64(i64, i64)
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define i32 @func(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: func:
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@ -25,6 +27,30 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
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ret i64 %tmp;
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}
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define i16 @func16(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: func16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl w8, w0, #16
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; CHECK-NEXT: subs w8, w8, w1, lsl #16
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; CHECK-NEXT: csel w8, wzr, w8, lo
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; CHECK-NEXT: lsr w0, w8, #16
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; CHECK-NEXT: ret
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%tmp = call i16 @llvm.usub.sat.i16(i16 %x, i16 %y);
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ret i16 %tmp;
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}
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define i8 @func8(i8 %x, i8 %y) nounwind {
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; CHECK-LABEL: func8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl w8, w0, #24
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; CHECK-NEXT: subs w8, w8, w1, lsl #24
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; CHECK-NEXT: csel w8, wzr, w8, lo
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; CHECK-NEXT: lsr w0, w8, #24
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; CHECK-NEXT: ret
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%tmp = call i8 @llvm.usub.sat.i8(i8 %x, i8 %y);
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ret i8 %tmp;
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}
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define i4 @func3(i4 %x, i4 %y) nounwind {
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; CHECK-LABEL: func3:
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; CHECK: // %bb.0:
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415
test/CodeGen/ARM/sadd_sat.ll
Normal file
415
test/CodeGen/ARM/sadd_sat.ll
Normal file
@ -0,0 +1,415 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=CHECK-T1
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; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2NODSP
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; RUN: llc < %s -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2DSP
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; RUN: llc < %s -mtriple=armv8a-none-eabi | FileCheck %s --check-prefix=CHECK-ARM
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declare i4 @llvm.sadd.sat.i4(i4, i4)
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declare i8 @llvm.sadd.sat.i8(i8, i8)
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declare i16 @llvm.sadd.sat.i16(i16, i16)
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declare i32 @llvm.sadd.sat.i32(i32, i32)
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declare i64 @llvm.sadd.sat.i64(i64, i64)
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define i32 @func(i32 %x, i32 %y) nounwind {
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; CHECK-T1-LABEL: func:
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; CHECK-T1: @ %bb.0:
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; CHECK-T1-NEXT: mov r2, r0
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; CHECK-T1-NEXT: movs r3, #1
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; CHECK-T1-NEXT: adds r0, r0, r1
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; CHECK-T1-NEXT: mov r1, r3
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; CHECK-T1-NEXT: bmi .LBB0_2
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; CHECK-T1-NEXT: @ %bb.1:
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; CHECK-T1-NEXT: movs r1, #0
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; CHECK-T1-NEXT: .LBB0_2:
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; CHECK-T1-NEXT: cmp r1, #0
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; CHECK-T1-NEXT: bne .LBB0_4
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; CHECK-T1-NEXT: @ %bb.3:
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; CHECK-T1-NEXT: lsls r1, r3, #31
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; CHECK-T1-NEXT: cmp r0, r2
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; CHECK-T1-NEXT: bvs .LBB0_5
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; CHECK-T1-NEXT: b .LBB0_6
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; CHECK-T1-NEXT: .LBB0_4:
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; CHECK-T1-NEXT: ldr r1, .LCPI0_0
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; CHECK-T1-NEXT: cmp r0, r2
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; CHECK-T1-NEXT: bvc .LBB0_6
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; CHECK-T1-NEXT: .LBB0_5:
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; CHECK-T1-NEXT: mov r0, r1
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; CHECK-T1-NEXT: .LBB0_6:
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; CHECK-T1-NEXT: bx lr
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; CHECK-T1-NEXT: .p2align 2
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; CHECK-T1-NEXT: @ %bb.7:
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; CHECK-T1-NEXT: .LCPI0_0:
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; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
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;
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; CHECK-T2-LABEL: func:
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; CHECK-T2: @ %bb.0:
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; CHECK-T2-NEXT: adds r2, r0, r1
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; CHECK-T2-NEXT: mov.w r3, #0
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; CHECK-T2-NEXT: mov.w r1, #-2147483648
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; CHECK-T2-NEXT: it mi
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; CHECK-T2-NEXT: movmi r3, #1
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; CHECK-T2-NEXT: cmp r3, #0
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; CHECK-T2-NEXT: it ne
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; CHECK-T2-NEXT: mvnne r1, #-2147483648
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; CHECK-T2-NEXT: cmp r2, r0
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; CHECK-T2-NEXT: it vc
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; CHECK-T2-NEXT: movvc r1, r2
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; CHECK-T2-NEXT: mov r0, r1
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; CHECK-T2-NEXT: bx lr
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;
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; CHECK-ARM-LABEL: func:
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; CHECK-ARM: @ %bb.0:
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; CHECK-ARM-NEXT: adds r2, r0, r1
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; CHECK-ARM-NEXT: mov r3, #0
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; CHECK-ARM-NEXT: movwmi r3, #1
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; CHECK-ARM-NEXT: mov r1, #-2147483648
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; CHECK-ARM-NEXT: cmp r3, #0
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; CHECK-ARM-NEXT: mvnne r1, #-2147483648
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; CHECK-ARM-NEXT: cmp r2, r0
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; CHECK-ARM-NEXT: movvc r1, r2
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; CHECK-ARM-NEXT: mov r0, r1
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; CHECK-ARM-NEXT: bx lr
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%tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %y)
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ret i32 %tmp
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}
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define i64 @func2(i64 %x, i64 %y) nounwind {
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; CHECK-T1-LABEL: func2:
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; CHECK-T1: @ %bb.0:
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; CHECK-T1-NEXT: .save {r4, r5, r6, r7, lr}
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; CHECK-T1-NEXT: push {r4, r5, r6, r7, lr}
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; CHECK-T1-NEXT: .pad #4
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; CHECK-T1-NEXT: sub sp, #4
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; CHECK-T1-NEXT: str r2, [sp] @ 4-byte Spill
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; CHECK-T1-NEXT: mov r2, r0
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; CHECK-T1-NEXT: movs r4, #1
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; CHECK-T1-NEXT: movs r0, #0
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; CHECK-T1-NEXT: cmp r3, #0
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; CHECK-T1-NEXT: mov r5, r4
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; CHECK-T1-NEXT: bge .LBB1_2
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; CHECK-T1-NEXT: @ %bb.1:
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; CHECK-T1-NEXT: mov r5, r0
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; CHECK-T1-NEXT: .LBB1_2:
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; CHECK-T1-NEXT: cmp r1, #0
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; CHECK-T1-NEXT: mov r7, r4
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; CHECK-T1-NEXT: bge .LBB1_4
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; CHECK-T1-NEXT: @ %bb.3:
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; CHECK-T1-NEXT: mov r7, r0
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; CHECK-T1-NEXT: .LBB1_4:
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; CHECK-T1-NEXT: subs r6, r7, r5
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; CHECK-T1-NEXT: rsbs r5, r6, #0
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; CHECK-T1-NEXT: adcs r5, r6
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; CHECK-T1-NEXT: ldr r6, [sp] @ 4-byte Reload
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; CHECK-T1-NEXT: adds r6, r2, r6
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; CHECK-T1-NEXT: adcs r1, r3
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; CHECK-T1-NEXT: cmp r1, #0
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; CHECK-T1-NEXT: mov r2, r4
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; CHECK-T1-NEXT: bge .LBB1_6
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; CHECK-T1-NEXT: @ %bb.5:
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; CHECK-T1-NEXT: mov r2, r0
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; CHECK-T1-NEXT: .LBB1_6:
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; CHECK-T1-NEXT: subs r0, r7, r2
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; CHECK-T1-NEXT: subs r2, r0, #1
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; CHECK-T1-NEXT: sbcs r0, r2
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; CHECK-T1-NEXT: ands r5, r0
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; CHECK-T1-NEXT: beq .LBB1_8
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; CHECK-T1-NEXT: @ %bb.7:
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; CHECK-T1-NEXT: asrs r6, r1, #31
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; CHECK-T1-NEXT: .LBB1_8:
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; CHECK-T1-NEXT: cmp r1, #0
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; CHECK-T1-NEXT: bmi .LBB1_10
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; CHECK-T1-NEXT: @ %bb.9:
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; CHECK-T1-NEXT: lsls r2, r4, #31
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; CHECK-T1-NEXT: cmp r5, #0
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; CHECK-T1-NEXT: beq .LBB1_11
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; CHECK-T1-NEXT: b .LBB1_12
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; CHECK-T1-NEXT: .LBB1_10:
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; CHECK-T1-NEXT: ldr r2, .LCPI1_0
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; CHECK-T1-NEXT: cmp r5, #0
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; CHECK-T1-NEXT: bne .LBB1_12
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; CHECK-T1-NEXT: .LBB1_11:
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; CHECK-T1-NEXT: mov r2, r1
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; CHECK-T1-NEXT: .LBB1_12:
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; CHECK-T1-NEXT: mov r0, r6
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; CHECK-T1-NEXT: mov r1, r2
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; CHECK-T1-NEXT: add sp, #4
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; CHECK-T1-NEXT: pop {r4, r5, r6, r7, pc}
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; CHECK-T1-NEXT: .p2align 2
|
||||
; CHECK-T1-NEXT: @ %bb.13:
|
||||
; CHECK-T1-NEXT: .LCPI1_0:
|
||||
; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
|
||||
;
|
||||
; CHECK-T2-LABEL: func2:
|
||||
; CHECK-T2: @ %bb.0:
|
||||
; CHECK-T2-NEXT: .save {r7, lr}
|
||||
; CHECK-T2-NEXT: push {r7, lr}
|
||||
; CHECK-T2-NEXT: cmp.w r1, #-1
|
||||
; CHECK-T2-NEXT: mov.w lr, #0
|
||||
; CHECK-T2-NEXT: it gt
|
||||
; CHECK-T2-NEXT: movgt.w lr, #1
|
||||
; CHECK-T2-NEXT: adds r0, r0, r2
|
||||
; CHECK-T2-NEXT: adc.w r2, r1, r3
|
||||
; CHECK-T2-NEXT: movs r1, #0
|
||||
; CHECK-T2-NEXT: cmp.w r2, #-1
|
||||
; CHECK-T2-NEXT: it gt
|
||||
; CHECK-T2-NEXT: movgt r1, #1
|
||||
; CHECK-T2-NEXT: subs.w r1, lr, r1
|
||||
; CHECK-T2-NEXT: mov.w r12, #0
|
||||
; CHECK-T2-NEXT: it ne
|
||||
; CHECK-T2-NEXT: movne r1, #1
|
||||
; CHECK-T2-NEXT: cmp.w r3, #-1
|
||||
; CHECK-T2-NEXT: it gt
|
||||
; CHECK-T2-NEXT: movgt.w r12, #1
|
||||
; CHECK-T2-NEXT: sub.w r3, lr, r12
|
||||
; CHECK-T2-NEXT: clz r3, r3
|
||||
; CHECK-T2-NEXT: lsrs r3, r3, #5
|
||||
; CHECK-T2-NEXT: ands r3, r1
|
||||
; CHECK-T2-NEXT: mov.w r1, #-2147483648
|
||||
; CHECK-T2-NEXT: it ne
|
||||
; CHECK-T2-NEXT: asrne r0, r2, #31
|
||||
; CHECK-T2-NEXT: cmp r2, #0
|
||||
; CHECK-T2-NEXT: it mi
|
||||
; CHECK-T2-NEXT: mvnmi r1, #-2147483648
|
||||
; CHECK-T2-NEXT: cmp r3, #0
|
||||
; CHECK-T2-NEXT: it eq
|
||||
; CHECK-T2-NEXT: moveq r1, r2
|
||||
; CHECK-T2-NEXT: pop {r7, pc}
|
||||
;
|
||||
; CHECK-ARM-LABEL: func2:
|
||||
; CHECK-ARM: @ %bb.0:
|
||||
; CHECK-ARM-NEXT: .save {r11, lr}
|
||||
; CHECK-ARM-NEXT: push {r11, lr}
|
||||
; CHECK-ARM-NEXT: adds r0, r0, r2
|
||||
; CHECK-ARM-NEXT: mov r2, #0
|
||||
; CHECK-ARM-NEXT: adc r12, r1, r3
|
||||
; CHECK-ARM-NEXT: cmn r1, #1
|
||||
; CHECK-ARM-NEXT: mov r1, #0
|
||||
; CHECK-ARM-NEXT: mov lr, #0
|
||||
; CHECK-ARM-NEXT: movwgt r1, #1
|
||||
; CHECK-ARM-NEXT: cmn r12, #1
|
||||
; CHECK-ARM-NEXT: movwgt r2, #1
|
||||
; CHECK-ARM-NEXT: subs r2, r1, r2
|
||||
; CHECK-ARM-NEXT: movwne r2, #1
|
||||
; CHECK-ARM-NEXT: cmn r3, #1
|
||||
; CHECK-ARM-NEXT: movwgt lr, #1
|
||||
; CHECK-ARM-NEXT: sub r1, r1, lr
|
||||
; CHECK-ARM-NEXT: clz r1, r1
|
||||
; CHECK-ARM-NEXT: lsr r1, r1, #5
|
||||
; CHECK-ARM-NEXT: ands r2, r1, r2
|
||||
; CHECK-ARM-NEXT: asrne r0, r12, #31
|
||||
; CHECK-ARM-NEXT: mov r1, #-2147483648
|
||||
; CHECK-ARM-NEXT: cmp r12, #0
|
||||
; CHECK-ARM-NEXT: mvnmi r1, #-2147483648
|
||||
; CHECK-ARM-NEXT: cmp r2, #0
|
||||
; CHECK-ARM-NEXT: moveq r1, r12
|
||||
; CHECK-ARM-NEXT: pop {r11, pc}
|
||||
%tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %y)
|
||||
ret i64 %tmp
|
||||
}
|
||||
|
||||
define i16 @func16(i16 %x, i16 %y) nounwind {
|
||||
; CHECK-T1-LABEL: func16:
|
||||
; CHECK-T1: @ %bb.0:
|
||||
; CHECK-T1-NEXT: lsls r3, r1, #16
|
||||
; CHECK-T1-NEXT: lsls r1, r0, #16
|
||||
; CHECK-T1-NEXT: movs r2, #1
|
||||
; CHECK-T1-NEXT: adds r0, r1, r3
|
||||
; CHECK-T1-NEXT: mov r3, r2
|
||||
; CHECK-T1-NEXT: bmi .LBB2_2
|
||||
; CHECK-T1-NEXT: @ %bb.1:
|
||||
; CHECK-T1-NEXT: movs r3, #0
|
||||
; CHECK-T1-NEXT: .LBB2_2:
|
||||
; CHECK-T1-NEXT: cmp r3, #0
|
||||
; CHECK-T1-NEXT: bne .LBB2_4
|
||||
; CHECK-T1-NEXT: @ %bb.3:
|
||||
; CHECK-T1-NEXT: lsls r2, r2, #31
|
||||
; CHECK-T1-NEXT: cmp r0, r1
|
||||
; CHECK-T1-NEXT: bvs .LBB2_5
|
||||
; CHECK-T1-NEXT: b .LBB2_6
|
||||
; CHECK-T1-NEXT: .LBB2_4:
|
||||
; CHECK-T1-NEXT: ldr r2, .LCPI2_0
|
||||
; CHECK-T1-NEXT: cmp r0, r1
|
||||
; CHECK-T1-NEXT: bvc .LBB2_6
|
||||
; CHECK-T1-NEXT: .LBB2_5:
|
||||
; CHECK-T1-NEXT: mov r0, r2
|
||||
; CHECK-T1-NEXT: .LBB2_6:
|
||||
; CHECK-T1-NEXT: asrs r0, r0, #16
|
||||
; CHECK-T1-NEXT: bx lr
|
||||
; CHECK-T1-NEXT: .p2align 2
|
||||
; CHECK-T1-NEXT: @ %bb.7:
|
||||
; CHECK-T1-NEXT: .LCPI2_0:
|
||||
; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
|
||||
;
|
||||
; CHECK-T2-LABEL: func16:
|
||||
; CHECK-T2: @ %bb.0:
|
||||
; CHECK-T2-NEXT: lsls r2, r0, #16
|
||||
; CHECK-T2-NEXT: add.w r1, r2, r1, lsl #16
|
||||
; CHECK-T2-NEXT: movs r2, #0
|
||||
; CHECK-T2-NEXT: cmp r1, #0
|
||||
; CHECK-T2-NEXT: mov.w r3, #-2147483648
|
||||
; CHECK-T2-NEXT: it mi
|
||||
; CHECK-T2-NEXT: movmi r2, #1
|
||||
; CHECK-T2-NEXT: cmp r2, #0
|
||||
; CHECK-T2-NEXT: it ne
|
||||
; CHECK-T2-NEXT: mvnne r3, #-2147483648
|
||||
; CHECK-T2-NEXT: cmp.w r1, r0, lsl #16
|
||||
; CHECK-T2-NEXT: it vc
|
||||
; CHECK-T2-NEXT: movvc r3, r1
|
||||
; CHECK-T2-NEXT: asrs r0, r3, #16
|
||||
; CHECK-T2-NEXT: bx lr
|
||||
;
|
||||
; CHECK-ARM-LABEL: func16:
|
||||
; CHECK-ARM: @ %bb.0:
|
||||
; CHECK-ARM-NEXT: lsl r2, r0, #16
|
||||
; CHECK-ARM-NEXT: add r1, r2, r1, lsl #16
|
||||
; CHECK-ARM-NEXT: mov r2, #0
|
||||
; CHECK-ARM-NEXT: cmp r1, #0
|
||||
; CHECK-ARM-NEXT: movwmi r2, #1
|
||||
; CHECK-ARM-NEXT: mov r3, #-2147483648
|
||||
; CHECK-ARM-NEXT: cmp r2, #0
|
||||
; CHECK-ARM-NEXT: mvnne r3, #-2147483648
|
||||
; CHECK-ARM-NEXT: cmp r1, r0, lsl #16
|
||||
; CHECK-ARM-NEXT: movvc r3, r1
|
||||
; CHECK-ARM-NEXT: asr r0, r3, #16
|
||||
; CHECK-ARM-NEXT: bx lr
|
||||
%tmp = call i16 @llvm.sadd.sat.i16(i16 %x, i16 %y)
|
||||
ret i16 %tmp
|
||||
}
|
||||
|
||||
define i8 @func8(i8 %x, i8 %y) nounwind {
|
||||
; CHECK-T1-LABEL: func8:
|
||||
; CHECK-T1: @ %bb.0:
|
||||
; CHECK-T1-NEXT: lsls r3, r1, #24
|
||||
; CHECK-T1-NEXT: lsls r1, r0, #24
|
||||
; CHECK-T1-NEXT: movs r2, #1
|
||||
; CHECK-T1-NEXT: adds r0, r1, r3
|
||||
; CHECK-T1-NEXT: mov r3, r2
|
||||
; CHECK-T1-NEXT: bmi .LBB3_2
|
||||
; CHECK-T1-NEXT: @ %bb.1:
|
||||
; CHECK-T1-NEXT: movs r3, #0
|
||||
; CHECK-T1-NEXT: .LBB3_2:
|
||||
; CHECK-T1-NEXT: cmp r3, #0
|
||||
; CHECK-T1-NEXT: bne .LBB3_4
|
||||
; CHECK-T1-NEXT: @ %bb.3:
|
||||
; CHECK-T1-NEXT: lsls r2, r2, #31
|
||||
; CHECK-T1-NEXT: cmp r0, r1
|
||||
; CHECK-T1-NEXT: bvs .LBB3_5
|
||||
; CHECK-T1-NEXT: b .LBB3_6
|
||||
; CHECK-T1-NEXT: .LBB3_4:
|
||||
; CHECK-T1-NEXT: ldr r2, .LCPI3_0
|
||||
; CHECK-T1-NEXT: cmp r0, r1
|
||||
; CHECK-T1-NEXT: bvc .LBB3_6
|
||||
; CHECK-T1-NEXT: .LBB3_5:
|
||||
; CHECK-T1-NEXT: mov r0, r2
|
||||
; CHECK-T1-NEXT: .LBB3_6:
|
||||
; CHECK-T1-NEXT: asrs r0, r0, #24
|
||||
; CHECK-T1-NEXT: bx lr
|
||||
; CHECK-T1-NEXT: .p2align 2
|
||||
; CHECK-T1-NEXT: @ %bb.7:
|
||||
; CHECK-T1-NEXT: .LCPI3_0:
|
||||
; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
|
||||
;
|
||||
; CHECK-T2-LABEL: func8:
|
||||
; CHECK-T2: @ %bb.0:
|
||||
; CHECK-T2-NEXT: lsls r2, r0, #24
|
||||
; CHECK-T2-NEXT: add.w r1, r2, r1, lsl #24
|
||||
; CHECK-T2-NEXT: movs r2, #0
|
||||
; CHECK-T2-NEXT: cmp r1, #0
|
||||
; CHECK-T2-NEXT: mov.w r3, #-2147483648
|
||||
; CHECK-T2-NEXT: it mi
|
||||
; CHECK-T2-NEXT: movmi r2, #1
|
||||
; CHECK-T2-NEXT: cmp r2, #0
|
||||
; CHECK-T2-NEXT: it ne
|
||||
; CHECK-T2-NEXT: mvnne r3, #-2147483648
|
||||
; CHECK-T2-NEXT: cmp.w r1, r0, lsl #24
|
||||
; CHECK-T2-NEXT: it vc
|
||||
; CHECK-T2-NEXT: movvc r3, r1
|
||||
; CHECK-T2-NEXT: asrs r0, r3, #24
|
||||
; CHECK-T2-NEXT: bx lr
|
||||
;
|
||||
; CHECK-ARM-LABEL: func8:
|
||||
; CHECK-ARM: @ %bb.0:
|
||||
; CHECK-ARM-NEXT: lsl r2, r0, #24
|
||||
; CHECK-ARM-NEXT: add r1, r2, r1, lsl #24
|
||||
; CHECK-ARM-NEXT: mov r2, #0
|
||||
; CHECK-ARM-NEXT: cmp r1, #0
|
||||
; CHECK-ARM-NEXT: movwmi r2, #1
|
||||
; CHECK-ARM-NEXT: mov r3, #-2147483648
|
||||
; CHECK-ARM-NEXT: cmp r2, #0
|
||||
; CHECK-ARM-NEXT: mvnne r3, #-2147483648
|
||||
; CHECK-ARM-NEXT: cmp r1, r0, lsl #24
|
||||
; CHECK-ARM-NEXT: movvc r3, r1
|
||||
; CHECK-ARM-NEXT: asr r0, r3, #24
|
||||
; CHECK-ARM-NEXT: bx lr
|
||||
%tmp = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %y)
|
||||
ret i8 %tmp
|
||||
}
|
||||
|
||||
define i4 @func3(i4 %x, i4 %y) nounwind {
|
||||
; CHECK-T1-LABEL: func3:
|
||||
; CHECK-T1: @ %bb.0:
|
||||
; CHECK-T1-NEXT: lsls r3, r1, #28
|
||||
; CHECK-T1-NEXT: lsls r1, r0, #28
|
||||
; CHECK-T1-NEXT: movs r2, #1
|
||||
; CHECK-T1-NEXT: adds r0, r1, r3
|
||||
; CHECK-T1-NEXT: mov r3, r2
|
||||
; CHECK-T1-NEXT: bmi .LBB4_2
|
||||
; CHECK-T1-NEXT: @ %bb.1:
|
||||
; CHECK-T1-NEXT: movs r3, #0
|
||||
; CHECK-T1-NEXT: .LBB4_2:
|
||||
; CHECK-T1-NEXT: cmp r3, #0
|
||||
; CHECK-T1-NEXT: bne .LBB4_4
|
||||
; CHECK-T1-NEXT: @ %bb.3:
|
||||
; CHECK-T1-NEXT: lsls r2, r2, #31
|
||||
; CHECK-T1-NEXT: cmp r0, r1
|
||||
; CHECK-T1-NEXT: bvs .LBB4_5
|
||||
; CHECK-T1-NEXT: b .LBB4_6
|
||||
; CHECK-T1-NEXT: .LBB4_4:
|
||||
; CHECK-T1-NEXT: ldr r2, .LCPI4_0
|
||||
; CHECK-T1-NEXT: cmp r0, r1
|
||||
; CHECK-T1-NEXT: bvc .LBB4_6
|
||||
; CHECK-T1-NEXT: .LBB4_5:
|
||||
; CHECK-T1-NEXT: mov r0, r2
|
||||
; CHECK-T1-NEXT: .LBB4_6:
|
||||
; CHECK-T1-NEXT: asrs r0, r0, #28
|
||||
; CHECK-T1-NEXT: bx lr
|
||||
; CHECK-T1-NEXT: .p2align 2
|
||||
; CHECK-T1-NEXT: @ %bb.7:
|
||||
; CHECK-T1-NEXT: .LCPI4_0:
|
||||
; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
|
||||
;
|
||||
; CHECK-T2-LABEL: func3:
|
||||
; CHECK-T2: @ %bb.0:
|
||||
; CHECK-T2-NEXT: lsls r2, r0, #28
|
||||
; CHECK-T2-NEXT: add.w r1, r2, r1, lsl #28
|
||||
; CHECK-T2-NEXT: movs r2, #0
|
||||
; CHECK-T2-NEXT: cmp r1, #0
|
||||
; CHECK-T2-NEXT: mov.w r3, #-2147483648
|
||||
; CHECK-T2-NEXT: it mi
|
||||
; CHECK-T2-NEXT: movmi r2, #1
|
||||
; CHECK-T2-NEXT: cmp r2, #0
|
||||
; CHECK-T2-NEXT: it ne
|
||||
; CHECK-T2-NEXT: mvnne r3, #-2147483648
|
||||
; CHECK-T2-NEXT: cmp.w r1, r0, lsl #28
|
||||
; CHECK-T2-NEXT: it vc
|
||||
; CHECK-T2-NEXT: movvc r3, r1
|
||||
; CHECK-T2-NEXT: asrs r0, r3, #28
|
||||
; CHECK-T2-NEXT: bx lr
|
||||
;
|
||||
; CHECK-ARM-LABEL: func3:
|
||||
; CHECK-ARM: @ %bb.0:
|
||||
; CHECK-ARM-NEXT: lsl r2, r0, #28
|
||||
; CHECK-ARM-NEXT: add r1, r2, r1, lsl #28
|
||||
; CHECK-ARM-NEXT: mov r2, #0
|
||||
; CHECK-ARM-NEXT: cmp r1, #0
|
||||
; CHECK-ARM-NEXT: movwmi r2, #1
|
||||
; CHECK-ARM-NEXT: mov r3, #-2147483648
|
||||
; CHECK-ARM-NEXT: cmp r2, #0
|
||||
; CHECK-ARM-NEXT: mvnne r3, #-2147483648
|
||||
; CHECK-ARM-NEXT: cmp r1, r0, lsl #28
|
||||
; CHECK-ARM-NEXT: movvc r3, r1
|
||||
; CHECK-ARM-NEXT: asr r0, r3, #28
|
||||
; CHECK-ARM-NEXT: bx lr
|
||||
%tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %y)
|
||||
ret i4 %tmp
|
||||
}
|
||||
608
test/CodeGen/ARM/ssub_sat.ll
Normal file
608
test/CodeGen/ARM/ssub_sat.ll
Normal file
@ -0,0 +1,608 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=CHECK-T1
|
||||
; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2NODSP
|
||||
; RUN: llc < %s -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2DSP
|
||||
; RUN: llc < %s -mtriple=armv8a-none-eabi | FileCheck %s --check-prefix=CHECK-ARM
|
||||
|
||||
declare i4 @llvm.ssub.sat.i4(i4, i4)
|
||||
declare i8 @llvm.ssub.sat.i8(i8, i8)
|
||||
declare i16 @llvm.ssub.sat.i16(i16, i16)
|
||||
declare i32 @llvm.ssub.sat.i32(i32, i32)
|
||||
declare i64 @llvm.ssub.sat.i64(i64, i64)
|
||||
declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32>, <4 x i32>)
|
||||
|
||||
define i32 @func(i32 %x, i32 %y) nounwind {
|
||||
; CHECK-T1-LABEL: func:
|
||||
; CHECK-T1: @ %bb.0:
|
||||
; CHECK-T1-NEXT: .save {r4, lr}
|
||||
; CHECK-T1-NEXT: push {r4, lr}
|
||||
; CHECK-T1-NEXT: mov r2, r0
|
||||
; CHECK-T1-NEXT: movs r3, #1
|
||||
; CHECK-T1-NEXT: subs r0, r0, r1
|
||||
; CHECK-T1-NEXT: mov r4, r3
|
||||
; CHECK-T1-NEXT: bmi .LBB0_2
|
||||
; CHECK-T1-NEXT: @ %bb.1:
|
||||
; CHECK-T1-NEXT: movs r4, #0
|
||||
; CHECK-T1-NEXT: .LBB0_2:
|
||||
; CHECK-T1-NEXT: cmp r4, #0
|
||||
; CHECK-T1-NEXT: bne .LBB0_4
|
||||
; CHECK-T1-NEXT: @ %bb.3:
|
||||
; CHECK-T1-NEXT: lsls r3, r3, #31
|
||||
; CHECK-T1-NEXT: cmp r2, r1
|
||||
; CHECK-T1-NEXT: bvs .LBB0_5
|
||||
; CHECK-T1-NEXT: b .LBB0_6
|
||||
; CHECK-T1-NEXT: .LBB0_4:
|
||||
; CHECK-T1-NEXT: ldr r3, .LCPI0_0
|
||||
; CHECK-T1-NEXT: cmp r2, r1
|
||||
; CHECK-T1-NEXT: bvc .LBB0_6
|
||||
; CHECK-T1-NEXT: .LBB0_5:
|
||||
; CHECK-T1-NEXT: mov r0, r3
|
||||
; CHECK-T1-NEXT: .LBB0_6:
|
||||
; CHECK-T1-NEXT: pop {r4, pc}
|
||||
; CHECK-T1-NEXT: .p2align 2
|
||||
; CHECK-T1-NEXT: @ %bb.7:
|
||||
; CHECK-T1-NEXT: .LCPI0_0:
|
||||
; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
|
||||
;
|
||||
; CHECK-T2-LABEL: func:
|
||||
; CHECK-T2: @ %bb.0:
|
||||
; CHECK-T2-NEXT: subs.w r12, r0, r1
|
||||
; CHECK-T2-NEXT: mov.w r3, #0
|
||||
; CHECK-T2-NEXT: mov.w r2, #-2147483648
|
||||
; CHECK-T2-NEXT: it mi
|
||||
; CHECK-T2-NEXT: movmi r3, #1
|
||||
; CHECK-T2-NEXT: cmp r3, #0
|
||||
; CHECK-T2-NEXT: it ne
|
||||
; CHECK-T2-NEXT: mvnne r2, #-2147483648
|
||||
; CHECK-T2-NEXT: cmp r0, r1
|
||||
; CHECK-T2-NEXT: it vc
|
||||
; CHECK-T2-NEXT: movvc r2, r12
|
||||
; CHECK-T2-NEXT: mov r0, r2
|
||||
; CHECK-T2-NEXT: bx lr
|
||||
;
|
||||
; CHECK-ARM-LABEL: func:
|
||||
; CHECK-ARM: @ %bb.0:
|
||||
; CHECK-ARM-NEXT: subs r12, r0, r1
|
||||
; CHECK-ARM-NEXT: mov r3, #0
|
||||
; CHECK-ARM-NEXT: movwmi r3, #1
|
||||
; CHECK-ARM-NEXT: mov r2, #-2147483648
|
||||
; CHECK-ARM-NEXT: cmp r3, #0
|
||||
; CHECK-ARM-NEXT: mvnne r2, #-2147483648
|
||||
; CHECK-ARM-NEXT: cmp r0, r1
|
||||
; CHECK-ARM-NEXT: movvc r2, r12
|
||||
; CHECK-ARM-NEXT: mov r0, r2
|
||||
; CHECK-ARM-NEXT: bx lr
|
||||
%tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %y)
|
||||
ret i32 %tmp
|
||||
}
|
||||
|
||||
define i64 @func2(i64 %x, i64 %y) nounwind {
|
||||
; CHECK-T1-LABEL: func2:
|
||||
; CHECK-T1: @ %bb.0:
|
||||
; CHECK-T1-NEXT: .save {r4, r5, r6, r7, lr}
|
||||
; CHECK-T1-NEXT: push {r4, r5, r6, r7, lr}
|
||||
; CHECK-T1-NEXT: .pad #4
|
||||
; CHECK-T1-NEXT: sub sp, #4
|
||||
; CHECK-T1-NEXT: str r2, [sp] @ 4-byte Spill
|
||||
; CHECK-T1-NEXT: mov r2, r0
|
||||
; CHECK-T1-NEXT: movs r4, #1
|
||||
; CHECK-T1-NEXT: movs r0, #0
|
||||
; CHECK-T1-NEXT: cmp r3, #0
|
||||
; CHECK-T1-NEXT: mov r5, r4
|
||||
; CHECK-T1-NEXT: bge .LBB1_2
|
||||
; CHECK-T1-NEXT: @ %bb.1:
|
||||
; CHECK-T1-NEXT: mov r5, r0
|
||||
; CHECK-T1-NEXT: .LBB1_2:
|
||||
; CHECK-T1-NEXT: cmp r1, #0
|
||||
; CHECK-T1-NEXT: mov r7, r4
|
||||
; CHECK-T1-NEXT: bge .LBB1_4
|
||||
; CHECK-T1-NEXT: @ %bb.3:
|
||||
; CHECK-T1-NEXT: mov r7, r0
|
||||
; CHECK-T1-NEXT: .LBB1_4:
|
||||
; CHECK-T1-NEXT: subs r5, r7, r5
|
||||
; CHECK-T1-NEXT: subs r6, r5, #1
|
||||
; CHECK-T1-NEXT: sbcs r5, r6
|
||||
; CHECK-T1-NEXT: ldr r6, [sp] @ 4-byte Reload
|
||||
; CHECK-T1-NEXT: subs r6, r2, r6
|
||||
; CHECK-T1-NEXT: sbcs r1, r3
|
||||
; CHECK-T1-NEXT: cmp r1, #0
|
||||
; CHECK-T1-NEXT: mov r2, r4
|
||||
; CHECK-T1-NEXT: bge .LBB1_6
|
||||
; CHECK-T1-NEXT: @ %bb.5:
|
||||
; CHECK-T1-NEXT: mov r2, r0
|
||||
; CHECK-T1-NEXT: .LBB1_6:
|
||||
; CHECK-T1-NEXT: subs r0, r7, r2
|
||||
; CHECK-T1-NEXT: subs r2, r0, #1
|
||||
; CHECK-T1-NEXT: sbcs r0, r2
|
||||
; CHECK-T1-NEXT: ands r5, r0
|
||||
; CHECK-T1-NEXT: beq .LBB1_8
|
||||
; CHECK-T1-NEXT: @ %bb.7:
|
||||
; CHECK-T1-NEXT: asrs r6, r1, #31
|
||||
; CHECK-T1-NEXT: .LBB1_8:
|
||||
; CHECK-T1-NEXT: cmp r1, #0
|
||||
; CHECK-T1-NEXT: bmi .LBB1_10
|
||||
; CHECK-T1-NEXT: @ %bb.9:
|
||||
; CHECK-T1-NEXT: lsls r2, r4, #31
|
||||
; CHECK-T1-NEXT: cmp r5, #0
|
||||
; CHECK-T1-NEXT: beq .LBB1_11
|
||||
; CHECK-T1-NEXT: b .LBB1_12
|
||||
; CHECK-T1-NEXT: .LBB1_10:
|
||||
; CHECK-T1-NEXT: ldr r2, .LCPI1_0
|
||||
; CHECK-T1-NEXT: cmp r5, #0
|
||||
; CHECK-T1-NEXT: bne .LBB1_12
|
||||
; CHECK-T1-NEXT: .LBB1_11:
|
||||
; CHECK-T1-NEXT: mov r2, r1
|
||||
; CHECK-T1-NEXT: .LBB1_12:
|
||||
; CHECK-T1-NEXT: mov r0, r6
|
||||
; CHECK-T1-NEXT: mov r1, r2
|
||||
; CHECK-T1-NEXT: add sp, #4
|
||||
; CHECK-T1-NEXT: pop {r4, r5, r6, r7, pc}
|
||||
; CHECK-T1-NEXT: .p2align 2
|
||||
; CHECK-T1-NEXT: @ %bb.13:
|
||||
; CHECK-T1-NEXT: .LCPI1_0:
|
||||
; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
|
||||
;
|
||||
; CHECK-T2-LABEL: func2:
|
||||
; CHECK-T2: @ %bb.0:
|
||||
; CHECK-T2-NEXT: .save {r4, lr}
|
||||
; CHECK-T2-NEXT: push {r4, lr}
|
||||
; CHECK-T2-NEXT: cmp.w r3, #-1
|
||||
; CHECK-T2-NEXT: mov.w lr, #0
|
||||
; CHECK-T2-NEXT: it gt
|
||||
; CHECK-T2-NEXT: movgt.w lr, #1
|
||||
; CHECK-T2-NEXT: cmp.w r1, #-1
|
||||
; CHECK-T2-NEXT: mov.w r4, #0
|
||||
; CHECK-T2-NEXT: mov.w r12, #0
|
||||
; CHECK-T2-NEXT: it gt
|
||||
; CHECK-T2-NEXT: movgt r4, #1
|
||||
; CHECK-T2-NEXT: subs.w lr, r4, lr
|
||||
; CHECK-T2-NEXT: it ne
|
||||
; CHECK-T2-NEXT: movne.w lr, #1
|
||||
; CHECK-T2-NEXT: subs r0, r0, r2
|
||||
; CHECK-T2-NEXT: sbc.w r2, r1, r3
|
||||
; CHECK-T2-NEXT: cmp.w r2, #-1
|
||||
; CHECK-T2-NEXT: it gt
|
||||
; CHECK-T2-NEXT: movgt.w r12, #1
|
||||
; CHECK-T2-NEXT: subs.w r1, r4, r12
|
||||
; CHECK-T2-NEXT: it ne
|
||||
; CHECK-T2-NEXT: movne r1, #1
|
||||
; CHECK-T2-NEXT: ands.w r3, lr, r1
|
||||
; CHECK-T2-NEXT: mov.w r1, #-2147483648
|
||||
; CHECK-T2-NEXT: it ne
|
||||
; CHECK-T2-NEXT: asrne r0, r2, #31
|
||||
; CHECK-T2-NEXT: cmp r2, #0
|
||||
; CHECK-T2-NEXT: it mi
|
||||
; CHECK-T2-NEXT: mvnmi r1, #-2147483648
|
||||
; CHECK-T2-NEXT: cmp r3, #0
|
||||
; CHECK-T2-NEXT: it eq
|
||||
; CHECK-T2-NEXT: moveq r1, r2
|
||||
; CHECK-T2-NEXT: pop {r4, pc}
|
||||
;
|
||||
; CHECK-ARM-LABEL: func2:
|
||||
; CHECK-ARM: @ %bb.0:
|
||||
; CHECK-ARM-NEXT: .save {r4, lr}
|
||||
; CHECK-ARM-NEXT: push {r4, lr}
|
||||
; CHECK-ARM-NEXT: cmn r3, #1
|
||||
; CHECK-ARM-NEXT: mov lr, #0
|
||||
; CHECK-ARM-NEXT: movwgt lr, #1
|
||||
; CHECK-ARM-NEXT: cmn r1, #1
|
||||
; CHECK-ARM-NEXT: mov r4, #0
|
||||
; CHECK-ARM-NEXT: mov r12, #0
|
||||
; CHECK-ARM-NEXT: movwgt r4, #1
|
||||
; CHECK-ARM-NEXT: subs lr, r4, lr
|
||||
; CHECK-ARM-NEXT: movwne lr, #1
|
||||
; CHECK-ARM-NEXT: subs r0, r0, r2
|
||||
; CHECK-ARM-NEXT: sbc r2, r1, r3
|
||||
; CHECK-ARM-NEXT: cmn r2, #1
|
||||
; CHECK-ARM-NEXT: movwgt r12, #1
|
||||
; CHECK-ARM-NEXT: subs r1, r4, r12
|
||||
; CHECK-ARM-NEXT: movwne r1, #1
|
||||
; CHECK-ARM-NEXT: ands r3, lr, r1
|
||||
; CHECK-ARM-NEXT: asrne r0, r2, #31
|
||||
; CHECK-ARM-NEXT: mov r1, #-2147483648
|
||||
; CHECK-ARM-NEXT: cmp r2, #0
|
||||
; CHECK-ARM-NEXT: mvnmi r1, #-2147483648
|
||||
; CHECK-ARM-NEXT: cmp r3, #0
|
||||
; CHECK-ARM-NEXT: moveq r1, r2
|
||||
; CHECK-ARM-NEXT: pop {r4, pc}
|
||||
%tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %y)
|
||||
ret i64 %tmp
|
||||
}
|
||||
|
||||
define i16 @func16(i16 %x, i16 %y) nounwind {
|
||||
; CHECK-T1-LABEL: func16:
|
||||
; CHECK-T1: @ %bb.0:
|
||||
; CHECK-T1-NEXT: .save {r4, lr}
|
||||
; CHECK-T1-NEXT: push {r4, lr}
|
||||
; CHECK-T1-NEXT: lsls r1, r1, #16
|
||||
; CHECK-T1-NEXT: lsls r2, r0, #16
|
||||
; CHECK-T1-NEXT: movs r3, #1
|
||||
; CHECK-T1-NEXT: subs r0, r2, r1
|
||||
; CHECK-T1-NEXT: mov r4, r3
|
||||
; CHECK-T1-NEXT: bmi .LBB2_2
|
||||
; CHECK-T1-NEXT: @ %bb.1:
|
||||
; CHECK-T1-NEXT: movs r4, #0
|
||||
; CHECK-T1-NEXT: .LBB2_2:
|
||||
; CHECK-T1-NEXT: cmp r4, #0
|
||||
; CHECK-T1-NEXT: bne .LBB2_4
|
||||
; CHECK-T1-NEXT: @ %bb.3:
|
||||
; CHECK-T1-NEXT: lsls r3, r3, #31
|
||||
; CHECK-T1-NEXT: cmp r2, r1
|
||||
; CHECK-T1-NEXT: bvs .LBB2_5
|
||||
; CHECK-T1-NEXT: b .LBB2_6
|
||||
; CHECK-T1-NEXT: .LBB2_4:
|
||||
; CHECK-T1-NEXT: ldr r3, .LCPI2_0
|
||||
; CHECK-T1-NEXT: cmp r2, r1
|
||||
; CHECK-T1-NEXT: bvc .LBB2_6
|
||||
; CHECK-T1-NEXT: .LBB2_5:
|
||||
; CHECK-T1-NEXT: mov r0, r3
|
||||
; CHECK-T1-NEXT: .LBB2_6:
|
||||
; CHECK-T1-NEXT: asrs r0, r0, #16
|
||||
; CHECK-T1-NEXT: pop {r4, pc}
|
||||
; CHECK-T1-NEXT: .p2align 2
|
||||
; CHECK-T1-NEXT: @ %bb.7:
|
||||
; CHECK-T1-NEXT: .LCPI2_0:
|
||||
; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
|
||||
;
|
||||
; CHECK-T2-LABEL: func16:
|
||||
; CHECK-T2: @ %bb.0:
|
||||
; CHECK-T2-NEXT: lsls r0, r0, #16
|
||||
; CHECK-T2-NEXT: sub.w r12, r0, r1, lsl #16
|
||||
; CHECK-T2-NEXT: movs r3, #0
|
||||
; CHECK-T2-NEXT: cmp.w r12, #0
|
||||
; CHECK-T2-NEXT: mov.w r2, #-2147483648
|
||||
; CHECK-T2-NEXT: it mi
|
||||
; CHECK-T2-NEXT: movmi r3, #1
|
||||
; CHECK-T2-NEXT: cmp r3, #0
|
||||
; CHECK-T2-NEXT: it ne
|
||||
; CHECK-T2-NEXT: mvnne r2, #-2147483648
|
||||
; CHECK-T2-NEXT: cmp.w r0, r1, lsl #16
|
||||
; CHECK-T2-NEXT: it vc
|
||||
; CHECK-T2-NEXT: movvc r2, r12
|
||||
; CHECK-T2-NEXT: asrs r0, r2, #16
|
||||
; CHECK-T2-NEXT: bx lr
|
||||
;
|
||||
; CHECK-ARM-LABEL: func16:
|
||||
; CHECK-ARM: @ %bb.0:
|
||||
; CHECK-ARM-NEXT: lsl r0, r0, #16
|
||||
; CHECK-ARM-NEXT: sub r12, r0, r1, lsl #16
|
||||
; CHECK-ARM-NEXT: mov r3, #0
|
||||
; CHECK-ARM-NEXT: cmp r12, #0
|
||||
; CHECK-ARM-NEXT: movwmi r3, #1
|
||||
; CHECK-ARM-NEXT: mov r2, #-2147483648
|
||||
; CHECK-ARM-NEXT: cmp r3, #0
|
||||
; CHECK-ARM-NEXT: mvnne r2, #-2147483648
|
||||
; CHECK-ARM-NEXT: cmp r0, r1, lsl #16
|
||||
; CHECK-ARM-NEXT: movvc r2, r12
|
||||
; CHECK-ARM-NEXT: asr r0, r2, #16
|
||||
; CHECK-ARM-NEXT: bx lr
|
||||
%tmp = call i16 @llvm.ssub.sat.i16(i16 %x, i16 %y)
|
||||
ret i16 %tmp
|
||||
}
|
||||
|
||||
define i8 @func8(i8 %x, i8 %y) nounwind {
|
||||
; CHECK-T1-LABEL: func8:
|
||||
; CHECK-T1: @ %bb.0:
|
||||
; CHECK-T1-NEXT: .save {r4, lr}
|
||||
; CHECK-T1-NEXT: push {r4, lr}
|
||||
; CHECK-T1-NEXT: lsls r1, r1, #24
|
||||
; CHECK-T1-NEXT: lsls r2, r0, #24
|
||||
; CHECK-T1-NEXT: movs r3, #1
|
||||
; CHECK-T1-NEXT: subs r0, r2, r1
|
||||
; CHECK-T1-NEXT: mov r4, r3
|
||||
; CHECK-T1-NEXT: bmi .LBB3_2
|
||||
; CHECK-T1-NEXT: @ %bb.1:
|
||||
; CHECK-T1-NEXT: movs r4, #0
|
||||
; CHECK-T1-NEXT: .LBB3_2:
|
||||
; CHECK-T1-NEXT: cmp r4, #0
|
||||
; CHECK-T1-NEXT: bne .LBB3_4
|
||||
; CHECK-T1-NEXT: @ %bb.3:
|
||||
; CHECK-T1-NEXT: lsls r3, r3, #31
|
||||
; CHECK-T1-NEXT: cmp r2, r1
|
||||
; CHECK-T1-NEXT: bvs .LBB3_5
|
||||
; CHECK-T1-NEXT: b .LBB3_6
|
||||
; CHECK-T1-NEXT: .LBB3_4:
|
||||
; CHECK-T1-NEXT: ldr r3, .LCPI3_0
|
||||
; CHECK-T1-NEXT: cmp r2, r1
|
||||
; CHECK-T1-NEXT: bvc .LBB3_6
|
||||
; CHECK-T1-NEXT: .LBB3_5:
|
||||
; CHECK-T1-NEXT: mov r0, r3
|
||||
; CHECK-T1-NEXT: .LBB3_6:
|
||||
; CHECK-T1-NEXT: asrs r0, r0, #24
|
||||
; CHECK-T1-NEXT: pop {r4, pc}
|
||||
; CHECK-T1-NEXT: .p2align 2
|
||||
; CHECK-T1-NEXT: @ %bb.7:
|
||||
; CHECK-T1-NEXT: .LCPI3_0:
|
||||
; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
|
||||
;
|
||||
; CHECK-T2-LABEL: func8:
|
||||
; CHECK-T2: @ %bb.0:
|
||||
; CHECK-T2-NEXT: lsls r0, r0, #24
|
||||
; CHECK-T2-NEXT: sub.w r12, r0, r1, lsl #24
|
||||
; CHECK-T2-NEXT: movs r3, #0
|
||||
; CHECK-T2-NEXT: cmp.w r12, #0
|
||||
; CHECK-T2-NEXT: mov.w r2, #-2147483648
|
||||
; CHECK-T2-NEXT: it mi
|
||||
; CHECK-T2-NEXT: movmi r3, #1
|
||||
; CHECK-T2-NEXT: cmp r3, #0
|
||||
; CHECK-T2-NEXT: it ne
|
||||
; CHECK-T2-NEXT: mvnne r2, #-2147483648
|
||||
; CHECK-T2-NEXT: cmp.w r0, r1, lsl #24
|
||||
; CHECK-T2-NEXT: it vc
|
||||
; CHECK-T2-NEXT: movvc r2, r12
|
||||
; CHECK-T2-NEXT: asrs r0, r2, #24
|
||||
; CHECK-T2-NEXT: bx lr
|
||||
;
|
||||
; CHECK-ARM-LABEL: func8:
|
||||
; CHECK-ARM: @ %bb.0:
|
||||
; CHECK-ARM-NEXT: lsl r0, r0, #24
|
||||
; CHECK-ARM-NEXT: sub r12, r0, r1, lsl #24
|
||||
; CHECK-ARM-NEXT: mov r3, #0
|
||||
; CHECK-ARM-NEXT: cmp r12, #0
|
||||
; CHECK-ARM-NEXT: movwmi r3, #1
|
||||
; CHECK-ARM-NEXT: mov r2, #-2147483648
|
||||
; CHECK-ARM-NEXT: cmp r3, #0
|
||||
; CHECK-ARM-NEXT: mvnne r2, #-2147483648
|
||||
; CHECK-ARM-NEXT: cmp r0, r1, lsl #24
|
||||
; CHECK-ARM-NEXT: movvc r2, r12
|
||||
; CHECK-ARM-NEXT: asr r0, r2, #24
|
||||
; CHECK-ARM-NEXT: bx lr
|
||||
%tmp = call i8 @llvm.ssub.sat.i8(i8 %x, i8 %y)
|
||||
ret i8 %tmp
|
||||
}
|
||||
|
||||
define i4 @func3(i4 %x, i4 %y) nounwind {
|
||||
; CHECK-T1-LABEL: func3:
|
||||
; CHECK-T1: @ %bb.0:
|
||||
; CHECK-T1-NEXT: .save {r4, lr}
|
||||
; CHECK-T1-NEXT: push {r4, lr}
|
||||
; CHECK-T1-NEXT: lsls r1, r1, #28
|
||||
; CHECK-T1-NEXT: lsls r2, r0, #28
|
||||
; CHECK-T1-NEXT: movs r3, #1
|
||||
; CHECK-T1-NEXT: subs r0, r2, r1
|
||||
; CHECK-T1-NEXT: mov r4, r3
|
||||
; CHECK-T1-NEXT: bmi .LBB4_2
|
||||
; CHECK-T1-NEXT: @ %bb.1:
|
||||
; CHECK-T1-NEXT: movs r4, #0
|
||||
; CHECK-T1-NEXT: .LBB4_2:
|
||||
; CHECK-T1-NEXT: cmp r4, #0
|
||||
; CHECK-T1-NEXT: bne .LBB4_4
|
||||
; CHECK-T1-NEXT: @ %bb.3:
|
||||
; CHECK-T1-NEXT: lsls r3, r3, #31
|
||||
; CHECK-T1-NEXT: cmp r2, r1
|
||||
; CHECK-T1-NEXT: bvs .LBB4_5
|
||||
; CHECK-T1-NEXT: b .LBB4_6
|
||||
; CHECK-T1-NEXT: .LBB4_4:
|
||||
; CHECK-T1-NEXT: ldr r3, .LCPI4_0
|
||||
; CHECK-T1-NEXT: cmp r2, r1
|
||||
; CHECK-T1-NEXT: bvc .LBB4_6
|
||||
; CHECK-T1-NEXT: .LBB4_5:
|
||||
; CHECK-T1-NEXT: mov r0, r3
|
||||
; CHECK-T1-NEXT: .LBB4_6:
|
||||
; CHECK-T1-NEXT: asrs r0, r0, #28
|
||||
; CHECK-T1-NEXT: pop {r4, pc}
|
||||
; CHECK-T1-NEXT: .p2align 2
|
||||
; CHECK-T1-NEXT: @ %bb.7:
|
||||
; CHECK-T1-NEXT: .LCPI4_0:
|
||||
; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
|
||||
;
|
||||
; CHECK-T2-LABEL: func3:
|
||||
; CHECK-T2: @ %bb.0:
|
||||
; CHECK-T2-NEXT: lsls r0, r0, #28
|
||||
; CHECK-T2-NEXT: sub.w r12, r0, r1, lsl #28
|
||||
; CHECK-T2-NEXT: movs r3, #0
|
||||
; CHECK-T2-NEXT: cmp.w r12, #0
|
||||
; CHECK-T2-NEXT: mov.w r2, #-2147483648
|
||||
; CHECK-T2-NEXT: it mi
|
||||
; CHECK-T2-NEXT: movmi r3, #1
|
||||
; CHECK-T2-NEXT: cmp r3, #0
|
||||
; CHECK-T2-NEXT: it ne
|
||||
; CHECK-T2-NEXT: mvnne r2, #-2147483648
|
||||
; CHECK-T2-NEXT: cmp.w r0, r1, lsl #28
|
||||
; CHECK-T2-NEXT: it vc
|
||||
; CHECK-T2-NEXT: movvc r2, r12
|
||||
; CHECK-T2-NEXT: asrs r0, r2, #28
|
||||
; CHECK-T2-NEXT: bx lr
|
||||
;
|
||||
; CHECK-ARM-LABEL: func3:
|
||||
; CHECK-ARM: @ %bb.0:
|
||||
; CHECK-ARM-NEXT: lsl r0, r0, #28
|
||||
; CHECK-ARM-NEXT: sub r12, r0, r1, lsl #28
|
||||
; CHECK-ARM-NEXT: mov r3, #0
|
||||
; CHECK-ARM-NEXT: cmp r12, #0
|
||||
; CHECK-ARM-NEXT: movwmi r3, #1
|
||||
; CHECK-ARM-NEXT: mov r2, #-2147483648
|
||||
; CHECK-ARM-NEXT: cmp r3, #0
|
||||
; CHECK-ARM-NEXT: mvnne r2, #-2147483648
|
||||
; CHECK-ARM-NEXT: cmp r0, r1, lsl #28
|
||||
; CHECK-ARM-NEXT: movvc r2, r12
|
||||
; CHECK-ARM-NEXT: asr r0, r2, #28
|
||||
; CHECK-ARM-NEXT: bx lr
|
||||
%tmp = call i4 @llvm.ssub.sat.i4(i4 %x, i4 %y)
|
||||
ret i4 %tmp
|
||||
}
|
||||
|
||||
define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind {
|
||||
; CHECK-T1-LABEL: vec:
|
||||
; CHECK-T1: @ %bb.0:
|
||||
; CHECK-T1-NEXT: .save {r4, r5, r6, r7, lr}
|
||||
; CHECK-T1-NEXT: push {r4, r5, r6, r7, lr}
|
||||
; CHECK-T1-NEXT: .pad #12
|
||||
; CHECK-T1-NEXT: sub sp, #12
|
||||
; CHECK-T1-NEXT: str r3, [sp] @ 4-byte Spill
|
||||
; CHECK-T1-NEXT: mov r4, r1
|
||||
; CHECK-T1-NEXT: mov r1, r0
|
||||
; CHECK-T1-NEXT: ldr r5, [sp, #32]
|
||||
; CHECK-T1-NEXT: movs r7, #1
|
||||
; CHECK-T1-NEXT: movs r0, #0
|
||||
; CHECK-T1-NEXT: str r0, [sp, #8] @ 4-byte Spill
|
||||
; CHECK-T1-NEXT: subs r0, r1, r5
|
||||
; CHECK-T1-NEXT: str r0, [sp, #4] @ 4-byte Spill
|
||||
; CHECK-T1-NEXT: mov r6, r7
|
||||
; CHECK-T1-NEXT: bmi .LBB5_2
|
||||
; CHECK-T1-NEXT: @ %bb.1:
|
||||
; CHECK-T1-NEXT: ldr r6, [sp, #8] @ 4-byte Reload
|
||||
; CHECK-T1-NEXT: .LBB5_2:
|
||||
; CHECK-T1-NEXT: lsls r3, r7, #31
|
||||
; CHECK-T1-NEXT: ldr r0, .LCPI5_0
|
||||
; CHECK-T1-NEXT: cmp r6, #0
|
||||
; CHECK-T1-NEXT: mov r6, r0
|
||||
; CHECK-T1-NEXT: bne .LBB5_4
|
||||
; CHECK-T1-NEXT: @ %bb.3:
|
||||
; CHECK-T1-NEXT: mov r6, r3
|
||||
; CHECK-T1-NEXT: .LBB5_4:
|
||||
; CHECK-T1-NEXT: cmp r1, r5
|
||||
; CHECK-T1-NEXT: bvc .LBB5_6
|
||||
; CHECK-T1-NEXT: @ %bb.5:
|
||||
; CHECK-T1-NEXT: str r6, [sp, #4] @ 4-byte Spill
|
||||
; CHECK-T1-NEXT: .LBB5_6:
|
||||
; CHECK-T1-NEXT: ldr r5, [sp, #36]
|
||||
; CHECK-T1-NEXT: subs r1, r4, r5
|
||||
; CHECK-T1-NEXT: mov r6, r7
|
||||
; CHECK-T1-NEXT: bmi .LBB5_8
|
||||
; CHECK-T1-NEXT: @ %bb.7:
|
||||
; CHECK-T1-NEXT: ldr r6, [sp, #8] @ 4-byte Reload
|
||||
; CHECK-T1-NEXT: .LBB5_8:
|
||||
; CHECK-T1-NEXT: cmp r6, #0
|
||||
; CHECK-T1-NEXT: mov r6, r0
|
||||
; CHECK-T1-NEXT: bne .LBB5_10
|
||||
; CHECK-T1-NEXT: @ %bb.9:
|
||||
; CHECK-T1-NEXT: mov r6, r3
|
||||
; CHECK-T1-NEXT: .LBB5_10:
|
||||
; CHECK-T1-NEXT: cmp r4, r5
|
||||
; CHECK-T1-NEXT: bvc .LBB5_12
|
||||
; CHECK-T1-NEXT: @ %bb.11:
|
||||
; CHECK-T1-NEXT: mov r1, r6
|
||||
; CHECK-T1-NEXT: .LBB5_12:
|
||||
; CHECK-T1-NEXT: ldr r5, [sp, #40]
|
||||
; CHECK-T1-NEXT: subs r4, r2, r5
|
||||
; CHECK-T1-NEXT: mov r6, r7
|
||||
; CHECK-T1-NEXT: bmi .LBB5_14
|
||||
; CHECK-T1-NEXT: @ %bb.13:
|
||||
; CHECK-T1-NEXT: ldr r6, [sp, #8] @ 4-byte Reload
|
||||
; CHECK-T1-NEXT: .LBB5_14:
|
||||
; CHECK-T1-NEXT: cmp r6, #0
|
||||
; CHECK-T1-NEXT: mov r6, r0
|
||||
; CHECK-T1-NEXT: bne .LBB5_16
|
||||
; CHECK-T1-NEXT: @ %bb.15:
|
||||
; CHECK-T1-NEXT: mov r6, r3
|
||||
; CHECK-T1-NEXT: .LBB5_16:
|
||||
; CHECK-T1-NEXT: cmp r2, r5
|
||||
; CHECK-T1-NEXT: bvc .LBB5_18
|
||||
; CHECK-T1-NEXT: @ %bb.17:
|
||||
; CHECK-T1-NEXT: mov r4, r6
|
||||
; CHECK-T1-NEXT: .LBB5_18:
|
||||
; CHECK-T1-NEXT: ldr r2, [sp, #44]
|
||||
; CHECK-T1-NEXT: ldr r6, [sp] @ 4-byte Reload
|
||||
; CHECK-T1-NEXT: subs r5, r6, r2
|
||||
; CHECK-T1-NEXT: bpl .LBB5_23
|
||||
; CHECK-T1-NEXT: @ %bb.19:
|
||||
; CHECK-T1-NEXT: cmp r7, #0
|
||||
; CHECK-T1-NEXT: beq .LBB5_24
|
||||
; CHECK-T1-NEXT: .LBB5_20:
|
||||
; CHECK-T1-NEXT: cmp r6, r2
|
||||
; CHECK-T1-NEXT: bvc .LBB5_22
|
||||
; CHECK-T1-NEXT: .LBB5_21:
|
||||
; CHECK-T1-NEXT: mov r5, r0
|
||||
; CHECK-T1-NEXT: .LBB5_22:
|
||||
; CHECK-T1-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
|
||||
; CHECK-T1-NEXT: mov r2, r4
|
||||
; CHECK-T1-NEXT: mov r3, r5
|
||||
; CHECK-T1-NEXT: add sp, #12
|
||||
; CHECK-T1-NEXT: pop {r4, r5, r6, r7, pc}
|
||||
; CHECK-T1-NEXT: .LBB5_23:
|
||||
; CHECK-T1-NEXT: ldr r7, [sp, #8] @ 4-byte Reload
|
||||
; CHECK-T1-NEXT: cmp r7, #0
|
||||
; CHECK-T1-NEXT: bne .LBB5_20
|
||||
; CHECK-T1-NEXT: .LBB5_24:
|
||||
; CHECK-T1-NEXT: mov r0, r3
|
||||
; CHECK-T1-NEXT: cmp r6, r2
|
||||
; CHECK-T1-NEXT: bvs .LBB5_21
|
||||
; CHECK-T1-NEXT: b .LBB5_22
|
||||
; CHECK-T1-NEXT: .p2align 2
|
||||
; CHECK-T1-NEXT: @ %bb.25:
|
||||
; CHECK-T1-NEXT: .LCPI5_0:
|
||||
; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
|
||||
;
|
||||
; CHECK-T2-LABEL: vec:
|
||||
; CHECK-T2: @ %bb.0:
|
||||
; CHECK-T2-NEXT: .save {r4, r5, r6, r7, lr}
|
||||
; CHECK-T2-NEXT: push {r4, r5, r6, r7, lr}
|
||||
; CHECK-T2-NEXT: .pad #4
|
||||
; CHECK-T2-NEXT: sub sp, #4
|
||||
; CHECK-T2-NEXT: ldr r4, [sp, #24]
|
||||
; CHECK-T2-NEXT: mov lr, r0
|
||||
; CHECK-T2-NEXT: ldr r7, [sp, #28]
|
||||
; CHECK-T2-NEXT: movs r5, #0
|
||||
; CHECK-T2-NEXT: subs r6, r0, r4
|
||||
; CHECK-T2-NEXT: mov.w r0, #0
|
||||
; CHECK-T2-NEXT: it mi
|
||||
; CHECK-T2-NEXT: movmi r0, #1
|
||||
; CHECK-T2-NEXT: cmp r0, #0
|
||||
; CHECK-T2-NEXT: mov.w r0, #-2147483648
|
||||
; CHECK-T2-NEXT: mov.w r12, #-2147483648
|
||||
; CHECK-T2-NEXT: it ne
|
||||
; CHECK-T2-NEXT: mvnne r0, #-2147483648
|
||||
; CHECK-T2-NEXT: cmp lr, r4
|
||||
; CHECK-T2-NEXT: it vc
|
||||
; CHECK-T2-NEXT: movvc r0, r6
|
||||
; CHECK-T2-NEXT: subs r6, r1, r7
|
||||
; CHECK-T2-NEXT: mov.w r4, #0
|
||||
; CHECK-T2-NEXT: mov.w lr, #-2147483648
|
||||
; CHECK-T2-NEXT: it mi
|
||||
; CHECK-T2-NEXT: movmi r4, #1
|
||||
; CHECK-T2-NEXT: cmp r4, #0
|
||||
; CHECK-T2-NEXT: it ne
|
||||
; CHECK-T2-NEXT: mvnne lr, #-2147483648
|
||||
; CHECK-T2-NEXT: cmp r1, r7
|
||||
; CHECK-T2-NEXT: ldr r1, [sp, #32]
|
||||
; CHECK-T2-NEXT: mov.w r4, #0
|
||||
; CHECK-T2-NEXT: it vc
|
||||
; CHECK-T2-NEXT: movvc lr, r6
|
||||
; CHECK-T2-NEXT: subs r6, r2, r1
|
||||
; CHECK-T2-NEXT: it mi
|
||||
; CHECK-T2-NEXT: movmi r4, #1
|
||||
; CHECK-T2-NEXT: cmp r4, #0
|
||||
; CHECK-T2-NEXT: mov.w r4, #-2147483648
|
||||
; CHECK-T2-NEXT: it ne
|
||||
; CHECK-T2-NEXT: mvnne r4, #-2147483648
|
||||
; CHECK-T2-NEXT: cmp r2, r1
|
||||
; CHECK-T2-NEXT: ldr r1, [sp, #36]
|
||||
; CHECK-T2-NEXT: it vc
|
||||
; CHECK-T2-NEXT: movvc r4, r6
|
||||
; CHECK-T2-NEXT: subs r2, r3, r1
|
||||
; CHECK-T2-NEXT: it mi
|
||||
; CHECK-T2-NEXT: movmi r5, #1
|
||||
; CHECK-T2-NEXT: cmp r5, #0
|
||||
; CHECK-T2-NEXT: it ne
|
||||
; CHECK-T2-NEXT: mvnne r12, #-2147483648
|
||||
; CHECK-T2-NEXT: cmp r3, r1
|
||||
; CHECK-T2-NEXT: it vc
|
||||
; CHECK-T2-NEXT: movvc r12, r2
|
||||
; CHECK-T2-NEXT: mov r1, lr
|
||||
; CHECK-T2-NEXT: mov r2, r4
|
||||
; CHECK-T2-NEXT: mov r3, r12
|
||||
; CHECK-T2-NEXT: add sp, #4
|
||||
; CHECK-T2-NEXT: pop {r4, r5, r6, r7, pc}
|
||||
;
|
||||
; CHECK-ARM-LABEL: vec:
|
||||
; CHECK-ARM: @ %bb.0:
|
||||
; CHECK-ARM-NEXT: vmov d17, r2, r3
|
||||
; CHECK-ARM-NEXT: mov r12, sp
|
||||
; CHECK-ARM-NEXT: vld1.64 {d18, d19}, [r12]
|
||||
; CHECK-ARM-NEXT: vmov d16, r0, r1
|
||||
; CHECK-ARM-NEXT: vmvn.i32 q11, #0x80000000
|
||||
; CHECK-ARM-NEXT: vsub.i32 q10, q8, q9
|
||||
; CHECK-ARM-NEXT: vcgt.s32 q9, q9, #0
|
||||
; CHECK-ARM-NEXT: vclt.s32 q12, q10, #0
|
||||
; CHECK-ARM-NEXT: vmvn q13, q12
|
||||
; CHECK-ARM-NEXT: vcgt.s32 q8, q8, q10
|
||||
; CHECK-ARM-NEXT: vbsl q11, q12, q13
|
||||
; CHECK-ARM-NEXT: veor q8, q9, q8
|
||||
; CHECK-ARM-NEXT: vbsl q8, q11, q10
|
||||
; CHECK-ARM-NEXT: vmov r0, r1, d16
|
||||
; CHECK-ARM-NEXT: vmov r2, r3, d17
|
||||
; CHECK-ARM-NEXT: bx lr
|
||||
%tmp = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %x, <4 x i32> %y)
|
||||
ret <4 x i32> %tmp
|
||||
}
|
||||
199
test/CodeGen/ARM/uadd_sat.ll
Normal file
199
test/CodeGen/ARM/uadd_sat.ll
Normal file
@ -0,0 +1,199 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=CHECK-T1
|
||||
; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2NODSP
|
||||
; RUN: llc < %s -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2DSP
|
||||
; RUN: llc < %s -mtriple=armv8a-none-eabi | FileCheck %s --check-prefix=CHECK-ARM
|
||||
|
||||
declare i4 @llvm.uadd.sat.i4(i4, i4)
|
||||
declare i8 @llvm.uadd.sat.i8(i8, i8)
|
||||
declare i16 @llvm.uadd.sat.i16(i16, i16)
|
||||
declare i32 @llvm.uadd.sat.i32(i32, i32)
|
||||
declare i64 @llvm.uadd.sat.i64(i64, i64)
|
||||
|
||||
define i32 @func(i32 %x, i32 %y) nounwind {
|
||||
; CHECK-T1-LABEL: func:
|
||||
; CHECK-T1: @ %bb.0:
|
||||
; CHECK-T1-NEXT: adds r0, r0, r1
|
||||
; CHECK-T1-NEXT: blo .LBB0_2
|
||||
; CHECK-T1-NEXT: @ %bb.1:
|
||||
; CHECK-T1-NEXT: movs r0, #0
|
||||
; CHECK-T1-NEXT: mvns r0, r0
|
||||
; CHECK-T1-NEXT: .LBB0_2:
|
||||
; CHECK-T1-NEXT: bx lr
|
||||
;
|
||||
; CHECK-T2-LABEL: func:
|
||||
; CHECK-T2: @ %bb.0:
|
||||
; CHECK-T2-NEXT: adds r0, r0, r1
|
||||
; CHECK-T2-NEXT: it hs
|
||||
; CHECK-T2-NEXT: movhs.w r0, #-1
|
||||
; CHECK-T2-NEXT: bx lr
|
||||
;
|
||||
; CHECK-ARM-LABEL: func:
|
||||
; CHECK-ARM: @ %bb.0:
|
||||
; CHECK-ARM-NEXT: adds r0, r0, r1
|
||||
; CHECK-ARM-NEXT: mvnhs r0, #0
|
||||
; CHECK-ARM-NEXT: bx lr
|
||||
%tmp = call i32 @llvm.uadd.sat.i32(i32 %x, i32 %y)
|
||||
ret i32 %tmp
|
||||
}
|
||||
|
||||
define i64 @func2(i64 %x, i64 %y) nounwind {
|
||||
; CHECK-T1-LABEL: func2:
|
||||
; CHECK-T1: @ %bb.0:
|
||||
; CHECK-T1-NEXT: .save {r4, r5, r7, lr}
|
||||
; CHECK-T1-NEXT: push {r4, r5, r7, lr}
|
||||
; CHECK-T1-NEXT: movs r5, #0
|
||||
; CHECK-T1-NEXT: adds r4, r0, r2
|
||||
; CHECK-T1-NEXT: adcs r1, r3
|
||||
; CHECK-T1-NEXT: mov r3, r5
|
||||
; CHECK-T1-NEXT: adcs r3, r5
|
||||
; CHECK-T1-NEXT: mvns r2, r5
|
||||
; CHECK-T1-NEXT: cmp r3, #0
|
||||
; CHECK-T1-NEXT: mov r0, r2
|
||||
; CHECK-T1-NEXT: beq .LBB1_3
|
||||
; CHECK-T1-NEXT: @ %bb.1:
|
||||
; CHECK-T1-NEXT: cmp r3, #0
|
||||
; CHECK-T1-NEXT: beq .LBB1_4
|
||||
; CHECK-T1-NEXT: .LBB1_2:
|
||||
; CHECK-T1-NEXT: mov r1, r2
|
||||
; CHECK-T1-NEXT: pop {r4, r5, r7, pc}
|
||||
; CHECK-T1-NEXT: .LBB1_3:
|
||||
; CHECK-T1-NEXT: mov r0, r4
|
||||
; CHECK-T1-NEXT: cmp r3, #0
|
||||
; CHECK-T1-NEXT: bne .LBB1_2
|
||||
; CHECK-T1-NEXT: .LBB1_4:
|
||||
; CHECK-T1-NEXT: mov r2, r1
|
||||
; CHECK-T1-NEXT: mov r1, r2
|
||||
; CHECK-T1-NEXT: pop {r4, r5, r7, pc}
|
||||
;
|
||||
; CHECK-T2-LABEL: func2:
|
||||
; CHECK-T2: @ %bb.0:
|
||||
; CHECK-T2-NEXT: adds r0, r0, r2
|
||||
; CHECK-T2-NEXT: mov.w r12, #0
|
||||
; CHECK-T2-NEXT: adcs r1, r3
|
||||
; CHECK-T2-NEXT: adcs r2, r12, #0
|
||||
; CHECK-T2-NEXT: itt ne
|
||||
; CHECK-T2-NEXT: movne.w r0, #-1
|
||||
; CHECK-T2-NEXT: movne.w r1, #-1
|
||||
; CHECK-T2-NEXT: bx lr
|
||||
;
|
||||
; CHECK-ARM-LABEL: func2:
|
||||
; CHECK-ARM: @ %bb.0:
|
||||
; CHECK-ARM-NEXT: adds r0, r0, r2
|
||||
; CHECK-ARM-NEXT: mov r12, #0
|
||||
; CHECK-ARM-NEXT: adcs r1, r1, r3
|
||||
; CHECK-ARM-NEXT: adcs r2, r12, #0
|
||||
; CHECK-ARM-NEXT: mvnne r0, #0
|
||||
; CHECK-ARM-NEXT: mvnne r1, #0
|
||||
; CHECK-ARM-NEXT: bx lr
|
||||
%tmp = call i64 @llvm.uadd.sat.i64(i64 %x, i64 %y)
|
||||
ret i64 %tmp
|
||||
}
|
||||
|
||||
define i16 @func16(i16 %x, i16 %y) nounwind {
|
||||
; CHECK-T1-LABEL: func16:
|
||||
; CHECK-T1: @ %bb.0:
|
||||
; CHECK-T1-NEXT: lsls r1, r1, #16
|
||||
; CHECK-T1-NEXT: lsls r0, r0, #16
|
||||
; CHECK-T1-NEXT: adds r0, r0, r1
|
||||
; CHECK-T1-NEXT: blo .LBB2_2
|
||||
; CHECK-T1-NEXT: @ %bb.1:
|
||||
; CHECK-T1-NEXT: movs r0, #0
|
||||
; CHECK-T1-NEXT: mvns r0, r0
|
||||
; CHECK-T1-NEXT: .LBB2_2:
|
||||
; CHECK-T1-NEXT: lsrs r0, r0, #16
|
||||
; CHECK-T1-NEXT: bx lr
|
||||
;
|
||||
; CHECK-T2-LABEL: func16:
|
||||
; CHECK-T2: @ %bb.0:
|
||||
; CHECK-T2-NEXT: lsls r2, r0, #16
|
||||
; CHECK-T2-NEXT: add.w r1, r2, r1, lsl #16
|
||||
; CHECK-T2-NEXT: cmp.w r1, r0, lsl #16
|
||||
; CHECK-T2-NEXT: it lo
|
||||
; CHECK-T2-NEXT: movlo.w r1, #-1
|
||||
; CHECK-T2-NEXT: lsrs r0, r1, #16
|
||||
; CHECK-T2-NEXT: bx lr
|
||||
;
|
||||
; CHECK-ARM-LABEL: func16:
|
||||
; CHECK-ARM: @ %bb.0:
|
||||
; CHECK-ARM-NEXT: lsl r2, r0, #16
|
||||
; CHECK-ARM-NEXT: add r1, r2, r1, lsl #16
|
||||
; CHECK-ARM-NEXT: cmp r1, r0, lsl #16
|
||||
; CHECK-ARM-NEXT: mvnlo r1, #0
|
||||
; CHECK-ARM-NEXT: lsr r0, r1, #16
|
||||
; CHECK-ARM-NEXT: bx lr
|
||||
%tmp = call i16 @llvm.uadd.sat.i16(i16 %x, i16 %y)
|
||||
ret i16 %tmp
|
||||
}
|
||||
|
||||
define i8 @func8(i8 %x, i8 %y) nounwind {
|
||||
; CHECK-T1-LABEL: func8:
|
||||
; CHECK-T1: @ %bb.0:
|
||||
; CHECK-T1-NEXT: lsls r1, r1, #24
|
||||
; CHECK-T1-NEXT: lsls r0, r0, #24
|
||||
; CHECK-T1-NEXT: adds r0, r0, r1
|
||||
; CHECK-T1-NEXT: blo .LBB3_2
|
||||
; CHECK-T1-NEXT: @ %bb.1:
|
||||
; CHECK-T1-NEXT: movs r0, #0
|
||||
; CHECK-T1-NEXT: mvns r0, r0
|
||||
; CHECK-T1-NEXT: .LBB3_2:
|
||||
; CHECK-T1-NEXT: lsrs r0, r0, #24
|
||||
; CHECK-T1-NEXT: bx lr
|
||||
;
|
||||
; CHECK-T2-LABEL: func8:
|
||||
; CHECK-T2: @ %bb.0:
|
||||
; CHECK-T2-NEXT: lsls r2, r0, #24
|
||||
; CHECK-T2-NEXT: add.w r1, r2, r1, lsl #24
|
||||
; CHECK-T2-NEXT: cmp.w r1, r0, lsl #24
|
||||
; CHECK-T2-NEXT: it lo
|
||||
; CHECK-T2-NEXT: movlo.w r1, #-1
|
||||
; CHECK-T2-NEXT: lsrs r0, r1, #24
|
||||
; CHECK-T2-NEXT: bx lr
|
||||
;
|
||||
; CHECK-ARM-LABEL: func8:
|
||||
; CHECK-ARM: @ %bb.0:
|
||||
; CHECK-ARM-NEXT: lsl r2, r0, #24
|
||||
; CHECK-ARM-NEXT: add r1, r2, r1, lsl #24
|
||||
; CHECK-ARM-NEXT: cmp r1, r0, lsl #24
|
||||
; CHECK-ARM-NEXT: mvnlo r1, #0
|
||||
; CHECK-ARM-NEXT: lsr r0, r1, #24
|
||||
; CHECK-ARM-NEXT: bx lr
|
||||
%tmp = call i8 @llvm.uadd.sat.i8(i8 %x, i8 %y)
|
||||
ret i8 %tmp
|
||||
}
|
||||
|
||||
define i4 @func3(i4 %x, i4 %y) nounwind {
|
||||
; CHECK-T1-LABEL: func3:
|
||||
; CHECK-T1: @ %bb.0:
|
||||
; CHECK-T1-NEXT: lsls r1, r1, #28
|
||||
; CHECK-T1-NEXT: lsls r0, r0, #28
|
||||
; CHECK-T1-NEXT: adds r0, r0, r1
|
||||
; CHECK-T1-NEXT: blo .LBB4_2
|
||||
; CHECK-T1-NEXT: @ %bb.1:
|
||||
; CHECK-T1-NEXT: movs r0, #0
|
||||
; CHECK-T1-NEXT: mvns r0, r0
|
||||
; CHECK-T1-NEXT: .LBB4_2:
|
||||
; CHECK-T1-NEXT: lsrs r0, r0, #28
|
||||
; CHECK-T1-NEXT: bx lr
|
||||
;
|
||||
; CHECK-T2-LABEL: func3:
|
||||
; CHECK-T2: @ %bb.0:
|
||||
; CHECK-T2-NEXT: lsls r2, r0, #28
|
||||
; CHECK-T2-NEXT: add.w r1, r2, r1, lsl #28
|
||||
; CHECK-T2-NEXT: cmp.w r1, r0, lsl #28
|
||||
; CHECK-T2-NEXT: it lo
|
||||
; CHECK-T2-NEXT: movlo.w r1, #-1
|
||||
; CHECK-T2-NEXT: lsrs r0, r1, #28
|
||||
; CHECK-T2-NEXT: bx lr
|
||||
;
|
||||
; CHECK-ARM-LABEL: func3:
|
||||
; CHECK-ARM: @ %bb.0:
|
||||
; CHECK-ARM-NEXT: lsl r2, r0, #28
|
||||
; CHECK-ARM-NEXT: add r1, r2, r1, lsl #28
|
||||
; CHECK-ARM-NEXT: cmp r1, r0, lsl #28
|
||||
; CHECK-ARM-NEXT: mvnlo r1, #0
|
||||
; CHECK-ARM-NEXT: lsr r0, r1, #28
|
||||
; CHECK-ARM-NEXT: bx lr
|
||||
%tmp = call i4 @llvm.uadd.sat.i4(i4 %x, i4 %y)
|
||||
ret i4 %tmp
|
||||
}
|
||||
196
test/CodeGen/ARM/usub_sat.ll
Normal file
196
test/CodeGen/ARM/usub_sat.ll
Normal file
@ -0,0 +1,196 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=CHECK-T1
|
||||
; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2NODSP
|
||||
; RUN: llc < %s -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2DSP
|
||||
; RUN: llc < %s -mtriple=armv8a-none-eabi | FileCheck %s --check-prefix=CHECK-ARM
|
||||
|
||||
declare i4 @llvm.usub.sat.i4(i4, i4)
|
||||
declare i8 @llvm.usub.sat.i8(i8, i8)
|
||||
declare i16 @llvm.usub.sat.i16(i16, i16)
|
||||
declare i32 @llvm.usub.sat.i32(i32, i32)
|
||||
declare i64 @llvm.usub.sat.i64(i64, i64)
|
||||
|
||||
define i32 @func(i32 %x, i32 %y) nounwind {
|
||||
; CHECK-T1-LABEL: func:
|
||||
; CHECK-T1: @ %bb.0:
|
||||
; CHECK-T1-NEXT: subs r0, r0, r1
|
||||
; CHECK-T1-NEXT: bhs .LBB0_2
|
||||
; CHECK-T1-NEXT: @ %bb.1:
|
||||
; CHECK-T1-NEXT: movs r0, #0
|
||||
; CHECK-T1-NEXT: .LBB0_2:
|
||||
; CHECK-T1-NEXT: bx lr
|
||||
;
|
||||
; CHECK-T2-LABEL: func:
|
||||
; CHECK-T2: @ %bb.0:
|
||||
; CHECK-T2-NEXT: subs r0, r0, r1
|
||||
; CHECK-T2-NEXT: it lo
|
||||
; CHECK-T2-NEXT: movlo r0, #0
|
||||
; CHECK-T2-NEXT: bx lr
|
||||
;
|
||||
; CHECK-ARM-LABEL: func:
|
||||
; CHECK-ARM: @ %bb.0:
|
||||
; CHECK-ARM-NEXT: subs r0, r0, r1
|
||||
; CHECK-ARM-NEXT: movlo r0, #0
|
||||
; CHECK-ARM-NEXT: bx lr
|
||||
%tmp = call i32 @llvm.usub.sat.i32(i32 %x, i32 %y)
|
||||
ret i32 %tmp
|
||||
}
|
||||
|
||||
define i64 @func2(i64 %x, i64 %y) nounwind {
|
||||
; CHECK-T1-LABEL: func2:
|
||||
; CHECK-T1: @ %bb.0:
|
||||
; CHECK-T1-NEXT: .save {r4, lr}
|
||||
; CHECK-T1-NEXT: push {r4, lr}
|
||||
; CHECK-T1-NEXT: mov r4, r1
|
||||
; CHECK-T1-NEXT: movs r1, #0
|
||||
; CHECK-T1-NEXT: subs r2, r0, r2
|
||||
; CHECK-T1-NEXT: sbcs r4, r3
|
||||
; CHECK-T1-NEXT: mov r0, r1
|
||||
; CHECK-T1-NEXT: adcs r0, r1
|
||||
; CHECK-T1-NEXT: movs r3, #1
|
||||
; CHECK-T1-NEXT: subs r3, r3, r0
|
||||
; CHECK-T1-NEXT: mov r0, r1
|
||||
; CHECK-T1-NEXT: beq .LBB1_3
|
||||
; CHECK-T1-NEXT: @ %bb.1:
|
||||
; CHECK-T1-NEXT: cmp r3, #0
|
||||
; CHECK-T1-NEXT: beq .LBB1_4
|
||||
; CHECK-T1-NEXT: .LBB1_2:
|
||||
; CHECK-T1-NEXT: pop {r4, pc}
|
||||
; CHECK-T1-NEXT: .LBB1_3:
|
||||
; CHECK-T1-NEXT: mov r0, r2
|
||||
; CHECK-T1-NEXT: cmp r3, #0
|
||||
; CHECK-T1-NEXT: bne .LBB1_2
|
||||
; CHECK-T1-NEXT: .LBB1_4:
|
||||
; CHECK-T1-NEXT: mov r1, r4
|
||||
; CHECK-T1-NEXT: pop {r4, pc}
|
||||
;
|
||||
; CHECK-T2-LABEL: func2:
|
||||
; CHECK-T2: @ %bb.0:
|
||||
; CHECK-T2-NEXT: subs r0, r0, r2
|
||||
; CHECK-T2-NEXT: mov.w r12, #0
|
||||
; CHECK-T2-NEXT: sbcs r1, r3
|
||||
; CHECK-T2-NEXT: adc r2, r12, #0
|
||||
; CHECK-T2-NEXT: rsbs.w r2, r2, #1
|
||||
; CHECK-T2-NEXT: itt ne
|
||||
; CHECK-T2-NEXT: movne r0, #0
|
||||
; CHECK-T2-NEXT: movne r1, #0
|
||||
; CHECK-T2-NEXT: bx lr
|
||||
;
|
||||
; CHECK-ARM-LABEL: func2:
|
||||
; CHECK-ARM: @ %bb.0:
|
||||
; CHECK-ARM-NEXT: subs r0, r0, r2
|
||||
; CHECK-ARM-NEXT: mov r12, #0
|
||||
; CHECK-ARM-NEXT: sbcs r1, r1, r3
|
||||
; CHECK-ARM-NEXT: adc r2, r12, #0
|
||||
; CHECK-ARM-NEXT: rsbs r2, r2, #1
|
||||
; CHECK-ARM-NEXT: movwne r0, #0
|
||||
; CHECK-ARM-NEXT: movwne r1, #0
|
||||
; CHECK-ARM-NEXT: bx lr
|
||||
%tmp = call i64 @llvm.usub.sat.i64(i64 %x, i64 %y)
|
||||
ret i64 %tmp
|
||||
}
|
||||
|
||||
define i16 @func16(i16 %x, i16 %y) nounwind {
|
||||
; CHECK-T1-LABEL: func16:
|
||||
; CHECK-T1: @ %bb.0:
|
||||
; CHECK-T1-NEXT: lsls r1, r1, #16
|
||||
; CHECK-T1-NEXT: lsls r0, r0, #16
|
||||
; CHECK-T1-NEXT: subs r0, r0, r1
|
||||
; CHECK-T1-NEXT: bhs .LBB2_2
|
||||
; CHECK-T1-NEXT: @ %bb.1:
|
||||
; CHECK-T1-NEXT: movs r0, #0
|
||||
; CHECK-T1-NEXT: .LBB2_2:
|
||||
; CHECK-T1-NEXT: lsrs r0, r0, #16
|
||||
; CHECK-T1-NEXT: bx lr
|
||||
;
|
||||
; CHECK-T2-LABEL: func16:
|
||||
; CHECK-T2: @ %bb.0:
|
||||
; CHECK-T2-NEXT: lsls r0, r0, #16
|
||||
; CHECK-T2-NEXT: sub.w r2, r0, r1, lsl #16
|
||||
; CHECK-T2-NEXT: cmp.w r0, r1, lsl #16
|
||||
; CHECK-T2-NEXT: it lo
|
||||
; CHECK-T2-NEXT: movlo r2, #0
|
||||
; CHECK-T2-NEXT: lsrs r0, r2, #16
|
||||
; CHECK-T2-NEXT: bx lr
|
||||
;
|
||||
; CHECK-ARM-LABEL: func16:
|
||||
; CHECK-ARM: @ %bb.0:
|
||||
; CHECK-ARM-NEXT: lsl r0, r0, #16
|
||||
; CHECK-ARM-NEXT: sub r2, r0, r1, lsl #16
|
||||
; CHECK-ARM-NEXT: cmp r0, r1, lsl #16
|
||||
; CHECK-ARM-NEXT: movlo r2, #0
|
||||
; CHECK-ARM-NEXT: lsr r0, r2, #16
|
||||
; CHECK-ARM-NEXT: bx lr
|
||||
%tmp = call i16 @llvm.usub.sat.i16(i16 %x, i16 %y)
|
||||
ret i16 %tmp
|
||||
}
|
||||
|
||||
define i8 @func8(i8 %x, i8 %y) nounwind {
|
||||
; CHECK-T1-LABEL: func8:
|
||||
; CHECK-T1: @ %bb.0:
|
||||
; CHECK-T1-NEXT: lsls r1, r1, #24
|
||||
; CHECK-T1-NEXT: lsls r0, r0, #24
|
||||
; CHECK-T1-NEXT: subs r0, r0, r1
|
||||
; CHECK-T1-NEXT: bhs .LBB3_2
|
||||
; CHECK-T1-NEXT: @ %bb.1:
|
||||
; CHECK-T1-NEXT: movs r0, #0
|
||||
; CHECK-T1-NEXT: .LBB3_2:
|
||||
; CHECK-T1-NEXT: lsrs r0, r0, #24
|
||||
; CHECK-T1-NEXT: bx lr
|
||||
;
|
||||
; CHECK-T2-LABEL: func8:
|
||||
; CHECK-T2: @ %bb.0:
|
||||
; CHECK-T2-NEXT: lsls r0, r0, #24
|
||||
; CHECK-T2-NEXT: sub.w r2, r0, r1, lsl #24
|
||||
; CHECK-T2-NEXT: cmp.w r0, r1, lsl #24
|
||||
; CHECK-T2-NEXT: it lo
|
||||
; CHECK-T2-NEXT: movlo r2, #0
|
||||
; CHECK-T2-NEXT: lsrs r0, r2, #24
|
||||
; CHECK-T2-NEXT: bx lr
|
||||
;
|
||||
; CHECK-ARM-LABEL: func8:
|
||||
; CHECK-ARM: @ %bb.0:
|
||||
; CHECK-ARM-NEXT: lsl r0, r0, #24
|
||||
; CHECK-ARM-NEXT: sub r2, r0, r1, lsl #24
|
||||
; CHECK-ARM-NEXT: cmp r0, r1, lsl #24
|
||||
; CHECK-ARM-NEXT: movlo r2, #0
|
||||
; CHECK-ARM-NEXT: lsr r0, r2, #24
|
||||
; CHECK-ARM-NEXT: bx lr
|
||||
%tmp = call i8 @llvm.usub.sat.i8(i8 %x, i8 %y)
|
||||
ret i8 %tmp
|
||||
}
|
||||
|
||||
define i4 @func3(i4 %x, i4 %y) nounwind {
|
||||
; CHECK-T1-LABEL: func3:
|
||||
; CHECK-T1: @ %bb.0:
|
||||
; CHECK-T1-NEXT: lsls r1, r1, #28
|
||||
; CHECK-T1-NEXT: lsls r0, r0, #28
|
||||
; CHECK-T1-NEXT: subs r0, r0, r1
|
||||
; CHECK-T1-NEXT: bhs .LBB4_2
|
||||
; CHECK-T1-NEXT: @ %bb.1:
|
||||
; CHECK-T1-NEXT: movs r0, #0
|
||||
; CHECK-T1-NEXT: .LBB4_2:
|
||||
; CHECK-T1-NEXT: lsrs r0, r0, #28
|
||||
; CHECK-T1-NEXT: bx lr
|
||||
;
|
||||
; CHECK-T2-LABEL: func3:
|
||||
; CHECK-T2: @ %bb.0:
|
||||
; CHECK-T2-NEXT: lsls r0, r0, #28
|
||||
; CHECK-T2-NEXT: sub.w r2, r0, r1, lsl #28
|
||||
; CHECK-T2-NEXT: cmp.w r0, r1, lsl #28
|
||||
; CHECK-T2-NEXT: it lo
|
||||
; CHECK-T2-NEXT: movlo r2, #0
|
||||
; CHECK-T2-NEXT: lsrs r0, r2, #28
|
||||
; CHECK-T2-NEXT: bx lr
|
||||
;
|
||||
; CHECK-ARM-LABEL: func3:
|
||||
; CHECK-ARM: @ %bb.0:
|
||||
; CHECK-ARM-NEXT: lsl r0, r0, #28
|
||||
; CHECK-ARM-NEXT: sub r2, r0, r1, lsl #28
|
||||
; CHECK-ARM-NEXT: cmp r0, r1, lsl #28
|
||||
; CHECK-ARM-NEXT: movlo r2, #0
|
||||
; CHECK-ARM-NEXT: lsr r0, r2, #28
|
||||
; CHECK-ARM-NEXT: bx lr
|
||||
%tmp = call i4 @llvm.usub.sat.i4(i4 %x, i4 %y)
|
||||
ret i4 %tmp
|
||||
}
|
||||
@ -2,10 +2,12 @@
|
||||
; RUN: llc < %s -mtriple=i686 -mattr=cmov | FileCheck %s --check-prefixes=CHECK,X86
|
||||
; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s --check-prefixes=CHECK,X64
|
||||
|
||||
declare i4 @llvm.sadd.sat.i4 (i4, i4)
|
||||
declare i32 @llvm.sadd.sat.i32 (i32, i32)
|
||||
declare i64 @llvm.sadd.sat.i64 (i64, i64)
|
||||
declare <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32>, <4 x i32>)
|
||||
declare i4 @llvm.sadd.sat.i4(i4, i4)
|
||||
declare i8 @llvm.sadd.sat.i8(i8, i8)
|
||||
declare i16 @llvm.sadd.sat.i16(i16, i16)
|
||||
declare i32 @llvm.sadd.sat.i32(i32, i32)
|
||||
declare i64 @llvm.sadd.sat.i64(i64, i64)
|
||||
declare <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32>, <4 x i32>)
|
||||
|
||||
define i32 @func(i32 %x, i32 %y) nounwind {
|
||||
; X86-LABEL: func:
|
||||
@ -89,6 +91,70 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
|
||||
ret i64 %tmp;
|
||||
}
|
||||
|
||||
define i16 @func16(i16 %x, i16 %y) nounwind {
|
||||
; X86-LABEL: func16:
|
||||
; X86: # %bb.0:
|
||||
; X86-NEXT: pushl %esi
|
||||
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
|
||||
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %edx
|
||||
; X86-NEXT: xorl %ecx, %ecx
|
||||
; X86-NEXT: movl %eax, %esi
|
||||
; X86-NEXT: addw %dx, %si
|
||||
; X86-NEXT: setns %cl
|
||||
; X86-NEXT: addl $32767, %ecx # imm = 0x7FFF
|
||||
; X86-NEXT: addw %dx, %ax
|
||||
; X86-NEXT: cmovol %ecx, %eax
|
||||
; X86-NEXT: # kill: def $ax killed $ax killed $eax
|
||||
; X86-NEXT: popl %esi
|
||||
; X86-NEXT: retl
|
||||
;
|
||||
; X64-LABEL: func16:
|
||||
; X64: # %bb.0:
|
||||
; X64-NEXT: xorl %eax, %eax
|
||||
; X64-NEXT: movl %edi, %ecx
|
||||
; X64-NEXT: addw %si, %cx
|
||||
; X64-NEXT: setns %al
|
||||
; X64-NEXT: addl $32767, %eax # imm = 0x7FFF
|
||||
; X64-NEXT: addw %si, %di
|
||||
; X64-NEXT: cmovnol %edi, %eax
|
||||
; X64-NEXT: # kill: def $ax killed $ax killed $eax
|
||||
; X64-NEXT: retq
|
||||
%tmp = call i16 @llvm.sadd.sat.i16(i16 %x, i16 %y)
|
||||
ret i16 %tmp
|
||||
}
|
||||
|
||||
define i8 @func8(i8 %x, i8 %y) nounwind {
|
||||
; X86-LABEL: func8:
|
||||
; X86: # %bb.0:
|
||||
; X86-NEXT: movb {{[0-9]+}}(%esp), %al
|
||||
; X86-NEXT: movb {{[0-9]+}}(%esp), %dl
|
||||
; X86-NEXT: xorl %ecx, %ecx
|
||||
; X86-NEXT: movb %al, %ah
|
||||
; X86-NEXT: addb %dl, %ah
|
||||
; X86-NEXT: setns %cl
|
||||
; X86-NEXT: addl $127, %ecx
|
||||
; X86-NEXT: addb %dl, %al
|
||||
; X86-NEXT: movzbl %al, %eax
|
||||
; X86-NEXT: cmovol %ecx, %eax
|
||||
; X86-NEXT: # kill: def $al killed $al killed $eax
|
||||
; X86-NEXT: retl
|
||||
;
|
||||
; X64-LABEL: func8:
|
||||
; X64: # %bb.0:
|
||||
; X64-NEXT: xorl %ecx, %ecx
|
||||
; X64-NEXT: movl %edi, %eax
|
||||
; X64-NEXT: addb %sil, %al
|
||||
; X64-NEXT: setns %cl
|
||||
; X64-NEXT: addl $127, %ecx
|
||||
; X64-NEXT: addb %sil, %dil
|
||||
; X64-NEXT: movzbl %dil, %eax
|
||||
; X64-NEXT: cmovol %ecx, %eax
|
||||
; X64-NEXT: # kill: def $al killed $al killed $eax
|
||||
; X64-NEXT: retq
|
||||
%tmp = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %y)
|
||||
ret i8 %tmp
|
||||
}
|
||||
|
||||
define i4 @func3(i4 %x, i4 %y) nounwind {
|
||||
; X86-LABEL: func3:
|
||||
; X86: # %bb.0:
|
||||
|
||||
@ -2,10 +2,12 @@
|
||||
; RUN: llc < %s -mtriple=i686 -mattr=cmov | FileCheck %s --check-prefixes=CHECK,X86
|
||||
; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s --check-prefixes=CHECK,X64
|
||||
|
||||
declare i4 @llvm.ssub.sat.i4 (i4, i4)
|
||||
declare i32 @llvm.ssub.sat.i32 (i32, i32)
|
||||
declare i64 @llvm.ssub.sat.i64 (i64, i64)
|
||||
declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32>, <4 x i32>)
|
||||
declare i4 @llvm.ssub.sat.i4(i4, i4)
|
||||
declare i8 @llvm.ssub.sat.i8(i8, i8)
|
||||
declare i16 @llvm.ssub.sat.i16(i16, i16)
|
||||
declare i32 @llvm.ssub.sat.i32(i32, i32)
|
||||
declare i64 @llvm.ssub.sat.i64(i64, i64)
|
||||
declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32>, <4 x i32>)
|
||||
|
||||
define i32 @func(i32 %x, i32 %y) nounwind {
|
||||
; X86-LABEL: func:
|
||||
@ -89,6 +91,70 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
|
||||
ret i64 %tmp
|
||||
}
|
||||
|
||||
define i16 @func16(i16 %x, i16 %y) nounwind {
|
||||
; X86-LABEL: func16:
|
||||
; X86: # %bb.0:
|
||||
; X86-NEXT: pushl %esi
|
||||
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
|
||||
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %edx
|
||||
; X86-NEXT: xorl %ecx, %ecx
|
||||
; X86-NEXT: movl %eax, %esi
|
||||
; X86-NEXT: subw %dx, %si
|
||||
; X86-NEXT: setns %cl
|
||||
; X86-NEXT: addl $32767, %ecx # imm = 0x7FFF
|
||||
; X86-NEXT: subw %dx, %ax
|
||||
; X86-NEXT: cmovol %ecx, %eax
|
||||
; X86-NEXT: # kill: def $ax killed $ax killed $eax
|
||||
; X86-NEXT: popl %esi
|
||||
; X86-NEXT: retl
|
||||
;
|
||||
; X64-LABEL: func16:
|
||||
; X64: # %bb.0:
|
||||
; X64-NEXT: xorl %eax, %eax
|
||||
; X64-NEXT: movl %edi, %ecx
|
||||
; X64-NEXT: subw %si, %cx
|
||||
; X64-NEXT: setns %al
|
||||
; X64-NEXT: addl $32767, %eax # imm = 0x7FFF
|
||||
; X64-NEXT: subw %si, %di
|
||||
; X64-NEXT: cmovnol %edi, %eax
|
||||
; X64-NEXT: # kill: def $ax killed $ax killed $eax
|
||||
; X64-NEXT: retq
|
||||
%tmp = call i16 @llvm.ssub.sat.i16(i16 %x, i16 %y)
|
||||
ret i16 %tmp
|
||||
}
|
||||
|
||||
define i8 @func8(i8 %x, i8 %y) nounwind {
|
||||
; X86-LABEL: func8:
|
||||
; X86: # %bb.0:
|
||||
; X86-NEXT: movb {{[0-9]+}}(%esp), %al
|
||||
; X86-NEXT: movb {{[0-9]+}}(%esp), %dl
|
||||
; X86-NEXT: xorl %ecx, %ecx
|
||||
; X86-NEXT: movb %al, %ah
|
||||
; X86-NEXT: subb %dl, %ah
|
||||
; X86-NEXT: setns %cl
|
||||
; X86-NEXT: addl $127, %ecx
|
||||
; X86-NEXT: subb %dl, %al
|
||||
; X86-NEXT: movzbl %al, %eax
|
||||
; X86-NEXT: cmovol %ecx, %eax
|
||||
; X86-NEXT: # kill: def $al killed $al killed $eax
|
||||
; X86-NEXT: retl
|
||||
;
|
||||
; X64-LABEL: func8:
|
||||
; X64: # %bb.0:
|
||||
; X64-NEXT: xorl %ecx, %ecx
|
||||
; X64-NEXT: movl %edi, %eax
|
||||
; X64-NEXT: subb %sil, %al
|
||||
; X64-NEXT: setns %cl
|
||||
; X64-NEXT: addl $127, %ecx
|
||||
; X64-NEXT: subb %sil, %dil
|
||||
; X64-NEXT: movzbl %dil, %eax
|
||||
; X64-NEXT: cmovol %ecx, %eax
|
||||
; X64-NEXT: # kill: def $al killed $al killed $eax
|
||||
; X64-NEXT: retq
|
||||
%tmp = call i8 @llvm.ssub.sat.i8(i8 %x, i8 %y)
|
||||
ret i8 %tmp
|
||||
}
|
||||
|
||||
define i4 @func3(i4 %x, i4 %y) nounwind {
|
||||
; X86-LABEL: func3:
|
||||
; X86: # %bb.0:
|
||||
|
||||
@ -2,10 +2,12 @@
|
||||
; RUN: llc < %s -mtriple=i686 -mattr=cmov | FileCheck %s --check-prefixes=CHECK,X86
|
||||
; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s --check-prefixes=CHECK,X64
|
||||
|
||||
declare i4 @llvm.uadd.sat.i4 (i4, i4)
|
||||
declare i32 @llvm.uadd.sat.i32 (i32, i32)
|
||||
declare i64 @llvm.uadd.sat.i64 (i64, i64)
|
||||
declare <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32>, <4 x i32>)
|
||||
declare i4 @llvm.uadd.sat.i4(i4, i4)
|
||||
declare i8 @llvm.uadd.sat.i8(i8, i8)
|
||||
declare i16 @llvm.uadd.sat.i16(i16, i16)
|
||||
declare i32 @llvm.uadd.sat.i32(i32, i32)
|
||||
declare i64 @llvm.uadd.sat.i64(i64, i64)
|
||||
declare <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32>, <4 x i32>)
|
||||
|
||||
define i32 @func(i32 %x, i32 %y) nounwind {
|
||||
; X86-LABEL: func:
|
||||
@ -48,6 +50,50 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
|
||||
ret i64 %tmp
|
||||
}
|
||||
|
||||
define i16 @func16(i16 %x, i16 %y) nounwind {
|
||||
; X86-LABEL: func16:
|
||||
; X86: # %bb.0:
|
||||
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
|
||||
; X86-NEXT: addw {{[0-9]+}}(%esp), %cx
|
||||
; X86-NEXT: movl $65535, %eax # imm = 0xFFFF
|
||||
; X86-NEXT: cmovael %ecx, %eax
|
||||
; X86-NEXT: # kill: def $ax killed $ax killed $eax
|
||||
; X86-NEXT: retl
|
||||
;
|
||||
; X64-LABEL: func16:
|
||||
; X64: # %bb.0:
|
||||
; X64-NEXT: addw %si, %di
|
||||
; X64-NEXT: movl $65535, %eax # imm = 0xFFFF
|
||||
; X64-NEXT: cmovael %edi, %eax
|
||||
; X64-NEXT: # kill: def $ax killed $ax killed $eax
|
||||
; X64-NEXT: retq
|
||||
%tmp = call i16 @llvm.uadd.sat.i16(i16 %x, i16 %y)
|
||||
ret i16 %tmp
|
||||
}
|
||||
|
||||
define i8 @func8(i8 %x, i8 %y) nounwind {
|
||||
; X86-LABEL: func8:
|
||||
; X86: # %bb.0:
|
||||
; X86-NEXT: movb {{[0-9]+}}(%esp), %al
|
||||
; X86-NEXT: addb {{[0-9]+}}(%esp), %al
|
||||
; X86-NEXT: movzbl %al, %ecx
|
||||
; X86-NEXT: movl $255, %eax
|
||||
; X86-NEXT: cmovael %ecx, %eax
|
||||
; X86-NEXT: # kill: def $al killed $al killed $eax
|
||||
; X86-NEXT: retl
|
||||
;
|
||||
; X64-LABEL: func8:
|
||||
; X64: # %bb.0:
|
||||
; X64-NEXT: addb %sil, %dil
|
||||
; X64-NEXT: movzbl %dil, %ecx
|
||||
; X64-NEXT: movl $255, %eax
|
||||
; X64-NEXT: cmovael %ecx, %eax
|
||||
; X64-NEXT: # kill: def $al killed $al killed $eax
|
||||
; X64-NEXT: retq
|
||||
%tmp = call i8 @llvm.uadd.sat.i8(i8 %x, i8 %y)
|
||||
ret i8 %tmp
|
||||
}
|
||||
|
||||
define i4 @func3(i4 %x, i4 %y) nounwind {
|
||||
; X86-LABEL: func3:
|
||||
; X86: # %bb.0:
|
||||
|
||||
@ -2,10 +2,12 @@
|
||||
; RUN: llc < %s -mtriple=i686 -mattr=cmov | FileCheck %s --check-prefixes=CHECK,X86
|
||||
; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s --check-prefixes=CHECK,X64
|
||||
|
||||
declare i4 @llvm.usub.sat.i4 (i4, i4)
|
||||
declare i32 @llvm.usub.sat.i32 (i32, i32)
|
||||
declare i64 @llvm.usub.sat.i64 (i64, i64)
|
||||
declare <4 x i32> @llvm.usub.sat.v4i32(<4 x i32>, <4 x i32>)
|
||||
declare i4 @llvm.usub.sat.i4(i4, i4)
|
||||
declare i8 @llvm.usub.sat.i8(i8, i8)
|
||||
declare i16 @llvm.usub.sat.i16(i16, i16)
|
||||
declare i32 @llvm.usub.sat.i32(i32, i32)
|
||||
declare i64 @llvm.usub.sat.i64(i64, i64)
|
||||
declare <4 x i32> @llvm.usub.sat.v4i32(<4 x i32>, <4 x i32>)
|
||||
|
||||
define i32 @func(i32 %x, i32 %y) nounwind {
|
||||
; X86-LABEL: func:
|
||||
@ -48,6 +50,50 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
|
||||
ret i64 %tmp
|
||||
}
|
||||
|
||||
define i16 @func16(i16 %x, i16 %y) nounwind {
|
||||
; X86-LABEL: func16:
|
||||
; X86: # %bb.0:
|
||||
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
|
||||
; X86-NEXT: xorl %ecx, %ecx
|
||||
; X86-NEXT: subw {{[0-9]+}}(%esp), %ax
|
||||
; X86-NEXT: cmovbl %ecx, %eax
|
||||
; X86-NEXT: # kill: def $ax killed $ax killed $eax
|
||||
; X86-NEXT: retl
|
||||
;
|
||||
; X64-LABEL: func16:
|
||||
; X64: # %bb.0:
|
||||
; X64-NEXT: xorl %eax, %eax
|
||||
; X64-NEXT: subw %si, %di
|
||||
; X64-NEXT: cmovael %edi, %eax
|
||||
; X64-NEXT: # kill: def $ax killed $ax killed $eax
|
||||
; X64-NEXT: retq
|
||||
%tmp = call i16 @llvm.usub.sat.i16(i16 %x, i16 %y)
|
||||
ret i16 %tmp
|
||||
}
|
||||
|
||||
define i8 @func8(i8 %x, i8 %y) nounwind {
|
||||
; X86-LABEL: func8:
|
||||
; X86: # %bb.0:
|
||||
; X86-NEXT: movb {{[0-9]+}}(%esp), %al
|
||||
; X86-NEXT: xorl %ecx, %ecx
|
||||
; X86-NEXT: subb {{[0-9]+}}(%esp), %al
|
||||
; X86-NEXT: movzbl %al, %eax
|
||||
; X86-NEXT: cmovbl %ecx, %eax
|
||||
; X86-NEXT: # kill: def $al killed $al killed $eax
|
||||
; X86-NEXT: retl
|
||||
;
|
||||
; X64-LABEL: func8:
|
||||
; X64: # %bb.0:
|
||||
; X64-NEXT: xorl %ecx, %ecx
|
||||
; X64-NEXT: subb %sil, %dil
|
||||
; X64-NEXT: movzbl %dil, %eax
|
||||
; X64-NEXT: cmovbl %ecx, %eax
|
||||
; X64-NEXT: # kill: def $al killed $al killed $eax
|
||||
; X64-NEXT: retq
|
||||
%tmp = call i8 @llvm.usub.sat.i8(i8 %x, i8 %y)
|
||||
ret i8 %tmp
|
||||
}
|
||||
|
||||
define i4 @func3(i4 %x, i4 %y) nounwind {
|
||||
; X86-LABEL: func3:
|
||||
; X86: # %bb.0:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user