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[SLP] Fix regression in broadcasts caused by operand reordering patch D59973.
This patch fixes a regression caused by the operand reordering refactoring patch https://reviews.llvm.org/D59973 . The fix changes the strategy to Splat instead of Opcode, if broadcast opportunities are found. Please see the lit test for some examples. Committed on behalf of @vporpo (Vasileios Porpodas) Differential Revision: https://reviews.llvm.org/D62427 llvm-svn: 362613
This commit is contained in:
Dinar Temirbulatov
parent
18e4404610
commit
ed700abffd
@ -917,6 +917,32 @@ public:
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/// Clears the data.
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void clear() { OpsVec.clear(); }
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/// \Returns true if there are enough operands identical to \p Op to fill
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/// the whole vector.
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/// Note: This modifies the 'IsUsed' flag, so a cleanUsed() must follow.
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bool shouldBroadcast(Value *Op, unsigned OpIdx, unsigned Lane) {
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bool OpAPO = getData(OpIdx, Lane).APO;
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for (unsigned Ln = 0, Lns = getNumLanes(); Ln != Lns; ++Ln) {
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if (Ln == Lane)
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continue;
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// This is set to true if we found a candidate for broadcast at Lane.
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bool FoundCandidate = false;
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for (unsigned OpI = 0, OpE = getNumOperands(); OpI != OpE; ++OpI) {
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OperandData &Data = getData(OpI, Ln);
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if (Data.APO != OpAPO || Data.IsUsed)
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continue;
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if (Data.V == Op) {
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FoundCandidate = true;
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Data.IsUsed = true;
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break;
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}
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}
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if (!FoundCandidate)
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return false;
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}
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return true;
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}
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public:
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/// Initialize with all the operands of the instruction vector \p RootVL.
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VLOperands(ArrayRef<Value *> RootVL, const DataLayout &DL,
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@ -971,8 +997,13 @@ public:
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// side.
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if (isa<LoadInst>(OpLane0))
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ReorderingModes[OpIdx] = ReorderingMode::Load;
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else if (isa<Instruction>(OpLane0))
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ReorderingModes[OpIdx] = ReorderingMode::Opcode;
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else if (isa<Instruction>(OpLane0)) {
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// Check if OpLane0 should be broadcast.
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if (shouldBroadcast(OpLane0, OpIdx, FirstLane))
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ReorderingModes[OpIdx] = ReorderingMode::Splat;
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else
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ReorderingModes[OpIdx] = ReorderingMode::Opcode;
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}
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else if (isa<Constant>(OpLane0))
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ReorderingModes[OpIdx] = ReorderingMode::Constant;
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else if (isa<Argument>(OpLane0))
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@ -990,9 +1021,8 @@ public:
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for (int Pass = 0; Pass != 2; ++Pass) {
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// Skip the second pass if the first pass did not fail.
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bool StrategyFailed = false;
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// Mark the operand data as free to use for all but the first pass.
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if (Pass > 0)
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clearUsed();
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// Mark all operand data as free to use.
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clearUsed();
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// We keep the original operand order for the FirstLane, so reorder the
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// rest of the lanes. We are visiting the nodes in a circular fashion,
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// using FirstLane as the center point and increasing the radius
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@ -7,29 +7,31 @@
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; S[2] = %v2 + %v1
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; S[3] = %v1 + %v2
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;
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; TODO: We should broadcast %v1 and %v2
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; We broadcast %v1 and %v2
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;
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define void @bcast_vals(i64 *%A, i64 *%B, i64 *%S) {
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; CHECK-LABEL: @bcast_vals(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[A0:%.*]] = load i64, i64* [[A:%.*]], align 8
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; CHECK-NEXT: [[B0:%.*]] = load i64, i64* [[B:%.*]], align 8
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; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A0]], i32 0
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; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B0]], i32 1
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; CHECK-NEXT: [[TMP2:%.*]] = sub <2 x i64> [[TMP1]], <i64 1, i64 1>
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; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <2 x i64> [[TMP2]], <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 1, i32 0>
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; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i64> [[SHUFFLE]], i32 1
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; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i64> undef, i64 [[TMP3]], i32 0
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; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i64> [[SHUFFLE]], i32 0
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; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i64> [[TMP4]], i64 [[TMP5]], i32 1
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; CHECK-NEXT: [[SHUFFLE1:%.*]] = shufflevector <2 x i64> [[TMP6]], <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 1, i32 0>
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; CHECK-NEXT: [[TMP7:%.*]] = add <4 x i64> [[SHUFFLE]], [[SHUFFLE1]]
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; CHECK-NEXT: [[V1:%.*]] = sub i64 [[A0]], 1
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; CHECK-NEXT: [[V2:%.*]] = sub i64 [[B0]], 1
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; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i64> undef, i64 [[V1]], i32 0
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; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i64> [[TMP0]], i64 [[V1]], i32 1
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; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i64> [[TMP1]], i64 [[V1]], i32 2
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; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i64> [[TMP2]], i64 [[V1]], i32 3
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; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i64> undef, i64 [[V2]], i32 0
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; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i64> [[TMP4]], i64 [[V2]], i32 1
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; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i64> [[TMP5]], i64 [[V2]], i32 2
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; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i64> [[TMP6]], i64 [[V2]], i32 3
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; CHECK-NEXT: [[TMP8:%.*]] = add <4 x i64> [[TMP3]], [[TMP7]]
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; CHECK-NEXT: [[IDXS0:%.*]] = getelementptr inbounds i64, i64* [[S:%.*]], i64 0
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; CHECK-NEXT: [[IDXS1:%.*]] = getelementptr inbounds i64, i64* [[S]], i64 1
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; CHECK-NEXT: [[IDXS2:%.*]] = getelementptr inbounds i64, i64* [[S]], i64 2
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; CHECK-NEXT: [[IDXS3:%.*]] = getelementptr inbounds i64, i64* [[S]], i64 3
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; CHECK-NEXT: [[TMP8:%.*]] = bitcast i64* [[IDXS0]] to <4 x i64>*
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; CHECK-NEXT: store <4 x i64> [[TMP7]], <4 x i64>* [[TMP8]], align 8
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; CHECK-NEXT: [[TMP9:%.*]] = bitcast i64* [[IDXS0]] to <4 x i64>*
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; CHECK-NEXT: store <4 x i64> [[TMP8]], <4 x i64>* [[TMP9]], align 8
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; CHECK-NEXT: ret void
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;
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entry:
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@ -61,7 +63,8 @@ entry:
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; S[2] = %v5 + %v1
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; S[3] = %v1 + %v4
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;
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; TODO: We should broadcast %v1.
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; We broadcast %v1.
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;
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define void @bcast_vals2(i16 *%A, i16 *%B, i16 *%C, i16 *%D, i16 *%E, i32 *%S) {
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; CHECK-LABEL: @bcast_vals2(
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@ -72,25 +75,22 @@ define void @bcast_vals2(i16 *%A, i16 *%B, i16 *%C, i16 *%D, i16 *%E, i32 *%S) {
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; CHECK-NEXT: [[D0:%.*]] = load i16, i16* [[D:%.*]], align 8
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; CHECK-NEXT: [[E0:%.*]] = load i16, i16* [[E:%.*]], align 8
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; CHECK-NEXT: [[V1:%.*]] = sext i16 [[A0]] to i32
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; CHECK-NEXT: [[V2:%.*]] = sext i16 [[B0]] to i32
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; CHECK-NEXT: [[V3:%.*]] = sext i16 [[C0]] to i32
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; CHECK-NEXT: [[V4:%.*]] = sext i16 [[D0]] to i32
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; CHECK-NEXT: [[V5:%.*]] = sext i16 [[E0]] to i32
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; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> undef, i32 [[V1]], i32 0
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; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[V3]], i32 1
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; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[V5]], i32 2
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; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[V1]], i32 3
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; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> undef, i32 [[V2]], i32 0
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; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> [[TMP4]], i32 [[V1]], i32 1
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; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[V1]], i32 2
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; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> [[TMP6]], i32 [[V4]], i32 3
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; CHECK-NEXT: [[TMP8:%.*]] = add <4 x i32> [[TMP3]], [[TMP7]]
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; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i16> undef, i16 [[B0]], i32 0
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; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> [[TMP0]], i16 [[C0]], i32 1
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; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i16> [[TMP1]], i16 [[E0]], i32 2
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; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i16> [[TMP2]], i16 [[D0]], i32 3
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; CHECK-NEXT: [[TMP4:%.*]] = sext <4 x i16> [[TMP3]] to <4 x i32>
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; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> undef, i32 [[V1]], i32 0
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; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[V1]], i32 1
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; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> [[TMP6]], i32 [[V1]], i32 2
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; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x i32> [[TMP7]], i32 [[V1]], i32 3
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; CHECK-NEXT: [[TMP9:%.*]] = add <4 x i32> [[TMP8]], [[TMP4]]
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; CHECK-NEXT: [[IDXS0:%.*]] = getelementptr inbounds i32, i32* [[S:%.*]], i64 0
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; CHECK-NEXT: [[IDXS1:%.*]] = getelementptr inbounds i32, i32* [[S]], i64 1
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; CHECK-NEXT: [[IDXS2:%.*]] = getelementptr inbounds i32, i32* [[S]], i64 2
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; CHECK-NEXT: [[IDXS3:%.*]] = getelementptr inbounds i32, i32* [[S]], i64 3
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; CHECK-NEXT: [[TMP9:%.*]] = bitcast i32* [[IDXS0]] to <4 x i32>*
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; CHECK-NEXT: store <4 x i32> [[TMP8]], <4 x i32>* [[TMP9]], align 8
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; CHECK-NEXT: [[TMP10:%.*]] = bitcast i32* [[IDXS0]] to <4 x i32>*
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; CHECK-NEXT: store <4 x i32> [[TMP9]], <4 x i32>* [[TMP10]], align 8
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; CHECK-NEXT: ret void
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;
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entry:
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