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[X86][AMX] Lower tile copy instruction.
Since there is no tile copy instruction, we need to store tile register to stack and load from stack to another tile register. We need extra GR to hold the stride, and we need stack slot to hold the tile data register. We would run this pass after copy propagation, so that we don't miss copy optimization. And we would run this pass before prolog/epilog insertion, so that we can allocate stack slot. Differential Revision: https://reviews.llvm.org/D97112
This commit is contained in:
Luo, Yuanke
parent
771be1b79d
commit
ede5e5d465
@ -32,6 +32,7 @@ set(sources
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X86CmovConversion.cpp
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X86DomainReassignment.cpp
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X86DiscriminateMemOps.cpp
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X86LowerTileCopy.cpp
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X86LowerAMXType.cpp
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X86TileConfig.cpp
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X86PreTileConfig.cpp
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@ -76,10 +76,15 @@ FunctionPass *createX86FlagsCopyLoweringPass();
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/// Return a pass that expands WinAlloca pseudo-instructions.
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FunctionPass *createX86WinAllocaExpander();
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/// Return a pass that config the tile registers.
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FunctionPass *createX86TileConfigPass();
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/// Return a pass that insert pseudo tile config instruction.
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FunctionPass *createX86PreTileConfigPass();
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/// Return a pass that lower the tile copy instruction.
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FunctionPass *createX86LowerTileCopyPass();
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/// Return a pass that inserts int3 at the end of the function if it ends with a
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/// CALL instruction. The pass does the same for each funclet as well. This
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/// ensures that the open interval of function start and end PCs contains all
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@ -169,6 +174,7 @@ void initializeX86SpeculativeExecutionSideEffectSuppressionPass(PassRegistry &);
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void initializeX86PreTileConfigPass(PassRegistry &);
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void initializeX86TileConfigPass(PassRegistry &);
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void initializeX86LowerAMXTypeLegacyPassPass(PassRegistry &);
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void initializeX86LowerTileCopyPass(PassRegistry &);
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namespace X86AS {
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enum : unsigned {
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132
lib/Target/X86/X86LowerTileCopy.cpp
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132
lib/Target/X86/X86LowerTileCopy.cpp
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@ -0,0 +1,132 @@
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//===-- X86LowerTileCopy.cpp - Expand Tile Copy Instructions---------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the pass which lower AMX tile copy instructions. Since
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// there is no tile copy instruction, we need store tile register to stack
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// and load from stack to another tile register. We need extra GR to hold
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// the stride, and we need stack slot to hold the tile data register.
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// We would run this pass after copy propagation, so that we don't miss copy
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// optimization. And we would run this pass before prolog/epilog insertion,
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// so that we can allocate stack slot.
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//
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86InstrBuilder.h"
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#include "X86InstrInfo.h"
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#include "X86Subtarget.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/IR/DebugLoc.h"
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#include "llvm/InitializePasses.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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#define DEBUG_TYPE "x86-lower-tile-copy"
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namespace {
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class X86LowerTileCopy : public MachineFunctionPass {
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public:
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static char ID;
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X86LowerTileCopy() : MachineFunctionPass(ID) {}
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void getAnalysisUsage(AnalysisUsage &AU) const override;
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override { return "X86 Lower Tile Copy"; }
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};
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} // namespace
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char X86LowerTileCopy::ID = 0;
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INITIALIZE_PASS_BEGIN(X86LowerTileCopy, "lowertilecopy", "Tile Copy Lowering",
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false, false)
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INITIALIZE_PASS_END(X86LowerTileCopy, "lowertilecopy", "Tile Copy Lowering",
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false, false)
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void X86LowerTileCopy::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesAll();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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FunctionPass *llvm::createX86LowerTileCopyPass() {
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return new X86LowerTileCopy();
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}
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bool X86LowerTileCopy::runOnMachineFunction(MachineFunction &MF) {
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const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
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const X86InstrInfo *TII = ST.getInstrInfo();
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bool Changed = false;
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for (MachineBasicBlock &MBB : MF) {
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for (MachineBasicBlock::iterator MII = MBB.begin(), MIE = MBB.end();
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MII != MIE;) {
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MachineInstr &MI = *MII++;
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if (!MI.isCopy())
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continue;
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MachineOperand &DstMO = MI.getOperand(0);
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MachineOperand &SrcMO = MI.getOperand(1);
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Register SrcReg = SrcMO.getReg();
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Register DstReg = DstMO.getReg();
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if (!X86::TILERegClass.contains(DstReg, SrcReg))
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continue;
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const TargetRegisterInfo *TRI = ST.getRegisterInfo();
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// Allocate stack slot for tile register
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unsigned Size = TRI->getSpillSize(X86::TILERegClass);
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Align Alignment = TRI->getSpillAlign(X86::TILERegClass);
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int TileSS = MF.getFrameInfo().CreateSpillStackObject(Size, Alignment);
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// Allocate stack slot for stride register
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Size = TRI->getSpillSize(X86::GR64RegClass);
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Alignment = TRI->getSpillAlign(X86::GR64RegClass);
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int StrideSS = MF.getFrameInfo().CreateSpillStackObject(Size, Alignment);
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// TODO: Pick a killed regiter to avoid save/reload. There is problem
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// to get live interval in this stage.
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Register GR64Cand = X86::RAX;
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const DebugLoc &DL = MI.getDebugLoc();
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// mov %rax (%sp)
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BuildMI(MBB, MI, DL, TII->get(X86::IMPLICIT_DEF), GR64Cand);
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addFrameReference(BuildMI(MBB, MI, DL, TII->get(X86::MOV64mr)), StrideSS)
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.addReg(GR64Cand);
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// mov 64 %rax
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BuildMI(MBB, MI, DL, TII->get(X86::MOV64ri), GR64Cand).addImm(64);
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// tilestored %tmm, (%sp, %idx)
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unsigned Opc = X86::TILESTORED;
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MachineInstr *NewMI =
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addFrameReference(BuildMI(MBB, MI, DL, TII->get(Opc)), TileSS)
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.addReg(SrcReg, getKillRegState(SrcMO.isKill()));
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MachineOperand &MO = NewMI->getOperand(2);
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MO.setReg(GR64Cand);
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MO.setIsKill(true);
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// tileloadd (%sp, %idx), %tmm
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Opc = X86::TILELOADD;
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NewMI = addFrameReference(BuildMI(MBB, MI, DL, TII->get(Opc), DstReg),
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TileSS);
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// restore %rax
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// mov (%sp) %rax
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addFrameReference(BuildMI(MBB, MI, DL, TII->get(X86::MOV64rm), GR64Cand),
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StrideSS);
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MI.eraseFromParent();
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Changed = true;
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}
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}
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return Changed;
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}
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@ -875,6 +875,12 @@ static ShapeT getTileShape(Register VirtReg, VirtRegMap *VRM,
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default:
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llvm_unreachable("Unexpected machine instruction on tile register!");
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break;
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case X86::COPY: {
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Register SrcReg = MI->getOperand(1).getReg();
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ShapeT Shape = getTileShape(SrcReg, VRM, MRI);
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VRM->assignVirt2Shape(VirtReg, Shape);
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return Shape;
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}
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// We only collect the tile shape that is defined.
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case X86::PTILELOADDV:
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case X86::PTDPBSSDV:
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@ -73,6 +73,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86Target() {
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initializeX86CallFrameOptimizationPass(PR);
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initializeX86CmovConverterPassPass(PR);
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initializeX86TileConfigPass(PR);
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initializeX86LowerTileCopyPass(PR);
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initializeX86ExpandPseudoPass(PR);
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initializeX86ExecutionDomainFixPass(PR);
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initializeX86DomainReassignmentPass(PR);
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@ -508,6 +509,7 @@ void X86PassConfig::addMachineSSAOptimization() {
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}
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void X86PassConfig::addPostRegAlloc() {
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addPass(createX86LowerTileCopyPass());
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addPass(createX86FloatingPointStackifierPass());
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// When -O0 is enabled, the Load Value Injection Hardening pass will fall back
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// to using the Speculative Execution Side Effect Suppression pass for
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181
test/CodeGen/X86/AMX/amx-lower-tile-copy.ll
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181
test/CodeGen/X86/AMX/amx-lower-tile-copy.ll
Normal file
@ -0,0 +1,181 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-int8 -mattr=+avx512f -verify-machineinstrs | FileCheck %s
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define dso_local void @test1(i8 *%buf) nounwind {
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; CHECK-LABEL: test1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pushq %rbp
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; CHECK-NEXT: pushq %r15
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; CHECK-NEXT: pushq %r14
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: subq $4056, %rsp # imm = 0xFD8
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; CHECK-NEXT: vpxord %zmm0, %zmm0, %zmm0
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; CHECK-NEXT: vmovdqu64 %zmm0, {{[0-9]+}}(%rsp)
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; CHECK-NEXT: movb $1, {{[0-9]+}}(%rsp)
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; CHECK-NEXT: movb $8, {{[0-9]+}}(%rsp)
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; CHECK-NEXT: movw $8, {{[0-9]+}}(%rsp)
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; CHECK-NEXT: movb $8, {{[0-9]+}}(%rsp)
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; CHECK-NEXT: movw $8, {{[0-9]+}}(%rsp)
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; CHECK-NEXT: movb $8, {{[0-9]+}}(%rsp)
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; CHECK-NEXT: movw $8, {{[0-9]+}}(%rsp)
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; CHECK-NEXT: movb $8, {{[0-9]+}}(%rsp)
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; CHECK-NEXT: movw $8, {{[0-9]+}}(%rsp)
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; CHECK-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
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; CHECK-NEXT: movl $64, %eax
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; CHECK-NEXT: movw $8, %r14w
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; CHECK-NEXT: tileloadd (%rdi,%rax), %tmm3
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: testb %al, %al
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; CHECK-NEXT: jne .LBB0_3
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; CHECK-NEXT: # %bb.1: # %loop.header.preheader
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; CHECK-NEXT: movq %rdi, %rbx
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; CHECK-NEXT: xorl %ebp, %ebp
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; CHECK-NEXT: movl $32, %r15d
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: .LBB0_2: # %loop.header
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; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: movabsq $64, %rax
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; CHECK-NEXT: tilestored %tmm3, 2048(%rsp,%rax) # 1024-byte Folded Spill
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: callq foo
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; CHECK-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
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; CHECK-NEXT: movabsq $64, %rax
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; CHECK-NEXT: tileloadd 2048(%rsp,%rax), %tmm3 # 1024-byte Folded Reload
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; CHECK-NEXT: tileloadd (%rbx,%r15), %tmm0
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; CHECK-NEXT: tileloadd (%rbx,%r15), %tmm1
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; CHECK-NEXT: # implicit-def: $rax
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; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
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; CHECK-NEXT: movabsq $64, %rax
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; CHECK-NEXT: tilestored %tmm3, 1024(%rsp,%rax) # 1024-byte Folded Spill
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; CHECK-NEXT: tileloadd {{[-0-9]+}}(%r{{[sb]}}p), %tmm2 # 1024-byte Folded Reload
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; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
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; CHECK-NEXT: tdpbssd %tmm1, %tmm0, %tmm2
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; CHECK-NEXT: tilestored %tmm2, (%rbx,%r15)
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; CHECK-NEXT: incl %ebp
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; CHECK-NEXT: cmpw $100, %bp
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; CHECK-NEXT: jl .LBB0_2
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; CHECK-NEXT: .LBB0_3: # %exit
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; CHECK-NEXT: addq $4056, %rsp # imm = 0xFD8
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: popq %r14
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; CHECK-NEXT: popq %r15
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; CHECK-NEXT: popq %rbp
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; CHECK-NEXT: tilerelease
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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entry:
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%t1 = tail call x86_amx @llvm.x86.tileloadd64.internal(i16 8, i16 8, i8* %buf, i64 64)
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br i1 undef, label %loop.header, label %exit
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loop.header:
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%ivphi = phi i16 [0, %entry], [%iv, %loop.latch]
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call void @foo()
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br label %loop.body
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loop.body:
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%t2 = tail call x86_amx @llvm.x86.tileloadd64.internal(i16 8, i16 8, i8* %buf, i64 32)
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%t3 = tail call x86_amx @llvm.x86.tileloadd64.internal(i16 8, i16 8, i8* %buf, i64 32)
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%t4 = tail call x86_amx @llvm.x86.tdpbssd.internal(i16 8, i16 8, i16 8, x86_amx %t1, x86_amx %t2, x86_amx %t3)
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tail call void @llvm.x86.tilestored64.internal(i16 8, i16 8, i8* %buf, i64 32, x86_amx %t4)
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br label %loop.latch
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loop.latch:
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%iv = add i16 %ivphi, 1
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%c = icmp slt i16 %iv, 100
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br i1 %c, label %loop.header, label %exit
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exit:
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ret void
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}
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define dso_local void @test2(i8 *%buf) nounwind {
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; CHECK-LABEL: test2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pushq %rbp
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; CHECK-NEXT: pushq %r15
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; CHECK-NEXT: pushq %r14
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: subq $4056, %rsp # imm = 0xFD8
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; CHECK-NEXT: vpxord %zmm0, %zmm0, %zmm0
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; CHECK-NEXT: vmovdqu64 %zmm0, {{[0-9]+}}(%rsp)
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; CHECK-NEXT: movb $1, {{[0-9]+}}(%rsp)
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; CHECK-NEXT: movb $8, {{[0-9]+}}(%rsp)
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; CHECK-NEXT: movw $8, {{[0-9]+}}(%rsp)
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; CHECK-NEXT: movb $8, {{[0-9]+}}(%rsp)
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; CHECK-NEXT: movw $8, {{[0-9]+}}(%rsp)
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; CHECK-NEXT: movb $8, {{[0-9]+}}(%rsp)
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; CHECK-NEXT: movw $8, {{[0-9]+}}(%rsp)
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; CHECK-NEXT: movb $8, {{[0-9]+}}(%rsp)
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; CHECK-NEXT: movw $8, {{[0-9]+}}(%rsp)
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; CHECK-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
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; CHECK-NEXT: movw $8, %r14w
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; CHECK-NEXT: tilezero %tmm3
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: testb %al, %al
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; CHECK-NEXT: jne .LBB1_3
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; CHECK-NEXT: # %bb.1: # %loop.header.preheader
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; CHECK-NEXT: movq %rdi, %rbx
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; CHECK-NEXT: xorl %ebp, %ebp
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; CHECK-NEXT: movl $32, %r15d
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: .LBB1_2: # %loop.header
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; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: movabsq $64, %rax
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; CHECK-NEXT: tilestored %tmm3, 2048(%rsp,%rax) # 1024-byte Folded Spill
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: callq foo
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; CHECK-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
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; CHECK-NEXT: movabsq $64, %rax
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; CHECK-NEXT: tileloadd 2048(%rsp,%rax), %tmm3 # 1024-byte Folded Reload
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; CHECK-NEXT: tileloadd (%rbx,%r15), %tmm0
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; CHECK-NEXT: tileloadd (%rbx,%r15), %tmm1
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; CHECK-NEXT: # implicit-def: $rax
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; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
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; CHECK-NEXT: movabsq $64, %rax
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; CHECK-NEXT: tilestored %tmm3, 1024(%rsp,%rax) # 1024-byte Folded Spill
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; CHECK-NEXT: tileloadd {{[-0-9]+}}(%r{{[sb]}}p), %tmm2 # 1024-byte Folded Reload
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; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
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; CHECK-NEXT: tdpbssd %tmm1, %tmm0, %tmm2
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; CHECK-NEXT: tilestored %tmm2, (%rbx,%r15)
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; CHECK-NEXT: incl %ebp
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; CHECK-NEXT: cmpw $100, %bp
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; CHECK-NEXT: jl .LBB1_2
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; CHECK-NEXT: .LBB1_3: # %exit
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; CHECK-NEXT: addq $4056, %rsp # imm = 0xFD8
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: popq %r14
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; CHECK-NEXT: popq %r15
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; CHECK-NEXT: popq %rbp
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; CHECK-NEXT: tilerelease
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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entry:
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%t1 = tail call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 8)
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br i1 undef, label %loop.header, label %exit
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loop.header:
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%ivphi = phi i16 [0, %entry], [%iv, %loop.latch]
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call void @foo()
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br label %loop.body
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loop.body:
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%t2 = tail call x86_amx @llvm.x86.tileloadd64.internal(i16 8, i16 8, i8* %buf, i64 32)
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%t3 = tail call x86_amx @llvm.x86.tileloadd64.internal(i16 8, i16 8, i8* %buf, i64 32)
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%t4 = tail call x86_amx @llvm.x86.tdpbssd.internal(i16 8, i16 8, i16 8, x86_amx %t1, x86_amx %t2, x86_amx %t3)
|
||||
tail call void @llvm.x86.tilestored64.internal(i16 8, i16 8, i8* %buf, i64 32, x86_amx %t4)
|
||||
br label %loop.latch
|
||||
|
||||
loop.latch:
|
||||
%iv = add i16 %ivphi, 1
|
||||
%c = icmp slt i16 %iv, 100
|
||||
br i1 %c, label %loop.header, label %exit
|
||||
|
||||
exit:
|
||||
ret void
|
||||
}
|
||||
|
||||
declare dso_local void @foo()
|
||||
declare x86_amx @llvm.x86.tilezero.internal(i16, i16)
|
||||
declare x86_amx @llvm.x86.tileloadd64.internal(i16, i16, i8*, i64)
|
||||
declare x86_amx @llvm.x86.tdpbssd.internal(i16, i16, i16, x86_amx, x86_amx, x86_amx)
|
||||
declare void @llvm.x86.tilestored64.internal(i16, i16, i8*, i64, x86_amx)
|
||||
@ -45,6 +45,7 @@
|
||||
; CHECK-NEXT: Eliminate PHI nodes for register allocation
|
||||
; CHECK-NEXT: Two-Address instruction pass
|
||||
; CHECK-NEXT: Fast Register Allocator
|
||||
; CHECK-NEXT: X86 Lower Tile Copy
|
||||
; CHECK-NEXT: Bundle Machine CFG Edges
|
||||
; CHECK-NEXT: X86 FP Stackifier
|
||||
; CHECK-NEXT: Fixup Statepoint Caller Saved
|
||||
|
||||
@ -145,6 +145,7 @@
|
||||
; CHECK-NEXT: Stack Slot Coloring
|
||||
; CHECK-NEXT: Machine Copy Propagation Pass
|
||||
; CHECK-NEXT: Machine Loop Invariant Code Motion
|
||||
; CHECK-NEXT: X86 Lower Tile Copy
|
||||
; CHECK-NEXT: Bundle Machine CFG Edges
|
||||
; CHECK-NEXT: X86 FP Stackifier
|
||||
; CHECK-NEXT: MachineDominator Tree Construction
|
||||
|
||||
Loading…
Reference in New Issue
Block a user