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[X86] Move HasNOPL to a subtarget feature bit. Plumb MCSubtargetInfo through the MCAsmBackend constructor
After D41349, we can no get a MCSubtargetInfo into the MCAsmBackend constructor. This allows us to get NOPL from a subtarget feature rather than a CPU name blacklist. Differential Revision: https://reviews.llvm.org/D41721 llvm-svn: 322227
This commit is contained in:
Craig Topper
parent
798a2b9e65
commit
ee1a3c5643
@ -67,19 +67,10 @@ public:
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};
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class X86AsmBackend : public MCAsmBackend {
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const StringRef CPU;
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bool HasNopl;
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const uint64_t MaxNopLength;
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const MCSubtargetInfo &STI;
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public:
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X86AsmBackend(const Target &T, StringRef CPU)
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: MCAsmBackend(), CPU(CPU),
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MaxNopLength((CPU == "slm" || CPU == "silvermont") ? 7 : 15) {
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HasNopl = CPU != "generic" && CPU != "i386" && CPU != "i486" &&
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CPU != "i586" && CPU != "pentium" && CPU != "pentium-mmx" &&
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CPU != "i686" && CPU != "k6" && CPU != "k6-2" && CPU != "k6-3" &&
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CPU != "geode" && CPU != "winchip-c6" && CPU != "winchip2" &&
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CPU != "c3" && CPU != "c3-2" && CPU != "lakemont" && CPU != "";
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}
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X86AsmBackend(const Target &T, const MCSubtargetInfo &STI)
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: MCAsmBackend(), STI(STI) {}
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unsigned getNumFixupKinds() const override {
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return X86::NumTargetFixupKinds;
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@ -346,14 +337,15 @@ bool X86AsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
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};
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// This CPU doesn't support long nops. If needed add more.
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// FIXME: Can we get this from the subtarget somehow?
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// FIXME: We could generated something better than plain 0x90.
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if (!HasNopl) {
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if (!STI.getFeatureBits()[X86::FeatureNOPL]) {
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for (uint64_t i = 0; i < Count; ++i)
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OW->write8(0x90);
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return true;
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}
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uint64_t MaxNopLength = STI.getFeatureBits()[X86::ProcIntelSLM] ? 7 : 15;
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// 15 is the longest single nop instruction. Emit as many 15-byte nops as
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// needed, then emit a nop of the remaining length.
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do {
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@ -377,14 +369,15 @@ namespace {
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class ELFX86AsmBackend : public X86AsmBackend {
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public:
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uint8_t OSABI;
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ELFX86AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
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: X86AsmBackend(T, CPU), OSABI(OSABI) {}
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ELFX86AsmBackend(const Target &T, uint8_t OSABI, const MCSubtargetInfo &STI)
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: X86AsmBackend(T, STI), OSABI(OSABI) {}
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};
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class ELFX86_32AsmBackend : public ELFX86AsmBackend {
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public:
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ELFX86_32AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
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: ELFX86AsmBackend(T, OSABI, CPU) {}
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ELFX86_32AsmBackend(const Target &T, uint8_t OSABI,
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const MCSubtargetInfo &STI)
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: ELFX86AsmBackend(T, OSABI, STI) {}
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std::unique_ptr<MCObjectWriter>
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createObjectWriter(raw_pwrite_stream &OS) const override {
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@ -394,8 +387,9 @@ public:
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class ELFX86_X32AsmBackend : public ELFX86AsmBackend {
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public:
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ELFX86_X32AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
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: ELFX86AsmBackend(T, OSABI, CPU) {}
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ELFX86_X32AsmBackend(const Target &T, uint8_t OSABI,
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const MCSubtargetInfo &STI)
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: ELFX86AsmBackend(T, OSABI, STI) {}
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std::unique_ptr<MCObjectWriter>
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createObjectWriter(raw_pwrite_stream &OS) const override {
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@ -406,8 +400,9 @@ public:
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class ELFX86_IAMCUAsmBackend : public ELFX86AsmBackend {
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public:
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ELFX86_IAMCUAsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
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: ELFX86AsmBackend(T, OSABI, CPU) {}
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ELFX86_IAMCUAsmBackend(const Target &T, uint8_t OSABI,
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const MCSubtargetInfo &STI)
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: ELFX86AsmBackend(T, OSABI, STI) {}
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std::unique_ptr<MCObjectWriter>
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createObjectWriter(raw_pwrite_stream &OS) const override {
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@ -418,8 +413,9 @@ public:
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class ELFX86_64AsmBackend : public ELFX86AsmBackend {
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public:
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ELFX86_64AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
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: ELFX86AsmBackend(T, OSABI, CPU) {}
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ELFX86_64AsmBackend(const Target &T, uint8_t OSABI,
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const MCSubtargetInfo &STI)
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: ELFX86AsmBackend(T, OSABI, STI) {}
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std::unique_ptr<MCObjectWriter>
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createObjectWriter(raw_pwrite_stream &OS) const override {
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@ -431,8 +427,9 @@ class WindowsX86AsmBackend : public X86AsmBackend {
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bool Is64Bit;
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public:
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WindowsX86AsmBackend(const Target &T, bool is64Bit, StringRef CPU)
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: X86AsmBackend(T, CPU)
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WindowsX86AsmBackend(const Target &T, bool is64Bit,
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const MCSubtargetInfo &STI)
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: X86AsmBackend(T, STI)
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, Is64Bit(is64Bit) {
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}
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@ -790,9 +787,9 @@ private:
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}
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public:
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DarwinX86AsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef CPU,
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bool Is64Bit)
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: X86AsmBackend(T, CPU), MRI(MRI), Is64Bit(Is64Bit) {
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DarwinX86AsmBackend(const Target &T, const MCRegisterInfo &MRI,
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const MCSubtargetInfo &STI, bool Is64Bit)
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: X86AsmBackend(T, STI), MRI(MRI), Is64Bit(Is64Bit) {
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memset(SavedRegs, 0, sizeof(SavedRegs));
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OffsetSize = Is64Bit ? 8 : 4;
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MoveInstrSize = Is64Bit ? 3 : 2;
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@ -803,8 +800,8 @@ public:
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class DarwinX86_32AsmBackend : public DarwinX86AsmBackend {
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public:
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DarwinX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI,
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StringRef CPU)
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: DarwinX86AsmBackend(T, MRI, CPU, false) {}
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const MCSubtargetInfo &STI)
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: DarwinX86AsmBackend(T, MRI, STI, false) {}
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std::unique_ptr<MCObjectWriter>
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createObjectWriter(raw_pwrite_stream &OS) const override {
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@ -824,8 +821,8 @@ class DarwinX86_64AsmBackend : public DarwinX86AsmBackend {
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const MachO::CPUSubTypeX86 Subtype;
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public:
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DarwinX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI,
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StringRef CPU, MachO::CPUSubTypeX86 st)
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: DarwinX86AsmBackend(T, MRI, CPU, true), Subtype(st) {}
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const MCSubtargetInfo &STI, MachO::CPUSubTypeX86 st)
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: DarwinX86AsmBackend(T, MRI, STI, true), Subtype(st) {}
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std::unique_ptr<MCObjectWriter>
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createObjectWriter(raw_pwrite_stream &OS) const override {
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@ -847,19 +844,18 @@ MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
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const MCRegisterInfo &MRI,
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const MCTargetOptions &Options) {
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const Triple &TheTriple = STI.getTargetTriple();
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StringRef CPU = STI.getCPU();
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if (TheTriple.isOSBinFormatMachO())
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return new DarwinX86_32AsmBackend(T, MRI, CPU);
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return new DarwinX86_32AsmBackend(T, MRI, STI);
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if (TheTriple.isOSWindows() && TheTriple.isOSBinFormatCOFF())
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return new WindowsX86AsmBackend(T, false, CPU);
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return new WindowsX86AsmBackend(T, false, STI);
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uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
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if (TheTriple.isOSIAMCU())
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return new ELFX86_IAMCUAsmBackend(T, OSABI, CPU);
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return new ELFX86_IAMCUAsmBackend(T, OSABI, STI);
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return new ELFX86_32AsmBackend(T, OSABI, CPU);
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return new ELFX86_32AsmBackend(T, OSABI, STI);
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}
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MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
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@ -867,21 +863,20 @@ MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
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const MCRegisterInfo &MRI,
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const MCTargetOptions &Options) {
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const Triple &TheTriple = STI.getTargetTriple();
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StringRef CPU = STI.getCPU();
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if (TheTriple.isOSBinFormatMachO()) {
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MachO::CPUSubTypeX86 CS =
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StringSwitch<MachO::CPUSubTypeX86>(TheTriple.getArchName())
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.Case("x86_64h", MachO::CPU_SUBTYPE_X86_64_H)
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.Default(MachO::CPU_SUBTYPE_X86_64_ALL);
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return new DarwinX86_64AsmBackend(T, MRI, CPU, CS);
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return new DarwinX86_64AsmBackend(T, MRI, STI, CS);
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}
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if (TheTriple.isOSWindows() && TheTriple.isOSBinFormatCOFF())
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return new WindowsX86AsmBackend(T, true, CPU);
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return new WindowsX86AsmBackend(T, true, STI);
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uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
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if (TheTriple.getEnvironment() == Triple::GNUX32)
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return new ELFX86_X32AsmBackend(T, OSABI, CPU);
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return new ELFX86_64AsmBackend(T, OSABI, CPU);
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return new ELFX86_X32AsmBackend(T, OSABI, STI);
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return new ELFX86_64AsmBackend(T, OSABI, STI);
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}
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@ -34,6 +34,9 @@ def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
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def FeatureX87 : SubtargetFeature<"x87","HasX87", "true",
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"Enable X87 float instructions">;
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def FeatureNOPL : SubtargetFeature<"nopl", "HasNOPL", "true",
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"Enable NOPL instruction">;
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def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true",
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"Enable conditional move instructions">;
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@ -390,16 +393,16 @@ def : Proc<"i586", [FeatureX87, FeatureSlowUAMem16]>;
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def : Proc<"pentium", [FeatureX87, FeatureSlowUAMem16]>;
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def : Proc<"pentium-mmx", [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
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foreach P = ["i686", "pentiumpro"] in {
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def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMOV]>;
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}
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def : Proc<"i686", [FeatureX87, FeatureSlowUAMem16, FeatureCMOV]>;
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def : Proc<"pentiumpro", [FeatureX87, FeatureSlowUAMem16, FeatureCMOV,
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FeatureNOPL]>;
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def : Proc<"pentium2", [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
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FeatureCMOV, FeatureFXSR]>;
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FeatureCMOV, FeatureFXSR, FeatureNOPL]>;
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foreach P = ["pentium3", "pentium3m"] in {
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def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE1,
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FeatureFXSR]>;
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FeatureFXSR, FeatureNOPL]>;
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}
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// Enable the PostRAScheduler for SSE2 and SSE3 class cpus.
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@ -414,12 +417,12 @@ foreach P = ["pentium3", "pentium3m"] in {
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def : ProcessorModel<"pentium-m", GenericPostRAModel,
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[FeatureX87, FeatureSlowUAMem16, FeatureMMX,
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FeatureSSE2, FeatureFXSR]>;
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FeatureSSE2, FeatureFXSR, FeatureNOPL]>;
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foreach P = ["pentium4", "pentium4m"] in {
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def : ProcessorModel<P, GenericPostRAModel,
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[FeatureX87, FeatureSlowUAMem16, FeatureMMX,
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FeatureSSE2, FeatureFXSR]>;
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FeatureSSE2, FeatureFXSR, FeatureNOPL]>;
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}
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// Intel Quark.
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@ -428,18 +431,19 @@ def : Proc<"lakemont", []>;
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// Intel Core Duo.
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def : ProcessorModel<"yonah", SandyBridgeModel,
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[FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3,
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FeatureFXSR]>;
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FeatureFXSR, FeatureNOPL]>;
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// NetBurst.
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def : ProcessorModel<"prescott", GenericPostRAModel,
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[FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3,
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FeatureFXSR]>;
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FeatureFXSR, FeatureNOPL]>;
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def : ProcessorModel<"nocona", GenericPostRAModel, [
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FeatureX87,
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FeatureSlowUAMem16,
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FeatureMMX,
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FeatureSSE3,
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FeatureFXSR,
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FeatureNOPL,
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FeatureCMPXCHG16B
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]>;
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@ -450,6 +454,7 @@ def : ProcessorModel<"core2", SandyBridgeModel, [
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FeatureMMX,
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FeatureSSSE3,
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FeatureFXSR,
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FeatureNOPL,
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FeatureCMPXCHG16B,
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FeatureLAHFSAHF,
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FeatureMacroFusion
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@ -460,6 +465,7 @@ def : ProcessorModel<"penryn", SandyBridgeModel, [
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FeatureMMX,
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FeatureSSE41,
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FeatureFXSR,
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FeatureNOPL,
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FeatureCMPXCHG16B,
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FeatureLAHFSAHF,
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FeatureMacroFusion
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@ -473,6 +479,7 @@ class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
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FeatureMMX,
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FeatureSSSE3,
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FeatureFXSR,
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FeatureNOPL,
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FeatureCMPXCHG16B,
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FeatureMOVBE,
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FeatureLEAForSP,
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@ -492,6 +499,7 @@ class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
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FeatureMMX,
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FeatureSSE42,
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FeatureFXSR,
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FeatureNOPL,
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FeatureCMPXCHG16B,
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FeatureMOVBE,
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FeaturePOPCNT,
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@ -514,6 +522,7 @@ class GoldmontProc<string Name> : ProcessorModel<Name, SLMModel, [
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FeatureMMX,
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FeatureSSE42,
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FeatureFXSR,
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FeatureNOPL,
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FeatureCMPXCHG16B,
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FeatureMOVBE,
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FeaturePOPCNT,
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@ -543,6 +552,7 @@ class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
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FeatureMMX,
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FeatureSSE42,
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FeatureFXSR,
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FeatureNOPL,
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FeatureCMPXCHG16B,
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FeaturePOPCNT,
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FeatureLAHFSAHF,
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@ -558,6 +568,7 @@ class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
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FeatureMMX,
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FeatureSSE42,
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FeatureFXSR,
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FeatureNOPL,
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FeatureCMPXCHG16B,
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FeaturePOPCNT,
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FeatureAES,
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@ -584,6 +595,7 @@ def SNBFeatures : ProcessorFeatures<[], [
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FeatureMMX,
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FeatureAVX,
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FeatureFXSR,
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FeatureNOPL,
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FeatureCMPXCHG16B,
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FeaturePOPCNT,
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FeatureAES,
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@ -757,27 +769,28 @@ def : Proc<"k6-2", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
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def : Proc<"k6-3", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
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foreach P = ["athlon", "athlon-tbird"] in {
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def : Proc<P, [FeatureX87, FeatureSlowUAMem16, Feature3DNowA, FeatureSlowSHLD]>;
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def : Proc<P, [FeatureX87, FeatureSlowUAMem16, Feature3DNowA,
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FeatureNOPL, FeatureSlowSHLD]>;
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}
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foreach P = ["athlon-4", "athlon-xp", "athlon-mp"] in {
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def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureSSE1,
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Feature3DNowA, FeatureFXSR, FeatureSlowSHLD]>;
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Feature3DNowA, FeatureFXSR, FeatureNOPL, FeatureSlowSHLD]>;
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}
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foreach P = ["k8", "opteron", "athlon64", "athlon-fx"] in {
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def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
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FeatureFXSR, Feature64Bit, FeatureSlowSHLD]>;
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FeatureFXSR, FeatureNOPL, Feature64Bit, FeatureSlowSHLD]>;
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}
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foreach P = ["k8-sse3", "opteron-sse3", "athlon64-sse3"] in {
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def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureSSE3, Feature3DNowA,
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FeatureFXSR, FeatureCMPXCHG16B, FeatureSlowSHLD]>;
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FeatureFXSR, FeatureNOPL, FeatureCMPXCHG16B, FeatureSlowSHLD]>;
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}
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foreach P = ["amdfam10", "barcelona"] in {
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def : Proc<P, [FeatureX87, FeatureSSE4A, Feature3DNowA, FeatureFXSR,
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FeatureCMPXCHG16B, FeatureLZCNT, FeaturePOPCNT,
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FeatureNOPL, FeatureCMPXCHG16B, FeatureLZCNT, FeaturePOPCNT,
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FeatureSlowSHLD, FeatureLAHFSAHF]>;
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}
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@ -788,6 +801,7 @@ def : Proc<"btver1", [
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FeatureSSSE3,
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FeatureSSE4A,
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FeatureFXSR,
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FeatureNOPL,
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FeatureCMPXCHG16B,
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FeaturePRFCHW,
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FeatureLZCNT,
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@ -802,6 +816,7 @@ def : ProcessorModel<"btver2", BtVer2Model, [
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FeatureMMX,
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FeatureAVX,
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FeatureFXSR,
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FeatureNOPL,
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FeatureSSE4A,
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FeatureCMPXCHG16B,
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FeaturePRFCHW,
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@ -832,6 +847,7 @@ def : Proc<"bdver1", [
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FeatureMMX,
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FeatureAVX,
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FeatureFXSR,
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FeatureNOPL,
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FeatureSSE4A,
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FeatureLZCNT,
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FeaturePOPCNT,
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@ -853,6 +869,7 @@ def : Proc<"bdver2", [
|
||||
FeatureMMX,
|
||||
FeatureAVX,
|
||||
FeatureFXSR,
|
||||
FeatureNOPL,
|
||||
FeatureSSE4A,
|
||||
FeatureF16C,
|
||||
FeatureLZCNT,
|
||||
@ -879,6 +896,7 @@ def : Proc<"bdver3", [
|
||||
FeatureMMX,
|
||||
FeatureAVX,
|
||||
FeatureFXSR,
|
||||
FeatureNOPL,
|
||||
FeatureSSE4A,
|
||||
FeatureF16C,
|
||||
FeatureLZCNT,
|
||||
@ -901,6 +919,7 @@ def : Proc<"bdver4", [
|
||||
FeatureMMX,
|
||||
FeatureAVX2,
|
||||
FeatureFXSR,
|
||||
FeatureNOPL,
|
||||
FeatureXOP,
|
||||
FeatureFMA4,
|
||||
FeatureCMPXCHG16B,
|
||||
@ -938,6 +957,7 @@ def: ProcessorModel<"znver1", Znver1Model, [
|
||||
FeatureFMA,
|
||||
FeatureFSGSBase,
|
||||
FeatureFXSR,
|
||||
FeatureNOPL,
|
||||
FeatureFastLZCNT,
|
||||
FeatureLAHFSAHF,
|
||||
FeatureLZCNT,
|
||||
@ -982,6 +1002,7 @@ def : ProcessorModel<"x86-64", SandyBridgeModel, [
|
||||
FeatureMMX,
|
||||
FeatureSSE2,
|
||||
FeatureFXSR,
|
||||
FeatureNOPL,
|
||||
Feature64Bit,
|
||||
FeatureSlow3OpsLEA,
|
||||
FeatureSlowIncDec,
|
||||
|
||||
@ -260,6 +260,7 @@ void X86Subtarget::initializeEnvironment() {
|
||||
X86SSELevel = NoSSE;
|
||||
X863DNowLevel = NoThreeDNow;
|
||||
HasX87 = false;
|
||||
HasNOPL = false;
|
||||
HasCMov = false;
|
||||
HasX86_64 = false;
|
||||
HasPOPCNT = false;
|
||||
|
||||
@ -92,6 +92,10 @@ protected:
|
||||
/// True if the processor supports X87 instructions.
|
||||
bool HasX87;
|
||||
|
||||
/// True if this processor has NOPL instruction
|
||||
/// (generally pentium pro+).
|
||||
bool HasNOPL;
|
||||
|
||||
/// True if this processor has conditional move instructions
|
||||
/// (generally pentium pro+).
|
||||
bool HasCMov;
|
||||
@ -469,6 +473,7 @@ public:
|
||||
void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
|
||||
|
||||
bool hasX87() const { return HasX87; }
|
||||
bool hasNOPL() const { return HasNOPL; }
|
||||
bool hasCMov() const { return HasCMov; }
|
||||
bool hasSSE1() const { return X86SSELevel >= SSE1; }
|
||||
bool hasSSE2() const { return X86SSELevel >= SSE2; }
|
||||
|
||||
Loading…
Reference in New Issue
Block a user