From ee3ca03932ace6939c3aa3deb9a1af50a6e71c6a Mon Sep 17 00:00:00 2001 From: Colin LeMahieu Date: Fri, 30 Jan 2015 21:14:00 +0000 Subject: [PATCH] [Hexagon] Adding vector permutation instructions and tests. llvm-svn: 227612 --- lib/Target/Hexagon/HexagonInstrInfo.td | 80 +++++++++++++++++++ lib/Target/Hexagon/HexagonInstrInfoV3.td | 5 ++ test/MC/Disassembler/Hexagon/xtype_perm.txt | 88 ++++++++++++++++++++- 3 files changed, 172 insertions(+), 1 deletion(-) diff --git a/lib/Target/Hexagon/HexagonInstrInfo.td b/lib/Target/Hexagon/HexagonInstrInfo.td index b017efcae27..7e5fa0fff48 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/lib/Target/Hexagon/HexagonInstrInfo.td @@ -3866,12 +3866,42 @@ let hasNewValue = 1 in class T_S2op_1_ii MajOp, bits<3> MinOp, bit isSat = 0> : T_S2op_1 ; +// Vector sign/zero extend +let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 0 in { + def S2_vsxtbh : T_S2op_1_di <"vsxtbh", 0b00, 0b000>; + def S2_vsxthw : T_S2op_1_di <"vsxthw", 0b00, 0b100>; + def S2_vzxtbh : T_S2op_1_di <"vzxtbh", 0b00, 0b010>; + def S2_vzxthw : T_S2op_1_di <"vzxthw", 0b00, 0b110>; +} + +// Vector splat bytes/halfwords +let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 0 in { + def S2_vsplatrb : T_S2op_1_ii <"vsplatb", 0b01, 0b111>; + def S2_vsplatrh : T_S2op_1_di <"vsplath", 0b01, 0b010>; +} + // Sign extend word to doubleword let isCodeGenOnly = 0 in def A2_sxtw : T_S2op_1_di <"sxtw", 0b01, 0b000>; def: Pat <(i64 (sext I32:$src)), (A2_sxtw I32:$src)>; +// Vector saturate and pack +let Defs = [USR_OVF], isCodeGenOnly = 0 in { + def S2_svsathb : T_S2op_1_ii <"vsathb", 0b10, 0b000>; + def S2_svsathub : T_S2op_1_ii <"vsathub", 0b10, 0b010>; + def S2_vsathb : T_S2op_1_id <"vsathb", 0b00, 0b110>; + def S2_vsathub : T_S2op_1_id <"vsathub", 0b00, 0b000>; + def S2_vsatwh : T_S2op_1_id <"vsatwh", 0b00, 0b010>; + def S2_vsatwuh : T_S2op_1_id <"vsatwuh", 0b00, 0b100>; +} + +// Vector truncate +let isCodeGenOnly = 0 in { +def S2_vtrunohb : T_S2op_1_id <"vtrunohb", 0b10, 0b000>; +def S2_vtrunehb : T_S2op_1_id <"vtrunehb", 0b10, 0b010>; +} + // Swizzle the bytes of a word let isCodeGenOnly = 0 in def A2_swiz : T_S2op_1_ii <"swiz", 0b10, 0b111>; @@ -3887,6 +3917,12 @@ let Defs = [USR_OVF], isCodeGenOnly = 0 in { } let Itinerary = S_2op_tc_2_SLOT23, isCodeGenOnly = 0 in { + // Vector round and pack + def S2_vrndpackwh : T_S2op_1_id <"vrndwh", 0b10, 0b100>; + + let Defs = [USR_OVF] in + def S2_vrndpackwhs : T_S2op_1_id <"vrndwh", 0b10, 0b110, 1>; + // Bit reverse def S2_brev : T_S2op_1_ii <"brev", 0b01, 0b110>; @@ -4007,6 +4043,14 @@ def S2_deinterleave : T_S2op_3 <"deinterleave", 0b11, 0b100>; let isCodeGenOnly = 0 in def A2_vconj : T_S2op_3 <"vconj", 0b10, 0b111, 1>; +// Vector saturate without pack +let isCodeGenOnly = 0 in { +def S2_vsathb_nopack : T_S2op_3 <"vsathb", 0b00, 0b111>; +def S2_vsathub_nopack : T_S2op_3 <"vsathub", 0b00, 0b100>; +def S2_vsatwh_nopack : T_S2op_3 <"vsatwh", 0b00, 0b110>; +def S2_vsatwuh_nopack : T_S2op_3 <"vsatwuh", 0b00, 0b101>; +} + // Vector absolute value halfwords with and without saturation // Rdd64=vabsh(Rss64)[:sat] let isCodeGenOnly = 0 in { @@ -5573,6 +5617,16 @@ class T_S3op_64 MajOp, bits<3> MinOp, bit SwapOps, : T_S3op_1 ; +let Itinerary = S_3op_tc_1_SLOT23, isCodeGenOnly = 0 in { + def S2_shuffeb : T_S3op_64 < "shuffeb", 0b00, 0b010, 0>; + def S2_shuffeh : T_S3op_64 < "shuffeh", 0b00, 0b110, 0>; + def S2_shuffob : T_S3op_64 < "shuffob", 0b00, 0b100, 1>; + def S2_shuffoh : T_S3op_64 < "shuffoh", 0b10, 0b000, 1>; + + def S2_vtrunewh : T_S3op_64 < "vtrunewh", 0b10, 0b010, 0>; + def S2_vtrunowh : T_S3op_64 < "vtrunowh", 0b10, 0b100, 0>; +} + let isCodeGenOnly = 0 in def S2_lfsp : T_S3op_64 < "lfs", 0b10, 0b110, 0>; @@ -5702,6 +5756,32 @@ class T_S3op_8 MinOp, bit isSat, bit isRnd, bit hasShift, b let Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23, isCodeGenOnly = 0 in def S2_vcrotate : T_S3op_shiftVect < "vcrotate", 0b11, 0b00>; +let hasSideEffects = 0 in +class T_S3op_7 + : SInst <(outs DoubleRegs:$Rdd), + (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, u3Imm:$u3), + "$Rdd = "#mnemonic#"($Rss, $Rtt, #$u3)" , + [], "", S_3op_tc_1_SLOT23 > { + bits<5> Rdd; + bits<5> Rss; + bits<5> Rtt; + bits<3> u3; + + let IClass = 0b1100; + + let Inst{27-24} = 0b0000; + let Inst{23} = MajOp; + let Inst{20-16} = !if(MajOp, Rss, Rtt); + let Inst{12-8} = !if(MajOp, Rtt, Rss); + let Inst{7-5} = u3; + let Inst{4-0} = Rdd; + } + +let isCodeGenOnly = 0 in { +def S2_valignib : T_S3op_7 < "valignb", 0>; +def S2_vspliceib : T_S3op_7 < "vspliceb", 1>; +} + //===----------------------------------------------------------------------===// // Template class for 'insert bitfield' instructions //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/HexagonInstrInfoV3.td b/lib/Target/Hexagon/HexagonInstrInfoV3.td index f363b9a2d4a..0f2fd84cd45 100644 --- a/lib/Target/Hexagon/HexagonInstrInfoV3.td +++ b/lib/Target/Hexagon/HexagonInstrInfoV3.td @@ -254,3 +254,8 @@ let isCodeGenOnly = 0 in { def M2_vrcmpys_s1rp_h : T_MType_vrcmpy <"vrcmpys", 0b101, 0b110, 1>; def M2_vrcmpys_s1rp_l : T_MType_vrcmpy <"vrcmpys", 0b101, 0b111, 0>; } + +// S2_cabacdecbin: Cabac decode bin. +let Defs = [P0], isPredicateLate = 1, Itinerary = S_3op_tc_1_SLOT23, + isCodeGenOnly = 0 in +def S2_cabacdecbin : T_S3op_64 < "decbin", 0b11, 0b110, 0>; diff --git a/test/MC/Disassembler/Hexagon/xtype_perm.txt b/test/MC/Disassembler/Hexagon/xtype_perm.txt index 7267e71b18a..91d2fc5ae69 100644 --- a/test/MC/Disassembler/Hexagon/xtype_perm.txt +++ b/test/MC/Disassembler/Hexagon/xtype_perm.txt @@ -1,5 +1,11 @@ -# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple=hexagon -disassemble < %s | FileCheck %s +# Hexagon Programmer's Reference Manual 11.10.6 XTYPE/PERM +# CABAC decode bin +0xd0 0xde 0xd4 0xc1 +# CHECK: r17:16 = decbin(r21:20, r31:30) + +# Saturate 0x11 0xc0 0xd4 0x88 # CHECK: r17 = sat(r21:20) 0x91 0xc0 0xd5 0x8c @@ -10,9 +16,89 @@ # CHECK: r17 = satub(r21) 0xf1 0xc0 0xd5 0x8c # CHECK: r17 = satb(r21) + +# Swizzle bytes 0xf1 0xc0 0x95 0x8c # CHECK: r17 = swiz(r21) + +# Vector align 0x70 0xd4 0x1e 0xc2 # CHECK: r17:16 = valignb(r21:20, r31:30, p3) 0x70 0xde 0x94 0xc2 # CHECK: r17:16 = vspliceb(r21:20, r31:30, p3) + +# Vector round and pack +0x91 0xc0 0x94 0x88 +# CHECK: r17 = vrndwh(r21:20) +0xd1 0xc0 0x94 0x88 +# CHECK: r17 = vrndwh(r21:20):sat + +# Vector saturate and pack +0x11 0xc0 0x14 0x88 +# CHECK: r17 = vsathub(r21:20) +0x51 0xc0 0x14 0x88 +# CHECK: r17 = vsatwh(r21:20) +0x91 0xc0 0x14 0x88 +# CHECK: r17 = vsatwuh(r21:20) +0xd1 0xc0 0x14 0x88 +# CHECK: r17 = vsathb(r21:20) +0x11 0xc0 0x95 0x8c +# CHECK: r17 = vsathb(r21) +0x51 0xc0 0x95 0x8c +# CHECK: r17 = vsathub(r21) + +# Vector saturate without pack +0x90 0xc0 0x14 0x80 +# CHECK: r17:16 = vsathub(r21:20) +0xb0 0xc0 0x14 0x80 +# CHECK: r17:16 = vsatwuh(r21:20) +0xd0 0xc0 0x14 0x80 +# CHECK: r17:16 = vsatwh(r21:20) +0xf0 0xc0 0x14 0x80 +# CHECK: r17:16 = vsathb(r21:20) + +# Vector shuffle +0x50 0xde 0x14 0xc1 +# CHECK: r17:16 = shuffeb(r21:20, r31:30) +0x90 0xd4 0x1e 0xc1 +# CHECK: r17:16 = shuffob(r21:20, r31:30) +0xd0 0xde 0x14 0xc1 +# CHECK: r17:16 = shuffeh(r21:20, r31:30) +0x10 0xd4 0x9e 0xc1 +# CHECK: r17:16 = shuffoh(r21:20, r31:30) + +# Vector splat bytes +0xf1 0xc0 0x55 0x8c +# CHECK: r17 = vsplatb(r21) + +# Vector splat halfwords +0x50 0xc0 0x55 0x84 +# CHECK: r17:16 = vsplath(r21) + +# Vector splice +0x70 0xde 0x94 0xc0 +# CHECK: r17:16 = vspliceb(r21:20, r31:30, #3) +0x70 0xde 0x94 0xc2 +# CHECK: r17:16 = vspliceb(r21:20, r31:30, p3) + +# Vector sign extend +0x10 0xc0 0x15 0x84 +# CHECK: r17:16 = vsxtbh(r21) +0x90 0xc0 0x15 0x84 +# CHECK: r17:16 = vsxthw(r21) + +# Vector truncate +0x11 0xc0 0x94 0x88 +# CHECK: r17 = vtrunohb(r21:20) +0x51 0xc0 0x94 0x88 +# CHECK: r17 = vtrunehb(r21:20) +0x50 0xde 0x94 0xc1 +# CHECK: r17:16 = vtrunewh(r21:20, r31:30) +0x90 0xde 0x94 0xc1 +# CHECK: r17:16 = vtrunowh(r21:20, r31:30) + +# Vector zero extend +0x50 0xc0 0x15 0x84 +# CHECK: r17:16 = vzxtbh(r21) +0xd0 0xc0 0x15 0x84 +# CHECK: r17:16 = vzxthw(r21)