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[Hexagon] Adding vector permutation instructions and tests.
llvm-svn: 227612
This commit is contained in:
Colin LeMahieu
parent
42ded7f3da
commit
ee3ca03932
@ -3866,12 +3866,42 @@ let hasNewValue = 1 in
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class T_S2op_1_ii <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit isSat = 0>
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: T_S2op_1 <mnemonic, 0b1100, IntRegs, IntRegs, MajOp, MinOp, isSat>;
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// Vector sign/zero extend
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let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 0 in {
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def S2_vsxtbh : T_S2op_1_di <"vsxtbh", 0b00, 0b000>;
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def S2_vsxthw : T_S2op_1_di <"vsxthw", 0b00, 0b100>;
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def S2_vzxtbh : T_S2op_1_di <"vzxtbh", 0b00, 0b010>;
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def S2_vzxthw : T_S2op_1_di <"vzxthw", 0b00, 0b110>;
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}
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// Vector splat bytes/halfwords
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let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 0 in {
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def S2_vsplatrb : T_S2op_1_ii <"vsplatb", 0b01, 0b111>;
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def S2_vsplatrh : T_S2op_1_di <"vsplath", 0b01, 0b010>;
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}
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// Sign extend word to doubleword
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let isCodeGenOnly = 0 in
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def A2_sxtw : T_S2op_1_di <"sxtw", 0b01, 0b000>;
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def: Pat <(i64 (sext I32:$src)), (A2_sxtw I32:$src)>;
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// Vector saturate and pack
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let Defs = [USR_OVF], isCodeGenOnly = 0 in {
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def S2_svsathb : T_S2op_1_ii <"vsathb", 0b10, 0b000>;
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def S2_svsathub : T_S2op_1_ii <"vsathub", 0b10, 0b010>;
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def S2_vsathb : T_S2op_1_id <"vsathb", 0b00, 0b110>;
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def S2_vsathub : T_S2op_1_id <"vsathub", 0b00, 0b000>;
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def S2_vsatwh : T_S2op_1_id <"vsatwh", 0b00, 0b010>;
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def S2_vsatwuh : T_S2op_1_id <"vsatwuh", 0b00, 0b100>;
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}
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// Vector truncate
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let isCodeGenOnly = 0 in {
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def S2_vtrunohb : T_S2op_1_id <"vtrunohb", 0b10, 0b000>;
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def S2_vtrunehb : T_S2op_1_id <"vtrunehb", 0b10, 0b010>;
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}
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// Swizzle the bytes of a word
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let isCodeGenOnly = 0 in
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def A2_swiz : T_S2op_1_ii <"swiz", 0b10, 0b111>;
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@ -3887,6 +3917,12 @@ let Defs = [USR_OVF], isCodeGenOnly = 0 in {
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}
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let Itinerary = S_2op_tc_2_SLOT23, isCodeGenOnly = 0 in {
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// Vector round and pack
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def S2_vrndpackwh : T_S2op_1_id <"vrndwh", 0b10, 0b100>;
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let Defs = [USR_OVF] in
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def S2_vrndpackwhs : T_S2op_1_id <"vrndwh", 0b10, 0b110, 1>;
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// Bit reverse
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def S2_brev : T_S2op_1_ii <"brev", 0b01, 0b110>;
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@ -4007,6 +4043,14 @@ def S2_deinterleave : T_S2op_3 <"deinterleave", 0b11, 0b100>;
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let isCodeGenOnly = 0 in
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def A2_vconj : T_S2op_3 <"vconj", 0b10, 0b111, 1>;
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// Vector saturate without pack
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let isCodeGenOnly = 0 in {
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def S2_vsathb_nopack : T_S2op_3 <"vsathb", 0b00, 0b111>;
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def S2_vsathub_nopack : T_S2op_3 <"vsathub", 0b00, 0b100>;
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def S2_vsatwh_nopack : T_S2op_3 <"vsatwh", 0b00, 0b110>;
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def S2_vsatwuh_nopack : T_S2op_3 <"vsatwuh", 0b00, 0b101>;
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}
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// Vector absolute value halfwords with and without saturation
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// Rdd64=vabsh(Rss64)[:sat]
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let isCodeGenOnly = 0 in {
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@ -5573,6 +5617,16 @@ class T_S3op_64 <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit SwapOps,
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: T_S3op_1 <mnemonic, DoubleRegs, MajOp, MinOp, SwapOps,
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isSat, isRnd, hasShift>;
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let Itinerary = S_3op_tc_1_SLOT23, isCodeGenOnly = 0 in {
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def S2_shuffeb : T_S3op_64 < "shuffeb", 0b00, 0b010, 0>;
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def S2_shuffeh : T_S3op_64 < "shuffeh", 0b00, 0b110, 0>;
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def S2_shuffob : T_S3op_64 < "shuffob", 0b00, 0b100, 1>;
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def S2_shuffoh : T_S3op_64 < "shuffoh", 0b10, 0b000, 1>;
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def S2_vtrunewh : T_S3op_64 < "vtrunewh", 0b10, 0b010, 0>;
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def S2_vtrunowh : T_S3op_64 < "vtrunowh", 0b10, 0b100, 0>;
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}
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let isCodeGenOnly = 0 in
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def S2_lfsp : T_S3op_64 < "lfs", 0b10, 0b110, 0>;
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@ -5702,6 +5756,32 @@ class T_S3op_8 <string opc, bits<3> MinOp, bit isSat, bit isRnd, bit hasShift, b
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let Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23, isCodeGenOnly = 0 in
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def S2_vcrotate : T_S3op_shiftVect < "vcrotate", 0b11, 0b00>;
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let hasSideEffects = 0 in
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class T_S3op_7 <string mnemonic, bit MajOp >
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: SInst <(outs DoubleRegs:$Rdd),
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(ins DoubleRegs:$Rss, DoubleRegs:$Rtt, u3Imm:$u3),
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"$Rdd = "#mnemonic#"($Rss, $Rtt, #$u3)" ,
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[], "", S_3op_tc_1_SLOT23 > {
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bits<5> Rdd;
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bits<5> Rss;
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bits<5> Rtt;
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bits<3> u3;
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let IClass = 0b1100;
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let Inst{27-24} = 0b0000;
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let Inst{23} = MajOp;
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let Inst{20-16} = !if(MajOp, Rss, Rtt);
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let Inst{12-8} = !if(MajOp, Rtt, Rss);
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let Inst{7-5} = u3;
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let Inst{4-0} = Rdd;
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}
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let isCodeGenOnly = 0 in {
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def S2_valignib : T_S3op_7 < "valignb", 0>;
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def S2_vspliceib : T_S3op_7 < "vspliceb", 1>;
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}
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//===----------------------------------------------------------------------===//
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// Template class for 'insert bitfield' instructions
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//===----------------------------------------------------------------------===//
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@ -254,3 +254,8 @@ let isCodeGenOnly = 0 in {
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def M2_vrcmpys_s1rp_h : T_MType_vrcmpy <"vrcmpys", 0b101, 0b110, 1>;
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def M2_vrcmpys_s1rp_l : T_MType_vrcmpy <"vrcmpys", 0b101, 0b111, 0>;
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}
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// S2_cabacdecbin: Cabac decode bin.
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let Defs = [P0], isPredicateLate = 1, Itinerary = S_3op_tc_1_SLOT23,
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isCodeGenOnly = 0 in
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def S2_cabacdecbin : T_S3op_64 < "decbin", 0b11, 0b110, 0>;
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@ -1,5 +1,11 @@
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# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
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# RUN: llvm-mc -triple=hexagon -disassemble < %s | FileCheck %s
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# Hexagon Programmer's Reference Manual 11.10.6 XTYPE/PERM
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# CABAC decode bin
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0xd0 0xde 0xd4 0xc1
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# CHECK: r17:16 = decbin(r21:20, r31:30)
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# Saturate
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0x11 0xc0 0xd4 0x88
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# CHECK: r17 = sat(r21:20)
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0x91 0xc0 0xd5 0x8c
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@ -10,9 +16,89 @@
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# CHECK: r17 = satub(r21)
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0xf1 0xc0 0xd5 0x8c
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# CHECK: r17 = satb(r21)
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# Swizzle bytes
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0xf1 0xc0 0x95 0x8c
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# CHECK: r17 = swiz(r21)
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# Vector align
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0x70 0xd4 0x1e 0xc2
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# CHECK: r17:16 = valignb(r21:20, r31:30, p3)
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0x70 0xde 0x94 0xc2
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# CHECK: r17:16 = vspliceb(r21:20, r31:30, p3)
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# Vector round and pack
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0x91 0xc0 0x94 0x88
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# CHECK: r17 = vrndwh(r21:20)
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0xd1 0xc0 0x94 0x88
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# CHECK: r17 = vrndwh(r21:20):sat
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# Vector saturate and pack
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0x11 0xc0 0x14 0x88
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# CHECK: r17 = vsathub(r21:20)
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0x51 0xc0 0x14 0x88
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# CHECK: r17 = vsatwh(r21:20)
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0x91 0xc0 0x14 0x88
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# CHECK: r17 = vsatwuh(r21:20)
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0xd1 0xc0 0x14 0x88
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# CHECK: r17 = vsathb(r21:20)
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0x11 0xc0 0x95 0x8c
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# CHECK: r17 = vsathb(r21)
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0x51 0xc0 0x95 0x8c
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# CHECK: r17 = vsathub(r21)
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# Vector saturate without pack
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0x90 0xc0 0x14 0x80
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# CHECK: r17:16 = vsathub(r21:20)
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0xb0 0xc0 0x14 0x80
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# CHECK: r17:16 = vsatwuh(r21:20)
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0xd0 0xc0 0x14 0x80
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# CHECK: r17:16 = vsatwh(r21:20)
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0xf0 0xc0 0x14 0x80
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# CHECK: r17:16 = vsathb(r21:20)
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# Vector shuffle
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0x50 0xde 0x14 0xc1
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# CHECK: r17:16 = shuffeb(r21:20, r31:30)
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0x90 0xd4 0x1e 0xc1
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# CHECK: r17:16 = shuffob(r21:20, r31:30)
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0xd0 0xde 0x14 0xc1
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# CHECK: r17:16 = shuffeh(r21:20, r31:30)
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0x10 0xd4 0x9e 0xc1
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# CHECK: r17:16 = shuffoh(r21:20, r31:30)
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# Vector splat bytes
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0xf1 0xc0 0x55 0x8c
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# CHECK: r17 = vsplatb(r21)
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# Vector splat halfwords
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0x50 0xc0 0x55 0x84
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# CHECK: r17:16 = vsplath(r21)
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# Vector splice
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0x70 0xde 0x94 0xc0
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# CHECK: r17:16 = vspliceb(r21:20, r31:30, #3)
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0x70 0xde 0x94 0xc2
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# CHECK: r17:16 = vspliceb(r21:20, r31:30, p3)
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# Vector sign extend
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0x10 0xc0 0x15 0x84
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# CHECK: r17:16 = vsxtbh(r21)
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0x90 0xc0 0x15 0x84
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# CHECK: r17:16 = vsxthw(r21)
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# Vector truncate
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0x11 0xc0 0x94 0x88
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# CHECK: r17 = vtrunohb(r21:20)
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0x51 0xc0 0x94 0x88
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# CHECK: r17 = vtrunehb(r21:20)
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0x50 0xde 0x94 0xc1
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# CHECK: r17:16 = vtrunewh(r21:20, r31:30)
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0x90 0xde 0x94 0xc1
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# CHECK: r17:16 = vtrunowh(r21:20, r31:30)
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# Vector zero extend
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0x50 0xc0 0x15 0x84
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# CHECK: r17:16 = vzxtbh(r21)
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0xd0 0xc0 0x15 0x84
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# CHECK: r17:16 = vzxthw(r21)
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