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[BranchRelaxation] Simplify offset computation and fix a bug in adjustBlockOffsets()

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If Start!=0, adjustBlockOffsets() may unnecessarily adjust the offset of
Start. There is no correctness issue, but it can create more block
splits.
This commit is contained in:
Fangrui Song 2020-01-19 14:53:45 -08:00 committed by Fangrui Song
parent 74f4f88ee1
commit ee4ec0d295
3 changed files with 8 additions and 20 deletions
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13
lib/CodeGen/BranchRelaxation.cpp
View File

@ -67,16 +67,13 @@ class BranchRelaxation : public MachineFunctionPass {
unsigned postOffset(const MachineBasicBlock &MBB) const {
const unsigned PO = Offset + Size;
const Align Alignment = MBB.getAlignment();
if (Alignment == 1)
return PO;
const Align ParentAlign = MBB.getParent()->getAlignment();
if (Alignment <= ParentAlign)
return PO + offsetToAlignment(PO, Alignment);
return alignTo(PO, Alignment);
// The alignment of this MBB is larger than the function's alignment, so we
// can't tell whether or not it will insert nops. Assume that it will.
return PO + Alignment.value() + offsetToAlignment(PO, Alignment);
return alignTo(PO, Alignment) + Alignment.value() - ParentAlign.value();
}
};
@ -129,7 +126,6 @@ void BranchRelaxation::verify() {
unsigned PrevNum = MF->begin()->getNumber();
for (MachineBasicBlock &MBB : *MF) {
const unsigned Num = MBB.getNumber();
assert(isAligned(MBB.getAlignment(), BlockInfo[Num].Offset));
assert(!Num || BlockInfo[PrevNum].postOffset(MBB) <= BlockInfo[Num].Offset);
assert(BlockInfo[Num].Size == computeBlockSize(MBB));
PrevNum = Num;
@ -195,10 +191,9 @@ unsigned BranchRelaxation::getInstrOffset(const MachineInstr &MI) const {
void BranchRelaxation::adjustBlockOffsets(MachineBasicBlock &Start) {
unsigned PrevNum = Start.getNumber();
for (auto &MBB : make_range(MachineFunction::iterator(Start), MF->end())) {
for (auto &MBB :
make_range(std::next(MachineFunction::iterator(Start)), MF->end())) {
unsigned Num = MBB.getNumber();
if (!Num) // block zero is never changed from offset zero.
continue;
// Get the offset and known bits at the end of the layout predecessor.
// Include the alignment of the current block.
BlockInfo[Num].Offset = BlockInfo[PrevNum].postOffset(MBB);

12
test/CodeGen/AArch64/branch-relax-bcc.ll
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@ -2,13 +2,10 @@
; CHECK-LABEL: invert_bcc:
; CHECK: fcmp s0, s1
; CHECK-NEXT: b.eq [[JUMP_BB1:LBB[0-9]+_[0-9]+]]
; CHECK-NEXT: b [[JUMP_BB2:LBB[0-9]+_[0-9]+]]
; CHECK-NEXT: [[JUMP_BB1]]:
; CHECK-NEXT: b.ne [[JUMP_BB1:LBB[0-9]+_[0-9]+]]
; CHECK-NEXT: b [[BB1:LBB[0-9]+_[0-9]+]]
; CHECK-NEXT: [[JUMP_BB2]]:
; CHECK-NEXT: [[JUMP_BB1]]:
; CHECK-NEXT: b.vc [[BB2:LBB[0-9]+_[0-9]+]]
; CHECK-NEXT: b [[BB1]]
@ -41,10 +38,7 @@ declare i32 @foo() #0
; CHECK-LABEL: _block_split:
; CHECK: cmp w0, #5
; CHECK-NEXT: b.eq [[LONG_BR_BB:LBB[0-9]+_[0-9]+]]
; CHECK-NEXT: b [[LOR_LHS_FALSE_BB:LBB[0-9]+_[0-9]+]]
; CHECK: [[LONG_BR_BB]]:
; CHECK-NEXT: b.ne [[LOR_LHS_FALSE_BB:LBB[0-9]+_[0-9]+]]
; CHECK-NEXT: b [[IF_THEN_BB:LBB[0-9]+_[0-9]+]]
; CHECK: [[LOR_LHS_FALSE_BB]]:

3
test/CodeGen/AMDGPU/branch-relaxation.ll
View File

@ -491,8 +491,7 @@ ret:
; GCN-LABEL: {{^}}long_branch_hang:
; GCN: s_cmp_lt_i32 s{{[0-9]+}}, 6
; GCN: s_cbranch_scc1 {{BB[0-9]+_[0-9]+}}
; GCN-NEXT: s_branch [[LONG_BR_0:BB[0-9]+_[0-9]+]]
; GCN: s_cbranch_scc0 [[LONG_BR_0:BB[0-9]+_[0-9]+]]
; GCN-NEXT: BB{{[0-9]+_[0-9]+}}:
; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, [[LONG_BR_DEST0:BB[0-9]+_[0-9]+]]-(