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Add -disable-shifter-op to disable isel of shifter ops. On Cortex-a9 the shifts cost extra instructions so it might be better to emit them separately to take advantage of dual-issues.
llvm-svn: 109934
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@ -36,6 +36,11 @@
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using namespace llvm;
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using namespace llvm;
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static cl::opt<bool>
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DisableShifterOp("disable-shifter-op", cl::Hidden,
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cl::desc("Disable isel of shifter-op"),
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cl::init(false));
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//===--------------------------------------------------------------------===//
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//===--------------------------------------------------------------------===//
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/// ARMDAGToDAGISel - ARM specific code to select ARM machine
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/// ARMDAGToDAGISel - ARM specific code to select ARM machine
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/// instructions for SelectionDAG operations.
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/// instructions for SelectionDAG operations.
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@ -220,6 +225,9 @@ bool ARMDAGToDAGISel::SelectShifterOperandReg(SDNode *Op,
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SDValue &BaseReg,
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SDValue &BaseReg,
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SDValue &ShReg,
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SDValue &ShReg,
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SDValue &Opc) {
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SDValue &Opc) {
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if (DisableShifterOp)
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return false;
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ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
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ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
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// Don't match base register only case. That is matched to a separate
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// Don't match base register only case. That is matched to a separate
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@ -666,6 +674,9 @@ bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDNode *Op, SDValue N,
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bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDNode *Op, SDValue N,
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bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDNode *Op, SDValue N,
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SDValue &BaseReg,
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SDValue &BaseReg,
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SDValue &Opc) {
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SDValue &Opc) {
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if (DisableShifterOp)
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return false;
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ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
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ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
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// Don't match base register only case. That is matched to a separate
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// Don't match base register only case. That is matched to a separate
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