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AArch64: use xzr/wzr for constant 0 in GlobalISel.

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COPYs from xzr and wzr can often be folded away entirely during register
allocation, unlike a movz.

llvm-svn: 368003
This commit is contained in:
Tim Northover 2019-08-06 09:18:41 +00:00
parent 8ded184cba
commit ee608c40a5
6 changed files with 53 additions and 28 deletions
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25
lib/Target/AArch64/AArch64InstructionSelector.cpp
View File

@ -1284,6 +1284,31 @@ bool AArch64InstructionSelector::earlySelect(MachineInstr &I) const {
return earlySelectSHL(I, MRI);
case TargetOpcode::G_LOAD:
return earlySelectLoad(I, MRI);
case TargetOpcode::G_CONSTANT: {
bool IsZero = false;
if (I.getOperand(1).isCImm())
IsZero = I.getOperand(1).getCImm()->getZExtValue() == 0;
else if (I.getOperand(1).isImm())
IsZero = I.getOperand(1).getImm() == 0;
if (!IsZero)
return false;
Register DefReg = I.getOperand(0).getReg();
LLT Ty = MRI.getType(DefReg);
assert((Ty == LLT::scalar(64) || Ty == LLT::scalar(32)) &&
"Unexpected legal constant type");
if (Ty == LLT::scalar(64)) {
I.getOperand(1).ChangeToRegister(AArch64::XZR, false);
RBI.constrainGenericRegister(DefReg, AArch64::GPR64RegClass, MRI);
} else {
I.getOperand(1).ChangeToRegister(AArch64::WZR, false);
RBI.constrainGenericRegister(DefReg, AArch64::GPR32RegClass, MRI);
}
I.setDesc(TII.get(TargetOpcode::COPY));
return true;
}
default:
return false;
}

8
test/CodeGen/AArch64/GlobalISel/fold-select.mir
View File

@ -21,9 +21,9 @@ body: |
; CHECK: liveins: $w0, $w1
; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 0
; CHECK: [[MOVwzr:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK: $wzr = SUBSWri [[COPY]], 0, 0, implicit-def $nzcv
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY1]], 0, implicit $nzcv
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVwzr]], [[COPY1]], 0, implicit $nzcv
; CHECK: $w0 = COPY [[CSELWr]]
; CHECK: RET_ReallyLR implicit $w0
%0:gpr(s32) = COPY $w0
@ -50,9 +50,9 @@ body: |
; CHECK: liveins: $s0, $w0, $w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 0
; CHECK: [[MOVwzr:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK: FCMPSri [[COPY1]], implicit-def $nzcv
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY]], 0, implicit $nzcv
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVwzr]], [[COPY]], 0, implicit $nzcv
; CHECK: $w0 = COPY [[CSELWr]]
; CHECK: RET_ReallyLR implicit $w0
%1:gpr(s32) = COPY $w1

26
test/CodeGen/AArch64/GlobalISel/opt-fold-compare.mir
View File

@ -44,10 +44,10 @@ body: |
; CHECK: liveins: $w0, $w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 0
; CHECK: [[MOVwzr:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: $wzr = ADDSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm1]], [[MOVi32imm]], 1, implicit $nzcv
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm1]], [[MOVwzr]], 1, implicit $nzcv
; CHECK: $w0 = COPY [[CSELWr]]
; CHECK: RET_ReallyLR implicit $w0
%0:gpr(s32) = COPY $w0
@ -76,7 +76,7 @@ body: |
; CHECK: liveins: $w0, $w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 0
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: $wzr = ADDSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm1]], [[MOVi32imm]], 1, implicit $nzcv
@ -108,7 +108,7 @@ body: |
; CHECK: liveins: $w0, $w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 0
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[MOVi32imm]], [[COPY1]], implicit-def $nzcv
; CHECK: $wzr = SUBSWrr [[COPY]], [[SUBSWrr]], implicit-def $nzcv
@ -141,7 +141,7 @@ body: |
; CHECK: liveins: $w0, $w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 0
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[MOVi32imm]], [[COPY]], implicit-def $nzcv
; CHECK: $wzr = SUBSWrr [[SUBSWrr]], [[COPY1]], implicit-def $nzcv
@ -174,7 +174,7 @@ body: |
; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 0
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = COPY $xzr
; CHECK: [[MOVi64imm1:%[0-9]+]]:gpr64 = MOVi64imm 1
; CHECK: $xzr = ADDSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[MOVi64imm1]], [[MOVi64imm]], 1, implicit $nzcv
@ -206,7 +206,7 @@ body: |
; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 0
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = COPY $xzr
; CHECK: [[MOVi64imm1:%[0-9]+]]:gpr64 = MOVi64imm 1
; CHECK: $xzr = ADDSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[MOVi64imm1]], [[MOVi64imm]], 1, implicit $nzcv
@ -238,7 +238,7 @@ body: |
; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 0
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = COPY $xzr
; CHECK: [[MOVi64imm1:%[0-9]+]]:gpr64 = MOVi64imm 1
; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[MOVi64imm]], [[COPY1]], implicit-def $nzcv
; CHECK: $xzr = SUBSXrr [[COPY]], [[SUBSXrr]], implicit-def $nzcv
@ -271,7 +271,7 @@ body: |
; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 0
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = COPY $xzr
; CHECK: [[MOVi64imm1:%[0-9]+]]:gpr64 = MOVi64imm 1
; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[MOVi64imm]], [[COPY]], implicit-def $nzcv
; CHECK: $xzr = SUBSXrr [[SUBSXrr]], [[COPY1]], implicit-def $nzcv
@ -302,7 +302,7 @@ body: |
; CHECK-LABEL: name: tst_s32
; CHECK: liveins: $w0, $w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 0
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: $wzr = ANDSWrr [[MOVi32imm]], [[COPY]], implicit-def $nzcv
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm1]], [[MOVi32imm]], 0, implicit $nzcv
@ -333,7 +333,7 @@ body: |
; CHECK-LABEL: name: tst_s64
; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 0
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = COPY $xzr
; CHECK: [[MOVi64imm1:%[0-9]+]]:gpr64 = MOVi64imm 1
; CHECK: $xzr = ANDSXrr [[MOVi64imm]], [[COPY]], implicit-def $nzcv
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[MOVi64imm1]], [[MOVi64imm]], 0, implicit $nzcv
@ -364,7 +364,7 @@ body: |
; CHECK-LABEL: name: no_tst_unsigned_compare
; CHECK: liveins: $w0, $w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 0
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[ANDWrr:%[0-9]+]]:gpr32common = ANDWrr [[MOVi32imm]], [[COPY]]
; CHECK: $wzr = SUBSWri [[ANDWrr]], 0, 0, implicit-def $nzcv
@ -396,7 +396,7 @@ body: |
; CHECK-LABEL: name: no_tst_nonzero
; CHECK: liveins: $w0, $w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 0
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[ANDWrr:%[0-9]+]]:gpr32common = ANDWrr [[MOVi32imm]], [[COPY]]
; CHECK: $wzr = SUBSWri [[ANDWrr]], 42, 0, implicit-def $nzcv

4
test/CodeGen/AArch64/GlobalISel/select-cmpxchg.mir
View File

@ -19,7 +19,7 @@ body: |
; CHECK-LABEL: name: cmpxchg_i32
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[CMP:%[0-9]+]]:gpr32 = MOVi32imm 0
; CHECK: [[CMP:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[RES:%[0-9]+]]:gpr32 = CASW [[CMP]], [[CST]], [[COPY]] :: (load store monotonic 4 on %ir.addr)
; CHECK: $w0 = COPY [[RES]]
@ -41,7 +41,7 @@ body: |
; CHECK-LABEL: name: cmpxchg_i64
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[CMP:%[0-9]+]]:gpr64 = MOVi64imm 0
; CHECK: [[CMP:%[0-9]+]]:gpr64 = COPY $xzr
; CHECK: [[CST:%[0-9]+]]:gpr64 = MOVi64imm 1
; CHECK: [[RES:%[0-9]+]]:gpr64 = CASX [[CMP]], [[CST]], [[COPY]] :: (load store monotonic 8 on %ir.addr)
; CHECK: $x0 = COPY [[RES]]

4
test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir
View File

@ -57,7 +57,7 @@ body: |
; CHECK: successors: %bb.4(0x40000000), %bb.1(0x40000000)
; CHECK: liveins: $w0
; CHECK: [[COPY:%[0-9]+]]:gpr32common = COPY $w0
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 0
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 4, 0, implicit-def $nzcv
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[SUBSWri]], %subreg.sub_32
; CHECK: [[UBFMXri:%[0-9]+]]:gpr64common = UBFMXri [[SUBREG_TO_REG]], 0, 31
@ -65,7 +65,7 @@ body: |
; CHECK: Bcc 8, %bb.4, implicit $nzcv
; CHECK: bb.1.entry:
; CHECK: successors: %bb.3(0x2aaaaaab), %bb.4(0x2aaaaaab), %bb.2(0x2aaaaaab)
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 0
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK: [[MOVaddrJT:%[0-9]+]]:gpr64 = MOVaddrJT target-flags(aarch64-page) %jump-table.0, target-flags(aarch64-pageoff, aarch64-nc) %jump-table.0
; CHECK: early-clobber %18:gpr64, early-clobber %19:gpr64sp = JumpTableDest32 [[MOVaddrJT]], [[UBFMXri]], %jump-table.0
; CHECK: BR %18

14
test/CodeGen/AArch64/GlobalISel/swifterror.ll
View File

@ -59,7 +59,7 @@ define float @caller2(i8* %error_ref) {
; CHECK-LABEL: caller2:
; CHECK: mov [[ID:x[0-9]+]], x0
; CHECK: fmov [[CMP:s[0-9]+]], #1.0
; CHECK: mov x21, #0
; CHECK: mov x21, xzr
; CHECK: bl {{.*}}foo
; CHECK: cbnz x21
; CHECK: fcmp s0, [[CMP]]
@ -187,7 +187,7 @@ entry:
define float @caller3(i8* %error_ref) {
; CHECK-LABEL: caller3:
; CHECK: mov [[ID:x[0-9]+]], x0
; CHECK: mov [[ZERO:x[0-9]+]], #0
; CHECK: mov [[ZERO:x[0-9]+]], xzr
; CHECK: bl {{.*}}foo_sret
; CHECK: mov x0, x21
; CHECK: cbnz x21
@ -263,8 +263,8 @@ define float @caller4(i8* %error_ref) {
; CHECK: mov [[ID:x[0-9]+]], x0
; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp]
; CHECK: mov x21, #0
; CHECK: str {{x[0-9]+}}, [sp, #16]
; CHECK: mov x21, xzr
; CHECK: bl {{.*}}foo_vararg
; CHECK: mov x0, x21
@ -333,7 +333,6 @@ entry:
; CHECK: mov x27, x7
; CHECK: mov x28, x21
; Setup call.
; CHECK: mov x8, #0
; CHECK: mov x0, #1
; CHECK: mov x1, #2
; CHECK: mov x2, #3
@ -342,7 +341,8 @@ entry:
; CHECK: mov x5, #6
; CHECK: mov x6, #7
; CHECK: mov x7, #8
; CHECK: mov x21, #0
; CHECK: str xzr, [sp]
; CHECK: mov x21, xzr
; CHECK: bl _params_in_reg2
; Restore original arguments for next call.
; CHECK: ldr x0, [sp
@ -406,7 +406,7 @@ declare swiftcc void @params_in_reg2(i64, i64, i64, i64, i64, i64, i64, i64, i8*
; CHECK: mov x5, #6
; CHECK: mov x6, #7
; CHECK: mov x7, #8
; CHECK: mov x21, #0
; CHECK: mov x21, xzr
; CHECK: bl _params_in_reg2
; Store swifterror %error_ptr_ref.
; CHECK: stp {{x[0-9]+}}, x21, [sp]
@ -489,7 +489,7 @@ entry:
declare swiftcc void @foo2(%swift_error** swifterror)
; CHECK-LABEL: testAssign
; CHECK: mov x21, #0
; CHECK: mov x21, xzr
; CHECK: bl _foo2
; CHECK: mov x0, x21