RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 19:52:54 +01:00
Code Issues Projects Releases Wiki Activity

Add <imp-def> operands to QQ and QQQQ stack loads.

Browse Source 
This pleases the register scavenger and brings
test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll a little closer to
working with -verify-machineinstrs.

llvm-svn: 138164
This commit is contained in:
Jakob Stoklund Olesen 2011-08-20 00:17:45 +00:00
parent 55c57f07dd
commit ee6264c790
1 changed files with 4 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -930,7 +930,8 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
MIB.addReg(DestReg, RegState::Define | RegState::Implicit);
}
} else
llvm_unreachable("Unknown reg class!");
@ -948,7 +949,8 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI);
AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI);
MIB.addReg(DestReg, RegState::Define | RegState::Implicit);
} else
llvm_unreachable("Unknown reg class!");
break;