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[CodeGenPrepare][NFC] Rename TargetTransformInfo::expandMemCmp -> TargetTransformInfo::enableMemCmpExpansion.

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Summary:
Right now there are two functions with the same name, one does the work
and the other one returns true if expansion is needed. Rename
TargetTransformInfo::expandMemCmp to make it more consistent with other
members of TargetTransformInfo.

Remove the unused Instruction* parameter.

Differential Revision: https://reviews.llvm.org/D38165

llvm-svn: 314096
This commit is contained in:
Clement Courbet 2017-09-25 06:35:16 +00:00
parent 7464cec0af
commit ee8300aee3
8 changed files with 12 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
include/llvm/Analysis/TargetTransformInfo.h
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@ -548,7 +548,7 @@ public:
bool enableAggressiveInterleaving(bool LoopHasReductions) const;
/// \brief Enable inline expansion of memcmp
bool expandMemCmp(Instruction *I, unsigned &MaxLoadSize) const;
bool enableMemCmpExpansion(unsigned &MaxLoadSize) const;
/// \brief Enable matching of interleaved access groups.
bool enableInterleavedAccessVectorization() const;
@ -985,7 +985,7 @@ public:
unsigned VF) = 0;
virtual bool supportsEfficientVectorElementLoadStore() = 0;
virtual bool enableAggressiveInterleaving(bool LoopHasReductions) = 0;
virtual bool expandMemCmp(Instruction *I, unsigned &MaxLoadSize) = 0;
virtual bool enableMemCmpExpansion(unsigned &MaxLoadSize) = 0;
virtual bool enableInterleavedAccessVectorization() = 0;
virtual bool isFPVectorizationPotentiallyUnsafe() = 0;
virtual bool allowsMisalignedMemoryAccesses(LLVMContext &Context,
@ -1235,8 +1235,8 @@ public:
bool enableAggressiveInterleaving(bool LoopHasReductions) override {
return Impl.enableAggressiveInterleaving(LoopHasReductions);
}
bool expandMemCmp(Instruction *I, unsigned &MaxLoadSize) override {
return Impl.expandMemCmp(I, MaxLoadSize);
bool enableMemCmpExpansion(unsigned &MaxLoadSize) override {
return Impl.enableMemCmpExpansion(MaxLoadSize);
}
bool enableInterleavedAccessVectorization() override {
return Impl.enableInterleavedAccessVectorization();

2
include/llvm/Analysis/TargetTransformInfoImpl.h
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@ -290,7 +290,7 @@ public:
bool enableAggressiveInterleaving(bool LoopHasReductions) { return false; }
bool expandMemCmp(Instruction *I, unsigned &MaxLoadSize) { return false; }
bool enableMemCmpExpansion(unsigned &MaxLoadSize) { return false; }
bool enableInterleavedAccessVectorization() { return false; }

4
lib/Analysis/TargetTransformInfo.cpp
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@ -245,8 +245,8 @@ bool TargetTransformInfo::enableAggressiveInterleaving(bool LoopHasReductions) c
return TTIImpl->enableAggressiveInterleaving(LoopHasReductions);
}
bool TargetTransformInfo::expandMemCmp(Instruction *I, unsigned &MaxLoadSize) const {
return TTIImpl->expandMemCmp(I, MaxLoadSize);
bool TargetTransformInfo::enableMemCmpExpansion(unsigned &MaxLoadSize) const {
return TTIImpl->enableMemCmpExpansion(MaxLoadSize);
}
bool TargetTransformInfo::enableInterleavedAccessVectorization() const {

2
lib/CodeGen/CodeGenPrepare.cpp
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@ -2315,7 +2315,7 @@ static bool expandMemCmp(CallInst *CI, const TargetTransformInfo *TTI,
// TTI call to check if target would like to expand memcmp. Also, get the
// MaxLoadSize.
unsigned MaxLoadSize;
if (!TTI->expandMemCmp(CI, MaxLoadSize))
if (!TTI->enableMemCmpExpansion(MaxLoadSize))
return false;
// Early exit from expansion if -Oz.

2
lib/Target/PowerPC/PPCTargetTransformInfo.cpp
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@ -215,7 +215,7 @@ bool PPCTTIImpl::enableAggressiveInterleaving(bool LoopHasReductions) {
return LoopHasReductions;
}
bool PPCTTIImpl::expandMemCmp(Instruction *I, unsigned &MaxLoadSize) {
bool PPCTTIImpl::enableMemCmpExpansion(unsigned &MaxLoadSize) {
MaxLoadSize = 8;
return true;
}

2
lib/Target/PowerPC/PPCTargetTransformInfo.h
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@ -61,7 +61,7 @@ public:
/// @{
bool enableAggressiveInterleaving(bool LoopHasReductions);
bool expandMemCmp(Instruction *I, unsigned &MaxLoadSize);
bool enableMemCmpExpansion(unsigned &MaxLoadSize);
bool enableInterleavedAccessVectorization();
unsigned getNumberOfRegisters(bool Vector);
unsigned getRegisterBitWidth(bool Vector) const;

2
lib/Target/X86/X86TargetTransformInfo.cpp
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@ -2536,7 +2536,7 @@ bool X86TTIImpl::areInlineCompatible(const Function *Caller,
return (CallerBits & CalleeBits) == CalleeBits;
}
bool X86TTIImpl::expandMemCmp(Instruction *I, unsigned &MaxLoadSize) {
bool X86TTIImpl::enableMemCmpExpansion(unsigned &MaxLoadSize) {
// TODO: We can increase these based on available vector ops.
MaxLoadSize = ST->is64Bit() ? 8 : 4;
return true;

2
lib/Target/X86/X86TargetTransformInfo.h
View File

@ -127,7 +127,7 @@ public:
bool hasDivRemOp(Type *DataType, bool IsSigned);
bool areInlineCompatible(const Function *Caller,
const Function *Callee) const;
bool expandMemCmp(Instruction *I, unsigned &MaxLoadSize);
bool enableMemCmpExpansion(unsigned &MaxLoadSize);
bool enableInterleavedAccessVectorization();
private:
int getGSScalarCost(unsigned Opcode, Type *DataTy, bool VariableMask,