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GlobalISel: Minor cleanups
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@ -35,7 +35,7 @@ bool CallLowering::lowerCall(MachineIRBuilder &MIRBuilder, ImmutableCallSite CS,
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Register SwiftErrorVReg,
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std::function<unsigned()> GetCalleeReg) const {
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CallLoweringInfo Info;
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auto &DL = CS.getParent()->getParent()->getParent()->getDataLayout();
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const DataLayout &DL = MIRBuilder.getDataLayout();
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// First step is to marshall all the function's parameters into the correct
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// physregs and memory locations. Gather the sequence of argument types that
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@ -62,17 +62,17 @@ bool CallLowering::lowerCall(MachineIRBuilder &MIRBuilder, ImmutableCallSite CS,
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if (!Info.OrigRet.Ty->isVoidTy())
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setArgFlags(Info.OrigRet, AttributeList::ReturnIndex, DL, CS);
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MachineFunction &MF = MIRBuilder.getMF();
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Info.KnownCallees =
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CS.getInstruction()->getMetadata(LLVMContext::MD_callees);
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Info.CallConv = CS.getCallingConv();
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Info.SwiftErrorVReg = SwiftErrorVReg;
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Info.IsMustTailCall = CS.isMustTailCall();
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Info.IsTailCall = CS.isTailCall() &&
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isInTailCallPosition(CS, MIRBuilder.getMF().getTarget()) &&
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(MIRBuilder.getMF()
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.getFunction()
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.getFnAttribute("disable-tail-calls")
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.getValueAsString() != "true");
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isInTailCallPosition(CS, MF.getTarget()) &&
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(MF.getFunction()
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.getFnAttribute("disable-tail-calls")
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.getValueAsString() != "true");
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Info.IsVarArg = CS.getFunctionType()->isVarArg();
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return lowerCall(MIRBuilder, Info);
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}
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@ -160,7 +160,7 @@ void CallLowering::unpackRegs(ArrayRef<Register> DstRegs, Register SrcReg,
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MachineIRBuilder &MIRBuilder) const {
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assert(DstRegs.size() > 1 && "Nothing to unpack");
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const DataLayout &DL = MIRBuilder.getMF().getDataLayout();
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const DataLayout &DL = MIRBuilder.getDataLayout();
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SmallVector<LLT, 8> LLTs;
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SmallVector<uint64_t, 8> Offsets;
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