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[AMDGPU][llvm-mc] Fixes to support buffer atomics.
Fixes for MUBUF_Atomic instructions to make operand list valid: - For RTN insns, make a copy of $vdata_in operand as $vdata. - Do not add operand for GLC, it is hardcoded and comes as a token. Workaround to avoid adding multiple default optional operands. Tests added. Differential Revision: http://reviews.llvm.org/D20257 llvm-svn: 270049
This commit is contained in:
Artem Tamazov
parent
07314a2bff
commit
eea90f5cc7
@ -87,6 +87,17 @@ const char* const OpGsSymbolic[] = {
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using namespace llvm;
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// In some cases (e.g. buffer atomic instructions) MatchOperandParserImpl()
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// may invoke tryCustomParseOperand() multiple times with the same MCK value.
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// That leads to adding of the same "default" operand multiple times in a row,
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// which is wrong. The workaround adds only the 1st default operand, while for
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// the rest the "dummy" operands being added. The reason for dummies is that if
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// we just skip adding an operand, then parser would get stuck in endless loop.
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// Dummies shall be removed prior matching & emitting MCInsts.
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//
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// Comment out this macro to disable the workaround.
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#define WORKAROUND_USE_DUMMY_OPERANDS_INSTEAD_MUTIPLE_DEFAULT_OPERANDS
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namespace {
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struct OptionalOperand;
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@ -99,6 +110,9 @@ class AMDGPUOperand : public MCParsedAsmOperand {
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Immediate,
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Register,
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Expression
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#ifdef WORKAROUND_USE_DUMMY_OPERANDS_INSTEAD_MUTIPLE_DEFAULT_OPERANDS
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,Dummy
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#endif
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} Kind;
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SMLoc StartLoc, EndLoc;
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@ -204,6 +218,12 @@ public:
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}
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}
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#ifdef WORKAROUND_USE_DUMMY_OPERANDS_INSTEAD_MUTIPLE_DEFAULT_OPERANDS
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bool isDummy() const {
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return Kind == Dummy;
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}
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#endif
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bool isToken() const override {
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return Kind == Token;
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}
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@ -440,6 +460,11 @@ public:
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case Expression:
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OS << "<expr " << *Expr << '>';
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break;
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#ifdef WORKAROUND_USE_DUMMY_OPERANDS_INSTEAD_MUTIPLE_DEFAULT_OPERANDS
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case Dummy:
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OS << "<dummy>";
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break;
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#endif
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}
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}
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@ -490,6 +515,15 @@ public:
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return Op;
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}
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#ifdef WORKAROUND_USE_DUMMY_OPERANDS_INSTEAD_MUTIPLE_DEFAULT_OPERANDS
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static AMDGPUOperand::Ptr CreateDummy(SMLoc S) {
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auto Op = llvm::make_unique<AMDGPUOperand>(Dummy);
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Op->StartLoc = S;
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Op->EndLoc = S;
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return Op;
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}
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#endif
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bool isSWaitCnt() const;
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bool isHwreg() const;
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bool isSendMsg() const;
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@ -545,6 +579,7 @@ private:
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bool ParseSectionDirectiveHSARodataReadonlyAgent();
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bool AddNextRegisterToList(unsigned& Reg, unsigned& RegWidth, RegisterKind RegKind, unsigned Reg1, unsigned RegNum);
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bool ParseAMDGPURegister(RegisterKind& RegKind, unsigned& Reg, unsigned& RegNum, unsigned& RegWidth);
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void cvtMubufImpl(MCInst &Inst, const OperandVector &Operands, bool IsAtomic, bool IsAtomicReturn);
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public:
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enum AMDGPUMatchResultTy {
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@ -633,8 +668,9 @@ public:
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OperandMatchResultTy parseSOppBrTarget(OperandVector &Operands);
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AMDGPUOperand::Ptr defaultHwreg() const;
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void cvtMubuf(MCInst &Inst, const OperandVector &Operands);
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void cvtMubuf(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, false, false); }
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void cvtMubufAtomic(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, true, false); }
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void cvtMubufAtomicReturn(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, true, true); }
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AMDGPUOperand::Ptr defaultMubufOffset() const;
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AMDGPUOperand::Ptr defaultGLC() const;
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AMDGPUOperand::Ptr defaultSLC() const;
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@ -926,6 +962,17 @@ bool AMDGPUAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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bool MatchingInlineAsm) {
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MCInst Inst;
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#ifdef WORKAROUND_USE_DUMMY_OPERANDS_INSTEAD_MUTIPLE_DEFAULT_OPERANDS
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// Remove dummies prior matching. Iterate backwards becase vector::erase()
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// invalidates all iterators which refer after erase point.
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for (auto I = Operands.rbegin(), E = Operands.rend(); I != E; ) {
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auto X = I++;
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if (static_cast<AMDGPUOperand*>(X->get())->isDummy()) {
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Operands.erase(X.base() -1);
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}
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}
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#endif
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switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
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default: break;
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case Match_Success:
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@ -1430,6 +1477,25 @@ AMDGPUAsmParser::parseIntWithPrefix(const char *Prefix, OperandVector &Operands,
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}
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Operands.push_back(AMDGPUOperand::CreateImm(Value, S, ImmTy));
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#ifdef WORKAROUND_USE_DUMMY_OPERANDS_INSTEAD_MUTIPLE_DEFAULT_OPERANDS
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if (Value == Default && AddDefault) {
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// Reverse lookup in previously added operands (skip just added one)
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// for the first non-dummy operand. If it is of the same type,
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// then replace just added default operand with dummy.
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for (auto I = Operands.rbegin(), E = Operands.rend(); I != E; ++I) {
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if (I == Operands.rbegin())
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continue;
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if (static_cast<AMDGPUOperand*>(I->get())->isDummy())
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continue;
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if (static_cast<AMDGPUOperand*>(I->get())->isImmTy(ImmTy)) {
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Operands.pop_back();
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Operands.push_back(AMDGPUOperand::CreateDummy(S)); // invalidates iterators
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break;
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}
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}
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}
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#endif
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return MatchOperand_Success;
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}
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@ -2047,9 +2113,11 @@ AMDGPUOperand::Ptr AMDGPUAsmParser::defaultTFE() const {
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return AMDGPUOperand::CreateImm(0, SMLoc(), AMDGPUOperand::ImmTyTFE);
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}
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void AMDGPUAsmParser::cvtMubuf(MCInst &Inst,
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const OperandVector &Operands) {
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void AMDGPUAsmParser::cvtMubufImpl(MCInst &Inst,
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const OperandVector &Operands,
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bool IsAtomic, bool IsAtomicReturn) {
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OptionalImmIndexMap OptionalIdx;
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assert(IsAtomicReturn ? IsAtomic : true);
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for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
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AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
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@ -2077,8 +2145,16 @@ void AMDGPUAsmParser::cvtMubuf(MCInst &Inst,
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OptionalIdx[Op.getImmTy()] = i;
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}
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// Copy $vdata_in operand and insert as $vdata for MUBUF_Atomic RTN insns.
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if (IsAtomicReturn) {
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MCInst::iterator I = Inst.begin(); // $vdata_in is always at the beginning.
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Inst.insert(I, *I);
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}
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addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOffset);
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addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGLC);
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if (!IsAtomic) { // glc is hard-coded.
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addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGLC);
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}
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addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySLC);
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addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE);
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}
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@ -2836,7 +2836,7 @@ multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
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let mayStore = 1, mayLoad = 1, hasPostISelHook = 1, hasSideEffects = 1 in {
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// No return variants
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let glc = 0 in {
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let glc = 0, AsmMatchConverter = "cvtMubufAtomic" in {
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defm _ADDR64 : MUBUFAtomicAddr64_m <
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op, name#"_addr64", (outs),
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@ -2883,13 +2883,14 @@ multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
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// Variant that return values
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let glc = 1, Constraints = "$vdata = $vdata_in",
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AsmMatchConverter = "cvtMubufAtomicReturn",
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DisableEncoding = "$vdata_in" in {
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defm _RTN_ADDR64 : MUBUFAtomicAddr64_m <
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op, name#"_rtn_addr64", (outs rc:$vdata),
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(ins rc:$vdata_in, VReg_64:$vaddr, SReg_128:$srsrc,
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SCSrc_32:$soffset, offset:$offset, slc:$slc),
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name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#" glc"#"$slc",
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name#" $vdata, $vaddr, $srsrc, $soffset addr64$offset glc$slc",
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[(set vt:$vdata,
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(atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset,
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i16:$offset, i1:$slc), vt:$vdata_in))], 1
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@ -2899,7 +2900,7 @@ multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
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op, name#"_rtn_offset", (outs rc:$vdata),
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(ins rc:$vdata_in, SReg_128:$srsrc, SCSrc_32:$soffset,
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offset:$offset, slc:$slc),
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name#" $vdata, off, $srsrc, $soffset $offset glc$slc",
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name#" $vdata, off, $srsrc, $soffset$offset glc$slc",
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[(set vt:$vdata,
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(atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
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i1:$slc), vt:$vdata_in))], 1
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@ -2910,7 +2911,7 @@ multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
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op, name#"_rtn_offen", (outs rc:$vdata),
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(ins rc:$vdata_in, VGPR_32:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
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offset:$offset, slc:$slc),
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name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#" glc"#"$slc",
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name#" $vdata, $vaddr, $srsrc, $soffset offen$offset glc$slc",
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[], 1
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>;
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}
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@ -2920,7 +2921,7 @@ multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
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op, name#"_rtn_idxen", (outs rc:$vdata),
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(ins rc:$vdata_in, VGPR_32:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
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offset:$offset, slc:$slc),
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name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#" glc"#"$slc",
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name#" $vdata, $vaddr, $srsrc, $soffset idxen$offset glc$slc",
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[], 1
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>;
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}
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@ -2930,7 +2931,7 @@ multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
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op, name#"_rtn_bothen", (outs rc:$vdata),
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(ins rc:$vdata_in, VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
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offset:$offset, slc:$slc),
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name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#" glc"#"$slc",
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name#" $vdata, $vaddr, $srsrc, $soffset idxen offen$offset glc$slc",
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[], 1
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>;
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}
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@ -500,4 +500,205 @@ buffer_wbinvl1_vol
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// VI: buffer_wbinvl1_vol ; encoding: [0x00,0x00,0xfc,0xe0,0x00,0x00,0x00,0x00]
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// NOSI: error: instruction not supported on this GPU
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// TODO: Atomics
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//===----------------------------------------------------------------------===//
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// Atomics
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//===----------------------------------------------------------------------===//
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buffer_atomic_inc v1, v[2:3], s[8:11], 56 addr64
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// SICI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 addr64 ; encoding: [0x00,0x80,0xf0,0xe0,0x02,0x01,0x02,0xb8]
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// NOVI: error: instruction not supported on this GPU
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buffer_atomic_inc v1, v[2:3], s[8:11], s4 addr64
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// SICI: buffer_atomic_inc v1, v[2:3], s[8:11], s4 addr64 ; encoding: [0x00,0x80,0xf0,0xe0,0x02,0x01,0x02,0x04]
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// NOVI: error: instruction not supported on this GPU
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buffer_atomic_inc v1, v[2:3], s[8:11], 56 addr64 slc
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// SICI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 addr64 slc ; encoding: [0x00,0x80,0xf0,0xe0,0x02,0x01,0x42,0xb8]
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// NOVI: error: instruction not supported on this GPU
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buffer_atomic_inc v1, v[2:3], s[8:11], 56 addr64 offset:4
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// SICI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 addr64 offset:4 ; encoding: [0x04,0x80,0xf0,0xe0,0x02,0x01,0x02,0xb8]
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// NOVI: error: instruction not supported on this GPU
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buffer_atomic_inc v1, v[2:3], s[8:11], 56 addr64 offset:4 slc
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// SICI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 addr64 offset:4 slc ; encoding: [0x04,0x80,0xf0,0xe0,0x02,0x01,0x42,0xb8]
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// NOVI: error: instruction not supported on this GPU
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buffer_atomic_inc v1, off, s[8:11], 56
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// SICI: buffer_atomic_inc v1, off, s[8:11], 56 ; encoding: [0x00,0x00,0xf0,0xe0,0x00,0x01,0x02,0xb8]
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// VI: buffer_atomic_inc v1, off, s[8:11], 56 ; encoding: [0x00,0x00,0x2c,0xe1,0x00,0x01,0x02,0xb8]
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buffer_atomic_inc v1, off, s[8:11], 56 slc
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// SICI: buffer_atomic_inc v1, off, s[8:11], 56 slc ; encoding: [0x00,0x00,0xf0,0xe0,0x00,0x01,0x42,0xb8]
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// VI: buffer_atomic_inc v1, off, s[8:11], 56 slc ; encoding: [0x00,0x00,0x2e,0xe1,0x00,0x01,0x02,0xb8]
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buffer_atomic_inc v1, off, s[8:11], s4 slc
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// SICI: buffer_atomic_inc v1, off, s[8:11], s4 slc ; encoding: [0x00,0x00,0xf0,0xe0,0x00,0x01,0x42,0x04]
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// VI: buffer_atomic_inc v1, off, s[8:11], s4 slc ; encoding: [0x00,0x00,0x2e,0xe1,0x00,0x01,0x02,0x04]
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buffer_atomic_inc v1, off, s[8:11], 56 offset:4
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// SICI: buffer_atomic_inc v1, off, s[8:11], 56 offset:4 ; encoding: [0x04,0x00,0xf0,0xe0,0x00,0x01,0x02,0xb8]
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// VI: buffer_atomic_inc v1, off, s[8:11], 56 offset:4 ; encoding: [0x04,0x00,0x2c,0xe1,0x00,0x01,0x02,0xb8]
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buffer_atomic_inc v1, off, s[8:11], 56 offset:4 slc
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// SICI: buffer_atomic_inc v1, off, s[8:11], 56 offset:4 slc ; encoding: [0x04,0x00,0xf0,0xe0,0x00,0x01,0x42,0xb8]
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// VI: buffer_atomic_inc v1, off, s[8:11], 56 offset:4 slc ; encoding: [0x04,0x00,0x2e,0xe1,0x00,0x01,0x02,0xb8]
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buffer_atomic_inc v1, v2, s[8:11], 56 offen
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// SICI: buffer_atomic_inc v1, v2, s[8:11], 56 offen ; encoding: [0x00,0x10,0xf0,0xe0,0x02,0x01,0x02,0xb8]
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// VI: buffer_atomic_inc v1, v2, s[8:11], 56 offen ; encoding: [0x00,0x10,0x2c,0xe1,0x02,0x01,0x02,0xb8]
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buffer_atomic_inc v1, v2, s[8:11], 56 offen slc
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// SICI: buffer_atomic_inc v1, v2, s[8:11], 56 offen slc ; encoding: [0x00,0x10,0xf0,0xe0,0x02,0x01,0x42,0xb8]
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// VI: buffer_atomic_inc v1, v2, s[8:11], 56 offen slc ; encoding: [0x00,0x10,0x2e,0xe1,0x02,0x01,0x02,0xb8]
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buffer_atomic_inc v1, v2, s[8:11], 56 offen offset:4
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// SICI: buffer_atomic_inc v1, v2, s[8:11], 56 offen offset:4 ; encoding: [0x04,0x10,0xf0,0xe0,0x02,0x01,0x02,0xb8]
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// VI: buffer_atomic_inc v1, v2, s[8:11], 56 offen offset:4 ; encoding: [0x04,0x10,0x2c,0xe1,0x02,0x01,0x02,0xb8]
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buffer_atomic_inc v1, v2, s[8:11], s4 offen offset:4
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// SICI: buffer_atomic_inc v1, v2, s[8:11], s4 offen offset:4 ; encoding: [0x04,0x10,0xf0,0xe0,0x02,0x01,0x02,0x04]
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// VI: buffer_atomic_inc v1, v2, s[8:11], s4 offen offset:4 ; encoding: [0x04,0x10,0x2c,0xe1,0x02,0x01,0x02,0x04]
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buffer_atomic_inc v1, v2, s[8:11], 56 offen offset:4 slc
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// SICI: buffer_atomic_inc v1, v2, s[8:11], 56 offen offset:4 slc ; encoding: [0x04,0x10,0xf0,0xe0,0x02,0x01,0x42,0xb8]
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// VI: buffer_atomic_inc v1, v2, s[8:11], 56 offen offset:4 slc ; encoding: [0x04,0x10,0x2e,0xe1,0x02,0x01,0x02,0xb8]
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buffer_atomic_inc v1, v2, s[8:11], 56 idxen
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// SICI: buffer_atomic_inc v1, v2, s[8:11], 56 idxen ; encoding: [0x00,0x20,0xf0,0xe0,0x02,0x01,0x02,0xb8]
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// VI: buffer_atomic_inc v1, v2, s[8:11], 56 idxen ; encoding: [0x00,0x20,0x2c,0xe1,0x02,0x01,0x02,0xb8]
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buffer_atomic_inc v1, v2, s[8:11], 56 idxen slc
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// SICI: buffer_atomic_inc v1, v2, s[8:11], 56 idxen slc ; encoding: [0x00,0x20,0xf0,0xe0,0x02,0x01,0x42,0xb8]
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// VI: buffer_atomic_inc v1, v2, s[8:11], 56 idxen slc ; encoding: [0x00,0x20,0x2e,0xe1,0x02,0x01,0x02,0xb8]
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buffer_atomic_inc v1, v2, s[8:11], 56 idxen offset:4
|
||||
// SICI: buffer_atomic_inc v1, v2, s[8:11], 56 idxen offset:4 ; encoding: [0x04,0x20,0xf0,0xe0,0x02,0x01,0x02,0xb8]
|
||||
// VI: buffer_atomic_inc v1, v2, s[8:11], 56 idxen offset:4 ; encoding: [0x04,0x20,0x2c,0xe1,0x02,0x01,0x02,0xb8]
|
||||
|
||||
buffer_atomic_inc v1, v2, s[8:11], 56 idxen offset:4 slc
|
||||
// SICI: buffer_atomic_inc v1, v2, s[8:11], 56 idxen offset:4 slc ; encoding: [0x04,0x20,0xf0,0xe0,0x02,0x01,0x42,0xb8]
|
||||
// VI: buffer_atomic_inc v1, v2, s[8:11], 56 idxen offset:4 slc ; encoding: [0x04,0x20,0x2e,0xe1,0x02,0x01,0x02,0xb8]
|
||||
|
||||
buffer_atomic_inc v1, v2, s[8:11], s4 idxen offset:4 slc
|
||||
// SICI: buffer_atomic_inc v1, v2, s[8:11], s4 idxen offset:4 slc ; encoding: [0x04,0x20,0xf0,0xe0,0x02,0x01,0x42,0x04]
|
||||
// VI: buffer_atomic_inc v1, v2, s[8:11], s4 idxen offset:4 slc ; encoding: [0x04,0x20,0x2e,0xe1,0x02,0x01,0x02,0x04]
|
||||
|
||||
buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen
|
||||
// SICI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen ; encoding: [0x00,0x30,0xf0,0xe0,0x02,0x01,0x02,0xb8]
|
||||
// VI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen ; encoding: [0x00,0x30,0x2c,0xe1,0x02,0x01,0x02,0xb8]
|
||||
|
||||
buffer_atomic_inc v1, v[2:3], s[8:11], s4 idxen offen
|
||||
// SICI: buffer_atomic_inc v1, v[2:3], s[8:11], s4 idxen offen ; encoding: [0x00,0x30,0xf0,0xe0,0x02,0x01,0x02,0x04]
|
||||
// VI: buffer_atomic_inc v1, v[2:3], s[8:11], s4 idxen offen ; encoding: [0x00,0x30,0x2c,0xe1,0x02,0x01,0x02,0x04]
|
||||
|
||||
buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen slc
|
||||
// SICI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen slc ; encoding: [0x00,0x30,0xf0,0xe0,0x02,0x01,0x42,0xb8]
|
||||
// VI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen slc ; encoding: [0x00,0x30,0x2e,0xe1,0x02,0x01,0x02,0xb8]
|
||||
|
||||
buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen offset:4
|
||||
// SICI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen offset:4 ; encoding: [0x04,0x30,0xf0,0xe0,0x02,0x01,0x02,0xb8]
|
||||
// VI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen offset:4 ; encoding: [0x04,0x30,0x2c,0xe1,0x02,0x01,0x02,0xb8]
|
||||
|
||||
buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen offset:4 slc
|
||||
// SICI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen offset:4 slc ; encoding: [0x04,0x30,0xf0,0xe0,0x02,0x01,0x42,0xb8]
|
||||
// VI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen offset:4 slc ; encoding: [0x04,0x30,0x2e,0xe1,0x02,0x01,0x02,0xb8]
|
||||
|
||||
buffer_atomic_inc v1, v[2:3], s[8:11], 56 addr64 glc
|
||||
// SICI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 addr64 glc ; encoding: [0x00,0xc0,0xf0,0xe0,0x02,0x01,0x02,0xb8]
|
||||
// NOVI: error: instruction not supported on this GPU
|
||||
|
||||
buffer_atomic_inc v1, v[2:3], s[8:11], s4 addr64 glc
|
||||
// SICI: buffer_atomic_inc v1, v[2:3], s[8:11], s4 addr64 glc ; encoding: [0x00,0xc0,0xf0,0xe0,0x02,0x01,0x02,0x04]
|
||||
// NOVI: error: instruction not supported on this GPU
|
||||
|
||||
buffer_atomic_inc v1, v[2:3], s[8:11], 56 addr64 glc slc
|
||||
// SICI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 addr64 glc slc ; encoding: [0x00,0xc0,0xf0,0xe0,0x02,0x01,0x42,0xb8]
|
||||
// NOVI: error: instruction not supported on this GPU
|
||||
|
||||
buffer_atomic_inc v1, v[2:3], s[8:11], 56 addr64 offset:4 glc
|
||||
// SICI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 addr64 offset:4 glc ; encoding: [0x04,0xc0,0xf0,0xe0,0x02,0x01,0x02,0xb8]
|
||||
// NOVI: error: instruction not supported on this GPU
|
||||
|
||||
buffer_atomic_inc v1, v[2:3], s[8:11], 56 addr64 offset:4 glc slc
|
||||
// SICI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 addr64 offset:4 glc slc ; encoding: [0x04,0xc0,0xf0,0xe0,0x02,0x01,0x42,0xb8]
|
||||
// NOVI: error: instruction not supported on this GPU
|
||||
|
||||
buffer_atomic_inc v1, off, s[8:11], 56 glc
|
||||
// SICI: buffer_atomic_inc v1, off, s[8:11], 56 glc ; encoding: [0x00,0x40,0xf0,0xe0,0x00,0x01,0x02,0xb8]
|
||||
// VI: buffer_atomic_inc v1, off, s[8:11], 56 glc ; encoding: [0x00,0x40,0x2c,0xe1,0x00,0x01,0x02,0xb8]
|
||||
|
||||
buffer_atomic_inc v1, off, s[8:11], 56 glc slc
|
||||
// SICI: buffer_atomic_inc v1, off, s[8:11], 56 glc slc ; encoding: [0x00,0x40,0xf0,0xe0,0x00,0x01,0x42,0xb8]
|
||||
// VI: buffer_atomic_inc v1, off, s[8:11], 56 glc slc ; encoding: [0x00,0x40,0x2e,0xe1,0x00,0x01,0x02,0xb8]
|
||||
|
||||
buffer_atomic_inc v1, off, s[8:11], s4 glc slc
|
||||
// SICI: buffer_atomic_inc v1, off, s[8:11], s4 glc slc ; encoding: [0x00,0x40,0xf0,0xe0,0x00,0x01,0x42,0x04]
|
||||
// VI: buffer_atomic_inc v1, off, s[8:11], s4 glc slc ; encoding: [0x00,0x40,0x2e,0xe1,0x00,0x01,0x02,0x04]
|
||||
|
||||
buffer_atomic_inc v1, off, s[8:11], 56 offset:4 glc
|
||||
// SICI: buffer_atomic_inc v1, off, s[8:11], 56 offset:4 glc ; encoding: [0x04,0x40,0xf0,0xe0,0x00,0x01,0x02,0xb8]
|
||||
// VI: buffer_atomic_inc v1, off, s[8:11], 56 offset:4 glc ; encoding: [0x04,0x40,0x2c,0xe1,0x00,0x01,0x02,0xb8]
|
||||
|
||||
buffer_atomic_inc v1, off, s[8:11], 56 offset:4 glc slc
|
||||
// SICI: buffer_atomic_inc v1, off, s[8:11], 56 offset:4 glc slc ; encoding: [0x04,0x40,0xf0,0xe0,0x00,0x01,0x42,0xb8]
|
||||
// VI: buffer_atomic_inc v1, off, s[8:11], 56 offset:4 glc slc ; encoding: [0x04,0x40,0x2e,0xe1,0x00,0x01,0x02,0xb8]
|
||||
|
||||
buffer_atomic_inc v1, v2, s[8:11], 56 offen glc
|
||||
// SICI: buffer_atomic_inc v1, v2, s[8:11], 56 offen glc ; encoding: [0x00,0x50,0xf0,0xe0,0x02,0x01,0x02,0xb8]
|
||||
// VI: buffer_atomic_inc v1, v2, s[8:11], 56 offen glc ; encoding: [0x00,0x50,0x2c,0xe1,0x02,0x01,0x02,0xb8]
|
||||
|
||||
buffer_atomic_inc v1, v2, s[8:11], 56 offen glc slc
|
||||
// SICI: buffer_atomic_inc v1, v2, s[8:11], 56 offen glc slc ; encoding: [0x00,0x50,0xf0,0xe0,0x02,0x01,0x42,0xb8]
|
||||
// VI: buffer_atomic_inc v1, v2, s[8:11], 56 offen glc slc ; encoding: [0x00,0x50,0x2e,0xe1,0x02,0x01,0x02,0xb8]
|
||||
|
||||
buffer_atomic_inc v1, v2, s[8:11], 56 offen offset:4 glc
|
||||
// SICI: buffer_atomic_inc v1, v2, s[8:11], 56 offen offset:4 glc ; encoding: [0x04,0x50,0xf0,0xe0,0x02,0x01,0x02,0xb8]
|
||||
// VI: buffer_atomic_inc v1, v2, s[8:11], 56 offen offset:4 glc ; encoding: [0x04,0x50,0x2c,0xe1,0x02,0x01,0x02,0xb8]
|
||||
|
||||
buffer_atomic_inc v1, v2, s[8:11], s4 offen offset:4 glc
|
||||
// SICI: buffer_atomic_inc v1, v2, s[8:11], s4 offen offset:4 glc ; encoding: [0x04,0x50,0xf0,0xe0,0x02,0x01,0x02,0x04]
|
||||
// VI: buffer_atomic_inc v1, v2, s[8:11], s4 offen offset:4 glc ; encoding: [0x04,0x50,0x2c,0xe1,0x02,0x01,0x02,0x04]
|
||||
|
||||
buffer_atomic_inc v1, v2, s[8:11], 56 offen offset:4 glc slc
|
||||
// SICI: buffer_atomic_inc v1, v2, s[8:11], 56 offen offset:4 glc slc ; encoding: [0x04,0x50,0xf0,0xe0,0x02,0x01,0x42,0xb8]
|
||||
// VI: buffer_atomic_inc v1, v2, s[8:11], 56 offen offset:4 glc slc ; encoding: [0x04,0x50,0x2e,0xe1,0x02,0x01,0x02,0xb8]
|
||||
|
||||
buffer_atomic_inc v1, v2, s[8:11], 56 idxen glc
|
||||
// SICI: buffer_atomic_inc v1, v2, s[8:11], 56 idxen glc ; encoding: [0x00,0x60,0xf0,0xe0,0x02,0x01,0x02,0xb8]
|
||||
// VI: buffer_atomic_inc v1, v2, s[8:11], 56 idxen glc ; encoding: [0x00,0x60,0x2c,0xe1,0x02,0x01,0x02,0xb8]
|
||||
|
||||
buffer_atomic_inc v1, v2, s[8:11], 56 idxen glc slc
|
||||
// SICI: buffer_atomic_inc v1, v2, s[8:11], 56 idxen glc slc ; encoding: [0x00,0x60,0xf0,0xe0,0x02,0x01,0x42,0xb8]
|
||||
// VI: buffer_atomic_inc v1, v2, s[8:11], 56 idxen glc slc ; encoding: [0x00,0x60,0x2e,0xe1,0x02,0x01,0x02,0xb8]
|
||||
|
||||
buffer_atomic_inc v1, v2, s[8:11], 56 idxen offset:4 glc
|
||||
// SICI: buffer_atomic_inc v1, v2, s[8:11], 56 idxen offset:4 glc ; encoding: [0x04,0x60,0xf0,0xe0,0x02,0x01,0x02,0xb8]
|
||||
// VI: buffer_atomic_inc v1, v2, s[8:11], 56 idxen offset:4 glc ; encoding: [0x04,0x60,0x2c,0xe1,0x02,0x01,0x02,0xb8]
|
||||
|
||||
buffer_atomic_inc v1, v2, s[8:11], 56 idxen offset:4 glc slc
|
||||
// SICI: buffer_atomic_inc v1, v2, s[8:11], 56 idxen offset:4 glc slc ; encoding: [0x04,0x60,0xf0,0xe0,0x02,0x01,0x42,0xb8]
|
||||
// VI: buffer_atomic_inc v1, v2, s[8:11], 56 idxen offset:4 glc slc ; encoding: [0x04,0x60,0x2e,0xe1,0x02,0x01,0x02,0xb8]
|
||||
|
||||
buffer_atomic_inc v1, v2, s[8:11], s4 idxen offset:4 glc slc
|
||||
// SICI: buffer_atomic_inc v1, v2, s[8:11], s4 idxen offset:4 glc slc ; encoding: [0x04,0x60,0xf0,0xe0,0x02,0x01,0x42,0x04]
|
||||
// VI: buffer_atomic_inc v1, v2, s[8:11], s4 idxen offset:4 glc slc ; encoding: [0x04,0x60,0x2e,0xe1,0x02,0x01,0x02,0x04]
|
||||
|
||||
buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen glc
|
||||
// SICI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen glc ; encoding: [0x00,0x70,0xf0,0xe0,0x02,0x01,0x02,0xb8]
|
||||
// VI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen glc ; encoding: [0x00,0x70,0x2c,0xe1,0x02,0x01,0x02,0xb8]
|
||||
|
||||
buffer_atomic_inc v1, v[2:3], s[8:11], s4 idxen offen glc
|
||||
// SICI: buffer_atomic_inc v1, v[2:3], s[8:11], s4 idxen offen glc ; encoding: [0x00,0x70,0xf0,0xe0,0x02,0x01,0x02,0x04]
|
||||
// VI: buffer_atomic_inc v1, v[2:3], s[8:11], s4 idxen offen glc ; encoding: [0x00,0x70,0x2c,0xe1,0x02,0x01,0x02,0x04]
|
||||
|
||||
buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen glc slc
|
||||
// SICI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen glc slc ; encoding: [0x00,0x70,0xf0,0xe0,0x02,0x01,0x42,0xb8]
|
||||
// VI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen glc slc ; encoding: [0x00,0x70,0x2e,0xe1,0x02,0x01,0x02,0xb8]
|
||||
|
||||
buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen offset:4 glc
|
||||
// SICI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen offset:4 glc ; encoding: [0x04,0x70,0xf0,0xe0,0x02,0x01,0x02,0xb8]
|
||||
// VI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen offset:4 glc ; encoding: [0x04,0x70,0x2c,0xe1,0x02,0x01,0x02,0xb8]
|
||||
|
||||
buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen offset:4 glc slc
|
||||
// SICI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen offset:4 glc slc ; encoding: [0x04,0x70,0xf0,0xe0,0x02,0x01,0x42,0xb8]
|
||||
// VI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen offset:4 glc slc ; encoding: [0x04,0x70,0x2e,0xe1,0x02,0x01,0x02,0xb8]
|
||||
|
||||
@ -138,3 +138,7 @@ s_setpc_b64 [ttmp2,ttmp3]
|
||||
v_readfirstlane_b32 ttmp8, v1
|
||||
// SICI: v_readfirstlane_b32 ttmp8, v1 ; encoding: [0x01,0x05,0xf0,0x7e]
|
||||
// VI: v_readfirstlane_b32 ttmp8, v1 ; encoding: [0x01,0x05,0xf0,0x7e]
|
||||
|
||||
buffer_atomic_inc v1, off, ttmp[8:11], 56 glc
|
||||
// SICI: buffer_atomic_inc v1, off, ttmp[8:11], 56 glc ; encoding: [0x00,0x40,0xf0,0xe0,0x00,0x01,0x1e,0xb8]
|
||||
// VI: buffer_atomic_inc v1, off, ttmp[8:11], 56 glc ; encoding: [0x00,0x40,0x2c,0xe1,0x00,0x01,0x1e,0xb8]
|
||||
|
||||
@ -234,3 +234,122 @@
|
||||
# VI: buffer_wbinvl1_vol ; encoding: [0x00,0x00,0xfc,0xe0,0x00,0x00,0x00,0x00]
|
||||
0x00 0x00 0xfc 0xe0 0x00 0x00 0x00 0x00
|
||||
|
||||
# VI: buffer_atomic_inc v1, off, s[8:11], 56 ; encoding: [0x00,0x00,0x2c,0xe1,0x00,0x01,0x02,0xb8]
|
||||
0x00 0x00 0x2c 0xe1 0x00 0x01 0x02 0xb8
|
||||
|
||||
# VI: buffer_atomic_inc v1, off, s[8:11], 56 slc ; encoding: [0x00,0x00,0x2e,0xe1,0x00,0x01,0x02,0xb8]
|
||||
0x00 0x00 0x2e 0xe1 0x00 0x01 0x02 0xb8
|
||||
|
||||
# VI: buffer_atomic_inc v1, off, s[8:11], s4 slc ; encoding: [0x00,0x00,0x2e,0xe1,0x00,0x01,0x02,0x04]
|
||||
0x00 0x00 0x2e 0xe1 0x00 0x01 0x02 0x04
|
||||
|
||||
# VI: buffer_atomic_inc v1, off, s[8:11], 56 offset:4 ; encoding: [0x04,0x00,0x2c,0xe1,0x00,0x01,0x02,0xb8]
|
||||
0x04 0x00 0x2c 0xe1 0x00 0x01 0x02 0xb8
|
||||
|
||||
# VI: buffer_atomic_inc v1, off, s[8:11], 56 offset:4 slc ; encoding: [0x04,0x00,0x2e,0xe1,0x00,0x01,0x02,0xb8]
|
||||
0x04 0x00 0x2e 0xe1 0x00 0x01 0x02 0xb8
|
||||
|
||||
# VI: buffer_atomic_inc v1, v2, s[8:11], 56 offen ; encoding: [0x00,0x10,0x2c,0xe1,0x02,0x01,0x02,0xb8]
|
||||
0x00 0x10 0x2c 0xe1 0x02 0x01 0x02 0xb8
|
||||
|
||||
# VI: buffer_atomic_inc v1, v2, s[8:11], 56 offen slc ; encoding: [0x00,0x10,0x2e,0xe1,0x02,0x01,0x02,0xb8]
|
||||
0x00 0x10 0x2e 0xe1 0x02 0x01 0x02 0xb8
|
||||
|
||||
# VI: buffer_atomic_inc v1, v2, s[8:11], 56 offen offset:4 ; encoding: [0x04,0x10,0x2c,0xe1,0x02,0x01,0x02,0xb8]
|
||||
0x04 0x10 0x2c 0xe1 0x02 0x01 0x02 0xb8
|
||||
|
||||
# VI: buffer_atomic_inc v1, v2, s[8:11], s4 offen offset:4 ; encoding: [0x04,0x10,0x2c,0xe1,0x02,0x01,0x02,0x04]
|
||||
0x04 0x10 0x2c 0xe1 0x02 0x01 0x02 0x04
|
||||
|
||||
# VI: buffer_atomic_inc v1, v2, s[8:11], 56 offen offset:4 slc ; encoding: [0x04,0x10,0x2e,0xe1,0x02,0x01,0x02,0xb8]
|
||||
0x04 0x10 0x2e 0xe1 0x02 0x01 0x02 0xb8
|
||||
|
||||
# VI: buffer_atomic_inc v1, v2, s[8:11], 56 idxen ; encoding: [0x00,0x20,0x2c,0xe1,0x02,0x01,0x02,0xb8]
|
||||
0x00 0x20 0x2c 0xe1 0x02 0x01 0x02 0xb8
|
||||
|
||||
# VI: buffer_atomic_inc v1, v2, s[8:11], 56 idxen slc ; encoding: [0x00,0x20,0x2e,0xe1,0x02,0x01,0x02,0xb8]
|
||||
0x00 0x20 0x2e 0xe1 0x02 0x01 0x02 0xb8
|
||||
|
||||
# VI: buffer_atomic_inc v1, v2, s[8:11], 56 idxen offset:4 ; encoding: [0x04,0x20,0x2c,0xe1,0x02,0x01,0x02,0xb8]
|
||||
0x04 0x20 0x2c 0xe1 0x02 0x01 0x02 0xb8
|
||||
|
||||
# VI: buffer_atomic_inc v1, v2, s[8:11], 56 idxen offset:4 slc ; encoding: [0x04,0x20,0x2e,0xe1,0x02,0x01,0x02,0xb8]
|
||||
0x04 0x20 0x2e 0xe1 0x02 0x01 0x02 0xb8
|
||||
|
||||
# VI: buffer_atomic_inc v1, v2, s[8:11], s4 idxen offset:4 slc ; encoding: [0x04,0x20,0x2e,0xe1,0x02,0x01,0x02,0x04]
|
||||
0x04 0x20 0x2e 0xe1 0x02 0x01 0x02 0x04
|
||||
|
||||
# VI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen ; encoding: [0x00,0x30,0x2c,0xe1,0x02,0x01,0x02,0xb8]
|
||||
0x00 0x30 0x2c 0xe1 0x02 0x01 0x02 0xb8
|
||||
|
||||
# VI: buffer_atomic_inc v1, v[2:3], s[8:11], s4 idxen offen ; encoding: [0x00,0x30,0x2c,0xe1,0x02,0x01,0x02,0x04]
|
||||
0x00 0x30 0x2c 0xe1 0x02 0x01 0x02 0x04
|
||||
|
||||
# VI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen slc ; encoding: [0x00,0x30,0x2e,0xe1,0x02,0x01,0x02,0xb8]
|
||||
0x00 0x30 0x2e 0xe1 0x02 0x01 0x02 0xb8
|
||||
|
||||
# VI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen offset:4 ; encoding: [0x04,0x30,0x2c,0xe1,0x02,0x01,0x02,0xb8]
|
||||
0x04 0x30 0x2c 0xe1 0x02 0x01 0x02 0xb8
|
||||
|
||||
# VI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen offset:4 slc ; encoding: [0x04,0x30,0x2e,0xe1,0x02,0x01,0x02,0xb8]
|
||||
0x04 0x30 0x2e 0xe1 0x02 0x01 0x02 0xb8
|
||||
|
||||
# VI: buffer_atomic_inc v1, off, s[8:11], 56 glc ; encoding: [0x00,0x40,0x2c,0xe1,0x00,0x01,0x02,0xb8]
|
||||
0x00 0x40 0x2c 0xe1 0x00 0x01 0x02 0xb8
|
||||
|
||||
# VI: buffer_atomic_inc v1, off, s[8:11], 56 glc slc ; encoding: [0x00,0x40,0x2e,0xe1,0x00,0x01,0x02,0xb8]
|
||||
0x00 0x40 0x2e 0xe1 0x00 0x01 0x02 0xb8
|
||||
|
||||
# VI: buffer_atomic_inc v1, off, s[8:11], s4 glc slc ; encoding: [0x00,0x40,0x2e,0xe1,0x00,0x01,0x02,0x04]
|
||||
0x00 0x40 0x2e 0xe1 0x00 0x01 0x02 0x04
|
||||
|
||||
# VI: buffer_atomic_inc v1, off, s[8:11], 56 offset:4 glc ; encoding: [0x04,0x40,0x2c,0xe1,0x00,0x01,0x02,0xb8]
|
||||
0x04 0x40 0x2c 0xe1 0x00 0x01 0x02 0xb8
|
||||
|
||||
# VI: buffer_atomic_inc v1, off, s[8:11], 56 offset:4 glc slc ; encoding: [0x04,0x40,0x2e,0xe1,0x00,0x01,0x02,0xb8]
|
||||
0x04 0x40 0x2e 0xe1 0x00 0x01 0x02 0xb8
|
||||
|
||||
# VI: buffer_atomic_inc v1, v2, s[8:11], 56 offen glc ; encoding: [0x00,0x50,0x2c,0xe1,0x02,0x01,0x02,0xb8]
|
||||
0x00 0x50 0x2c 0xe1 0x02 0x01 0x02 0xb8
|
||||
|
||||
# VI: buffer_atomic_inc v1, v2, s[8:11], 56 offen glc slc ; encoding: [0x00,0x50,0x2e,0xe1,0x02,0x01,0x02,0xb8]
|
||||
0x00 0x50 0x2e 0xe1 0x02 0x01 0x02 0xb8
|
||||
|
||||
# VI: buffer_atomic_inc v1, v2, s[8:11], 56 offen offset:4 glc ; encoding: [0x04,0x50,0x2c,0xe1,0x02,0x01,0x02,0xb8]
|
||||
0x04 0x50 0x2c 0xe1 0x02 0x01 0x02 0xb8
|
||||
|
||||
# VI: buffer_atomic_inc v1, v2, s[8:11], s4 offen offset:4 glc ; encoding: [0x04,0x50,0x2c,0xe1,0x02,0x01,0x02,0x04]
|
||||
0x04 0x50 0x2c 0xe1 0x02 0x01 0x02 0x04
|
||||
|
||||
# VI: buffer_atomic_inc v1, v2, s[8:11], 56 offen offset:4 glc slc ; encoding: [0x04,0x50,0x2e,0xe1,0x02,0x01,0x02,0xb8]
|
||||
0x04 0x50 0x2e 0xe1 0x02 0x01 0x02 0xb8
|
||||
|
||||
# VI: buffer_atomic_inc v1, v2, s[8:11], 56 idxen glc ; encoding: [0x00,0x60,0x2c,0xe1,0x02,0x01,0x02,0xb8]
|
||||
0x00 0x60 0x2c 0xe1 0x02 0x01 0x02 0xb8
|
||||
|
||||
# VI: buffer_atomic_inc v1, v2, s[8:11], 56 idxen glc slc ; encoding: [0x00,0x60,0x2e,0xe1,0x02,0x01,0x02,0xb8]
|
||||
0x00 0x60 0x2e 0xe1 0x02 0x01 0x02 0xb8
|
||||
|
||||
# VI: buffer_atomic_inc v1, v2, s[8:11], 56 idxen offset:4 glc ; encoding: [0x04,0x60,0x2c,0xe1,0x02,0x01,0x02,0xb8]
|
||||
0x04 0x60 0x2c 0xe1 0x02 0x01 0x02 0xb8
|
||||
|
||||
# VI: buffer_atomic_inc v1, v2, s[8:11], 56 idxen offset:4 glc slc ; encoding: [0x04,0x60,0x2e,0xe1,0x02,0x01,0x02,0xb8]
|
||||
0x04 0x60 0x2e 0xe1 0x02 0x01 0x02 0xb8
|
||||
|
||||
# VI: buffer_atomic_inc v1, v2, s[8:11], s4 idxen offset:4 glc slc ; encoding: [0x04,0x60,0x2e,0xe1,0x02,0x01,0x02,0x04]
|
||||
0x04 0x60 0x2e 0xe1 0x02 0x01 0x02 0x04
|
||||
|
||||
# VI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen glc ; encoding: [0x00,0x70,0x2c,0xe1,0x02,0x01,0x02,0xb8]
|
||||
0x00 0x70 0x2c 0xe1 0x02 0x01 0x02 0xb8
|
||||
|
||||
# VI: buffer_atomic_inc v1, v[2:3], s[8:11], s4 idxen offen glc ; encoding: [0x00,0x70,0x2c,0xe1,0x02,0x01,0x02,0x04]
|
||||
0x00 0x70 0x2c 0xe1 0x02 0x01 0x02 0x04
|
||||
|
||||
# VI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen glc slc ; encoding: [0x00,0x70,0x2e,0xe1,0x02,0x01,0x02,0xb8]
|
||||
0x00 0x70 0x2e 0xe1 0x02 0x01 0x02 0xb8
|
||||
|
||||
# VI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen offset:4 glc ; encoding: [0x04,0x70,0x2c,0xe1,0x02,0x01,0x02,0xb8]
|
||||
0x04 0x70 0x2c 0xe1 0x02 0x01 0x02 0xb8
|
||||
|
||||
# VI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen offset:4 glc slc ; encoding: [0x04,0x70,0x2e,0xe1,0x02,0x01,0x02,0xb8]
|
||||
0x04 0x70 0x2e 0xe1 0x02 0x01 0x02 0xb8
|
||||
|
||||
Loading…
Reference in New Issue
Block a user