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[AVR] Use the short form of 'clr <reg>'

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r318895 made it so that the simpler instruction aliases are printed
rather than their expanded form.

llvm-svn: 318954
This commit is contained in:
Dylan McKay 2017-11-24 15:36:43 +00:00
parent 0b9cc4f48d
commit eebdc67e4c
4 changed files with 15 additions and 14 deletions
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4
test/CodeGen/AVR/interrupts.ll
View File

@ -7,7 +7,7 @@ define avr_intrcc void @interrupt_handler() {
; CHECK-NEXT: push r1
; CHECK-NEXT: in r0, 63
; CHECK-NEXT: push r0
; CHECK: eor r0, r0
; CHECK: clr r0
; CHECK: pop r0
; CHECK-NEXT: out 63, r0
; CHECK-NEXT: pop r1
@ -23,7 +23,7 @@ define avr_signalcc void @signal_handler() {
; CHECK-NEXT: push r1
; CHECK-NEXT: in r0, 63
; CHECK-NEXT: push r0
; CHECK: eor r0, r0
; CHECK: clr r0
; CHECK: pop r0
; CHECK-NEXT: out 63, r0
; CHECK-NEXT: pop r1

6
test/CodeGen/AVR/mul.ll
View File

@ -3,7 +3,7 @@
define i8 @mult8(i8 %a, i8 %b) {
; CHECK-LABEL: mult8:
; CHECK: muls r22, r24
; CHECK: eor r1, r1
; CHECK: clr r1
; CHECK: mov r24, r0
%mul = mul i8 %b, %a
ret i8 %mul
@ -16,10 +16,10 @@ define i16 @mult16(i16 %a, i16 %b) {
; CHECK: mul r22, r24
; CHECK: mov r19, r0
; CHECK: mov r20, r1
; CHECK: eor r1, r1
; CHECK: clr r1
; CHECK: add r20, r18
; CHECK: muls r23, r24
; CHECK: eor r1, r1
; CHECK: clr r1
; CHECK: mov r22, r0
; CHECK: add r22, r20
; :TODO: finish after reworking shift instructions

10
test/CodeGen/AVR/zext.ll
View File

@ -4,27 +4,27 @@
; eor R25, R25
define i16 @zext1(i8 %x) {
; CHECK-LABEL: zext1:
; CHECK: eor r25, r25
; CHECK: clr r25
%1 = zext i8 %x to i16
ret i16 %1
}
; zext R25:R24, R20
; mov R24, R20
; eor R25, R25
; clr R25
define i16 @zext2(i8 %x, i8 %y) {
; CHECK-LABEL: zext2:
; CHECK: mov r24, r22
; CHECK: eor r25, r25
; CHECK: clr r25
%1 = zext i8 %y to i16
ret i16 %1
}
; zext R25:R24, R24
; eor R25, R25
; clr R25
define i16 @zext_i1(i1 %x) {
; CHECK-LABEL: zext_i1:
; CHECK: eor r25, r25
; CHECK: clr r25
%1 = zext i1 %x to i16
ret i16 %1
}

9
test/MC/AVR/inst-clr.s
View File

@ -8,7 +8,8 @@ foo:
clr r5
clr r0
; CHECK: eor r2, r2 ; encoding: [0x22,0x24]
; CHECK: eor r12, r12 ; encoding: [0xcc,0x24]
; CHECK: eor r5, r5 ; encoding: [0x55,0x24]
; CHECK: eor r0, r0 ; encoding: [0x00,0x24]
; CHECK: clr r2 ; encoding: [0x22,0x24]
; CHECK: clr r12 ; encoding: [0xcc,0x24]
; CHECK: clr r5 ; encoding: [0x55,0x24]
; CHECK: clr r0 ; encoding: [0x00,0x24]