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[ARM] Always enable UseAA in the arm backend
This feature controls whether AA is used into the backend, and was previously turned on for certain subtargets to help create less constrained scheduling graphs. This patch turns it on for all subtargets, so that they can all make use of the extra information to produce better code. Differential Revision: https://reviews.llvm.org/D69796
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@ -415,10 +415,6 @@ def FeatureNoPostRASched : SubtargetFeature<"disable-postra-scheduler",
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"DisablePostRAScheduler", "true",
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"Don't schedule again after register allocation">;
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// Enable use of alias analysis during code generation
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def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
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"Use alias analysis during codegen">;
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// Armv8.5-A extensions
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def FeatureSB : SubtargetFeature<"sb", "HasSB", "true",
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@ -584,7 +580,6 @@ def ProcExynos : SubtargetFeature<"exynos", "ARMProcFamily", "Exynos",
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"Samsung Exynos processors",
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[FeatureZCZeroing,
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FeatureUseWideStrideVFP,
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FeatureUseAA,
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FeatureSplatVFPToNeon,
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FeatureSlowVGETLNi32,
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FeatureSlowVDUP32,
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@ -1067,13 +1062,11 @@ def : ProcessorModel<"cortex-m3", CortexM4Model, [ARMv7m,
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ProcM3,
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FeaturePrefLoopAlign32,
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FeatureUseMISched,
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FeatureUseAA,
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FeatureHasNoBranchPredictor]>;
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def : ProcessorModel<"sc300", CortexM4Model, [ARMv7m,
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ProcM3,
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FeatureUseMISched,
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FeatureUseAA,
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FeatureHasNoBranchPredictor]>;
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def : ProcessorModel<"cortex-m4", CortexM4Model, [ARMv7em,
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@ -1081,7 +1074,6 @@ def : ProcessorModel<"cortex-m4", CortexM4Model, [ARMv7em,
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FeaturePrefLoopAlign32,
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FeatureHasSlowFPVMLx,
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FeatureUseMISched,
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FeatureUseAA,
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FeatureHasNoBranchPredictor]>;
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def : ProcNoItin<"cortex-m7", [ARMv7em,
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@ -1096,7 +1088,6 @@ def : ProcessorModel<"cortex-m33", CortexM4Model, [ARMv8mMainline,
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FeaturePrefLoopAlign32,
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FeatureHasSlowFPVMLx,
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FeatureUseMISched,
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FeatureUseAA,
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FeatureHasNoBranchPredictor]>;
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def : ProcessorModel<"cortex-m35p", CortexM4Model, [ARMv8mMainline,
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@ -1105,7 +1096,6 @@ def : ProcessorModel<"cortex-m35p", CortexM4Model, [ARMv8mMainline,
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FeaturePrefLoopAlign32,
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FeatureHasSlowFPVMLx,
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FeatureUseMISched,
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FeatureUseAA,
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FeatureHasNoBranchPredictor]>;
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@ -1213,8 +1203,7 @@ def : ProcNoItin<"kryo", [ARMv8a, ProcKryo,
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def : ProcessorModel<"cortex-r52", CortexR52Model, [ARMv8r, ProcR52,
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FeatureUseMISched,
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FeatureFPAO,
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FeatureUseAA]>;
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FeatureFPAO]>;
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//===----------------------------------------------------------------------===//
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// Register File Description
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@ -223,9 +223,6 @@ protected:
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/// register allocation.
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bool DisablePostRAScheduler = false;
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/// UseAA - True if using AA during codegen (DAGCombine, MISched, etc)
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bool UseAA = false;
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/// HasThumb2 - True if Thumb2 instructions are supported.
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bool HasThumb2 = false;
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@ -811,7 +808,7 @@ public:
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/// Enable use of alias analysis during code generation (during MI
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/// scheduling, DAGCombine, etc.).
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bool useAA() const override { return UseAA; }
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bool useAA() const override { return true; }
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// enableAtomicExpand- True if we need to expand our atomics.
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bool enableAtomicExpand() const override;
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@ -36,10 +36,10 @@ entry:
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; CHECKV6-NEXT: ldr [[SB:r[0-7]]],
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; CHECKV6-NEXT: ldm{{(\.w)?}} [[LB]]!,
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; CHECKV6-NEXT: stm{{(\.w)?}} [[SB]]!,
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; CHECKV6-NEXT: ldrh{{(\.w)?}} {{.*}}, {{\[}}[[LB]]]
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; CHECKV6-NEXT: ldrb{{(\.w)?}} {{.*}}, {{\[}}[[LB]], #2]
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; CHECKV6-NEXT: strb{{(\.w)?}} {{.*}}, {{\[}}[[SB]], #2]
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; CHECKV6-NEXT: strh{{(\.w)?}} {{.*}}, {{\[}}[[SB]]]
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; CHECKV6-DAG: ldrh{{(\.w)?}} {{.*}}, {{\[}}[[LB]]]
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; CHECKV6-DAG: ldrb{{(\.w)?}} {{.*}}, {{\[}}[[LB]], #2]
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; CHECKV6-DAG: strb{{(\.w)?}} {{.*}}, {{\[}}[[SB]], #2]
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; CHECKV6-DAG: strh{{(\.w)?}} {{.*}}, {{\[}}[[SB]]]
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; CHECKV7: movt [[LB:[rl0-9]+]], :upper16:d
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; CHECKV7-NEXT: movt [[SB:[rl0-9]+]], :upper16:s
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; CHECKV7: ldr{{(\.w)?}} {{.*}}, {{\[}}[[LB]], #11]
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@ -57,14 +57,14 @@ entry:
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; Epilogue
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; --------
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; CHECK-V4T: ldr [[POP:r[4567]]], [sp, #16]
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; CHECK-V4T: ldr [[POP:r[4567]]], [sp, #12]
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; CHECK-V4T-NEXT: mov lr, [[POP]]
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; CHECK-V4T-NEXT: pop {[[SAVED]]}
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; CHECK-V4T-NEXT: add sp, #16
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; CHECK-V4T-NEXT: bx lr
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; CHECK-V5T: lsls r4
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; CHECK-V5T-NEXT: mov sp, r4
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; CHECK-V5T: ldr [[POP:r[4567]]], [sp, #16]
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; CHECK-V5T: ldr [[POP:r[4567]]], [sp, #12]
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; CHECK-V5T-NEXT: mov lr, [[POP]]
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; CHECK-V5T-NEXT: pop {[[SAVED]]}
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; CHECK-V5T-NEXT: add sp, #16
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@ -7,9 +7,9 @@
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; CHECK-LABEL: test
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; GENERIC: ldr
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; GENERIC: str
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; GENERIC: ldr
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; GENERIC: str
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; GENERIC: str
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; USEAA: ldr
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; USEAA: ldr
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; USEAA: str
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@ -1,13 +1,27 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -pre-RA-sched=source | FileCheck %s
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; Test that we correctly align elements when using va_arg
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; CHECK-LABEL: test1:
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; CHECK-NOT: bfc
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; CHECK: add [[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7
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; CHECK: bic {{(r[0-9]+)|(lr)}}, [[REG]], #7
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; CHECK-NOT: bic
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define i64 @test1(i32 %i, ...) nounwind optsize {
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; CHECK-LABEL: test1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .pad #12
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; CHECK-NEXT: sub sp, sp, #12
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; CHECK-NEXT: .pad #4
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; CHECK-NEXT: sub sp, sp, #4
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; CHECK-NEXT: add r0, sp, #4
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; CHECK-NEXT: stmib sp, {r1, r2, r3}
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; CHECK-NEXT: add r0, r0, #7
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; CHECK-NEXT: bic r1, r0, #7
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; CHECK-NEXT: orr r2, r1, #4
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; CHECK-NEXT: str r2, [sp]
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; CHECK-NEXT: ldr r0, [r1]
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; CHECK-NEXT: add r2, r2, #4
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; CHECK-NEXT: str r2, [sp]
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; CHECK-NEXT: ldr r1, [r1, #4]
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; CHECK-NEXT: add sp, sp, #4
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; CHECK-NEXT: add sp, sp, #12
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; CHECK-NEXT: bx lr
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entry:
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%g = alloca i8*, align 4
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%g1 = bitcast i8** %g to i8*
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@ -17,14 +31,25 @@ entry:
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ret i64 %0
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}
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; CHECK-LABEL: test2:
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; CHECK-NOT: bfc
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; CHECK: add [[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7
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; CHECK: bic {{(r[0-9]+)|(lr)}}, [[REG]], #7
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; CHECK-NOT: bic
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; CHECK: bx lr
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define double @test2(i32 %a, i32* %b, ...) nounwind optsize {
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; CHECK-LABEL: test2:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .pad #8
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; CHECK-NEXT: sub sp, sp, #8
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; CHECK-NEXT: .pad #4
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; CHECK-NEXT: sub sp, sp, #4
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; CHECK-NEXT: add r0, sp, #4
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; CHECK-NEXT: stmib sp, {r2, r3}
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; CHECK-NEXT: add r0, r0, #11
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; CHECK-NEXT: bic r0, r0, #3
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; CHECK-NEXT: str r2, [r1]
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; CHECK-NEXT: add r1, r0, #8
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; CHECK-NEXT: str r1, [sp]
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; CHECK-NEXT: vldr d16, [r0]
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: add sp, sp, #4
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; CHECK-NEXT: add sp, sp, #8
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; CHECK-NEXT: bx lr
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entry:
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%ap = alloca i8*, align 4 ; <i8**> [#uses=3]
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%ap1 = bitcast i8** %ap to i8* ; <i8*> [#uses=2]
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