mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2025-02-01 05:01:59 +01:00
AMDGPU: Don't fold immediate if clamp/omod are set
Doesn't fix any practical problems because clamp/omod are currently folded after peephole optimizer. llvm-svn: 296375
This commit is contained in:
Matt Arsenault
parent
e195aa940b
commit
eed7a831ed
@ -1537,15 +1537,10 @@ bool SIInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
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if (Opc == AMDGPU::V_MAD_F32 || Opc == AMDGPU::V_MAC_F32_e64 ||
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Opc == AMDGPU::V_MAD_F16 || Opc == AMDGPU::V_MAC_F16_e64) {
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bool IsF32 = Opc == AMDGPU::V_MAD_F32 || Opc == AMDGPU::V_MAC_F32_e64;
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// Don't fold if we are using source modifiers. The new VOP2 instructions
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// don't have them.
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if (hasModifiersSet(UseMI, AMDGPU::OpName::src0_modifiers) ||
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hasModifiersSet(UseMI, AMDGPU::OpName::src1_modifiers) ||
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hasModifiersSet(UseMI, AMDGPU::OpName::src2_modifiers)) {
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// Don't fold if we are using source or output modifiers. The new VOP2
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// instructions don't have them.
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if (hasAnyModifiersSet(UseMI))
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return false;
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}
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const MachineOperand &ImmOp = DefMI.getOperand(1);
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@ -1558,6 +1553,7 @@ bool SIInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
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if (isInlineConstant(UseMI, *Src0, ImmOp))
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return false;
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bool IsF32 = Opc == AMDGPU::V_MAD_F32 || Opc == AMDGPU::V_MAC_F32_e64;
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MachineOperand *Src1 = getNamedOperand(UseMI, AMDGPU::OpName::src1);
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MachineOperand *Src2 = getNamedOperand(UseMI, AMDGPU::OpName::src2);
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@ -1944,6 +1940,14 @@ bool SIInstrInfo::hasModifiersSet(const MachineInstr &MI,
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return Mods && Mods->getImm();
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}
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bool SIInstrInfo::hasAnyModifiersSet(const MachineInstr &MI) const {
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return hasModifiersSet(MI, AMDGPU::OpName::src0_modifiers) ||
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hasModifiersSet(MI, AMDGPU::OpName::src1_modifiers) ||
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hasModifiersSet(MI, AMDGPU::OpName::src2_modifiers) ||
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hasModifiersSet(MI, AMDGPU::OpName::clamp) ||
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hasModifiersSet(MI, AMDGPU::OpName::omod);
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}
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bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,
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const MachineOperand &MO,
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const MCOperandInfo &OpInfo) const {
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@ -607,6 +607,7 @@ public:
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bool hasModifiersSet(const MachineInstr &MI,
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unsigned OpName) const;
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bool hasAnyModifiersSet(const MachineInstr &MI) const;
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bool verifyInstruction(const MachineInstr &MI,
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StringRef &ErrInfo) const override;
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306
test/CodeGen/AMDGPU/fold-immediate-output-mods.mir
Normal file
306
test/CodeGen/AMDGPU/fold-immediate-output-mods.mir
Normal file
@ -0,0 +1,306 @@
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# RUN: llc -march=amdgcn -run-pass peephole-opt -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
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--- |
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define amdgpu_kernel void @no_fold_imm_madak_mac_clamp_f32() #0 {
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ret void
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}
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define amdgpu_kernel void @no_fold_imm_madak_mac_omod_f32() #0 {
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ret void
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}
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define amdgpu_kernel void @no_fold_imm_madak_mad_clamp_f32() #0 {
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ret void
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}
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define amdgpu_kernel void @no_fold_imm_madak_mad_omod_f32() #0 {
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ret void
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}
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attributes #0 = { nounwind }
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...
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---
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# GCN-LABEL: name: no_fold_imm_madak_mac_clamp_f32
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# GCN: %23 = V_MOV_B32_e32 1090519040, implicit %exec
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# GCN-NEXT: %24 = V_MAC_F32_e64 0, killed %19, 0, killed %21, 0, %23, 1, 0, implicit %exec
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name: no_fold_imm_madak_mac_clamp_f32
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tracksRegLiveness: true
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registers:
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- { id: 0, class: sgpr_64 }
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- { id: 1, class: sreg_32_xm0 }
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- { id: 2, class: sgpr_32 }
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- { id: 3, class: vgpr_32 }
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- { id: 4, class: sreg_64_xexec }
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- { id: 5, class: sreg_64_xexec }
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- { id: 6, class: sreg_64_xexec }
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- { id: 7, class: sreg_32 }
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- { id: 8, class: sreg_32 }
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- { id: 9, class: sreg_32_xm0 }
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- { id: 10, class: sreg_64 }
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- { id: 11, class: sreg_32_xm0 }
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- { id: 12, class: sreg_32_xm0 }
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- { id: 13, class: sgpr_64 }
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- { id: 14, class: sgpr_128 }
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- { id: 15, class: sreg_32_xm0 }
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- { id: 16, class: sreg_64 }
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- { id: 17, class: sgpr_128 }
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- { id: 18, class: sgpr_128 }
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- { id: 19, class: vgpr_32 }
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- { id: 20, class: vreg_64 }
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- { id: 21, class: vgpr_32 }
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- { id: 22, class: vreg_64 }
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- { id: 23, class: vgpr_32 }
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- { id: 24, class: vgpr_32 }
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- { id: 25, class: vgpr_32 }
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- { id: 26, class: vreg_64 }
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- { id: 27, class: vgpr_32 }
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- { id: 28, class: vreg_64 }
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- { id: 29, class: vreg_64 }
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liveins:
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- { reg: '%sgpr0_sgpr1', virtual-reg: '%0' }
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- { reg: '%vgpr0', virtual-reg: '%3' }
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body: |
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bb.0 (%ir-block.0):
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liveins: %sgpr0_sgpr1, %vgpr0
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%3 = COPY %vgpr0
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%0 = COPY %sgpr0_sgpr1
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%4 = S_LOAD_DWORDX2_IMM %0, 9, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
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%5 = S_LOAD_DWORDX2_IMM %0, 11, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
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%6 = S_LOAD_DWORDX2_IMM %0, 13, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
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%27 = V_ASHRREV_I32_e32 31, %3, implicit %exec
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%28 = REG_SEQUENCE %3, 1, %27, 2
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%11 = S_MOV_B32 61440
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%12 = S_MOV_B32 0
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%13 = REG_SEQUENCE killed %12, 1, killed %11, 2
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%14 = REG_SEQUENCE killed %5, 17, %13, 18
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%15 = S_MOV_B32 2
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%29 = V_LSHL_B64 killed %28, killed %15, implicit %exec
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%17 = REG_SEQUENCE killed %6, 17, %13, 18
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%18 = REG_SEQUENCE killed %4, 17, %13, 18
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%20 = COPY %29
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%19 = BUFFER_LOAD_DWORD_ADDR64 %20, killed %14, 0, 0, 0, 0, 0, implicit %exec
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%22 = COPY %29
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%21 = BUFFER_LOAD_DWORD_ADDR64 %22, killed %17, 0, 0, 0, 0, 0, implicit %exec
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%23 = V_MOV_B32_e32 1090519040, implicit %exec
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%24 = V_MAC_F32_e64 0, killed %19, 0, killed %21, 0, %23, 1, 0, implicit %exec
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%26 = COPY %29
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BUFFER_STORE_DWORD_ADDR64 killed %24, %26, killed %18, 0, 0, 0, 0, 0, implicit %exec
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S_ENDPGM
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...
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---
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# GCN-LABEL: name: no_fold_imm_madak_mac_omod_f32
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# GCN: %23 = V_MOV_B32_e32 1090519040, implicit %exec
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# GCN: %24 = V_MAC_F32_e64 0, killed %19, 0, killed %21, 0, %23, 0, 2, implicit %exec
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name: no_fold_imm_madak_mac_omod_f32
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tracksRegLiveness: true
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registers:
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- { id: 0, class: sgpr_64 }
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- { id: 1, class: sreg_32_xm0 }
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- { id: 2, class: sgpr_32 }
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- { id: 3, class: vgpr_32 }
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- { id: 4, class: sreg_64_xexec }
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- { id: 5, class: sreg_64_xexec }
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- { id: 6, class: sreg_64_xexec }
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- { id: 7, class: sreg_32 }
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- { id: 8, class: sreg_32 }
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- { id: 9, class: sreg_32_xm0 }
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- { id: 10, class: sreg_64 }
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- { id: 11, class: sreg_32_xm0 }
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- { id: 12, class: sreg_32_xm0 }
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- { id: 13, class: sgpr_64 }
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- { id: 14, class: sgpr_128 }
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- { id: 15, class: sreg_32_xm0 }
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- { id: 16, class: sreg_64 }
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- { id: 17, class: sgpr_128 }
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- { id: 18, class: sgpr_128 }
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- { id: 19, class: vgpr_32 }
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- { id: 20, class: vreg_64 }
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- { id: 21, class: vgpr_32 }
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- { id: 22, class: vreg_64 }
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- { id: 23, class: vgpr_32 }
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- { id: 24, class: vgpr_32 }
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- { id: 25, class: vgpr_32 }
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- { id: 26, class: vreg_64 }
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- { id: 27, class: vgpr_32 }
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- { id: 28, class: vreg_64 }
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- { id: 29, class: vreg_64 }
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liveins:
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- { reg: '%sgpr0_sgpr1', virtual-reg: '%0' }
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- { reg: '%vgpr0', virtual-reg: '%3' }
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body: |
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bb.0 (%ir-block.0):
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liveins: %sgpr0_sgpr1, %vgpr0
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%3 = COPY %vgpr0
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%0 = COPY %sgpr0_sgpr1
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%4 = S_LOAD_DWORDX2_IMM %0, 9, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
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%5 = S_LOAD_DWORDX2_IMM %0, 11, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
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%6 = S_LOAD_DWORDX2_IMM %0, 13, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
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%27 = V_ASHRREV_I32_e32 31, %3, implicit %exec
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%28 = REG_SEQUENCE %3, 1, %27, 2
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%11 = S_MOV_B32 61440
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%12 = S_MOV_B32 0
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%13 = REG_SEQUENCE killed %12, 1, killed %11, 2
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%14 = REG_SEQUENCE killed %5, 17, %13, 18
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%15 = S_MOV_B32 2
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%29 = V_LSHL_B64 killed %28, killed %15, implicit %exec
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%17 = REG_SEQUENCE killed %6, 17, %13, 18
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%18 = REG_SEQUENCE killed %4, 17, %13, 18
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%20 = COPY %29
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%19 = BUFFER_LOAD_DWORD_ADDR64 %20, killed %14, 0, 0, 0, 0, 0, implicit %exec
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%22 = COPY %29
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%21 = BUFFER_LOAD_DWORD_ADDR64 %22, killed %17, 0, 0, 0, 0, 0, implicit %exec
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%23 = V_MOV_B32_e32 1090519040, implicit %exec
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%24 = V_MAC_F32_e64 0, killed %19, 0, killed %21, 0, %23, 0, 2, implicit %exec
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%26 = COPY %29
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BUFFER_STORE_DWORD_ADDR64 killed %24, %26, killed %18, 0, 0, 0, 0, 0, implicit %exec
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S_ENDPGM
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...
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---
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# GCN: name: no_fold_imm_madak_mad_clamp_f32
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# GCN: %23 = V_MOV_B32_e32 1090519040, implicit %exec
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# GCN: %24 = V_MAD_F32 0, killed %19, 0, killed %21, 0, %23, 1, 0, implicit %exec
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name: no_fold_imm_madak_mad_clamp_f32
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tracksRegLiveness: true
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registers:
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- { id: 0, class: sgpr_64 }
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- { id: 1, class: sreg_32_xm0 }
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- { id: 2, class: sgpr_32 }
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- { id: 3, class: vgpr_32 }
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- { id: 4, class: sreg_64_xexec }
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- { id: 5, class: sreg_64_xexec }
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- { id: 6, class: sreg_64_xexec }
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- { id: 7, class: sreg_32 }
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- { id: 8, class: sreg_32 }
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- { id: 9, class: sreg_32_xm0 }
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- { id: 10, class: sreg_64 }
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- { id: 11, class: sreg_32_xm0 }
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- { id: 12, class: sreg_32_xm0 }
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- { id: 13, class: sgpr_64 }
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- { id: 14, class: sgpr_128 }
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- { id: 15, class: sreg_32_xm0 }
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- { id: 16, class: sreg_64 }
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- { id: 17, class: sgpr_128 }
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- { id: 18, class: sgpr_128 }
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- { id: 19, class: vgpr_32 }
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- { id: 20, class: vreg_64 }
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- { id: 21, class: vgpr_32 }
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- { id: 22, class: vreg_64 }
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- { id: 23, class: vgpr_32 }
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- { id: 24, class: vgpr_32 }
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- { id: 25, class: vgpr_32 }
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- { id: 26, class: vreg_64 }
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- { id: 27, class: vgpr_32 }
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- { id: 28, class: vreg_64 }
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- { id: 29, class: vreg_64 }
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liveins:
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- { reg: '%sgpr0_sgpr1', virtual-reg: '%0' }
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- { reg: '%vgpr0', virtual-reg: '%3' }
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body: |
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bb.0 (%ir-block.0):
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liveins: %sgpr0_sgpr1, %vgpr0
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%3 = COPY %vgpr0
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%0 = COPY %sgpr0_sgpr1
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%4 = S_LOAD_DWORDX2_IMM %0, 9, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
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%5 = S_LOAD_DWORDX2_IMM %0, 11, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
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%6 = S_LOAD_DWORDX2_IMM %0, 13, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
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%27 = V_ASHRREV_I32_e32 31, %3, implicit %exec
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%28 = REG_SEQUENCE %3, 1, %27, 2
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%11 = S_MOV_B32 61440
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%12 = S_MOV_B32 0
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%13 = REG_SEQUENCE killed %12, 1, killed %11, 2
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%14 = REG_SEQUENCE killed %5, 17, %13, 18
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%15 = S_MOV_B32 2
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%29 = V_LSHL_B64 killed %28, killed %15, implicit %exec
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%17 = REG_SEQUENCE killed %6, 17, %13, 18
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%18 = REG_SEQUENCE killed %4, 17, %13, 18
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%20 = COPY %29
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%19 = BUFFER_LOAD_DWORD_ADDR64 %20, killed %14, 0, 0, 0, 0, 0, implicit %exec
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%22 = COPY %29
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%21 = BUFFER_LOAD_DWORD_ADDR64 %22, killed %17, 0, 0, 0, 0, 0, implicit %exec
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%23 = V_MOV_B32_e32 1090519040, implicit %exec
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%24 = V_MAD_F32 0, killed %19, 0, killed %21, 0, %23, 1, 0, implicit %exec
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%26 = COPY %29
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BUFFER_STORE_DWORD_ADDR64 killed %24, %26, killed %18, 0, 0, 0, 0, 0, implicit %exec
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S_ENDPGM
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...
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---
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# GCN: name: no_fold_imm_madak_mad_omod_f32
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# GCN: %23 = V_MOV_B32_e32 1090519040, implicit %exec
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# GCN: %24 = V_MAD_F32 0, killed %19, 0, killed %21, 0, %23, 0, 1, implicit %exec
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name: no_fold_imm_madak_mad_omod_f32
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tracksRegLiveness: true
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registers:
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- { id: 0, class: sgpr_64 }
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- { id: 1, class: sreg_32_xm0 }
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- { id: 2, class: sgpr_32 }
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- { id: 3, class: vgpr_32 }
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- { id: 4, class: sreg_64_xexec }
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- { id: 5, class: sreg_64_xexec }
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- { id: 6, class: sreg_64_xexec }
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- { id: 7, class: sreg_32 }
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- { id: 8, class: sreg_32 }
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- { id: 9, class: sreg_32_xm0 }
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- { id: 10, class: sreg_64 }
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- { id: 11, class: sreg_32_xm0 }
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- { id: 12, class: sreg_32_xm0 }
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- { id: 13, class: sgpr_64 }
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- { id: 14, class: sgpr_128 }
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- { id: 15, class: sreg_32_xm0 }
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- { id: 16, class: sreg_64 }
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- { id: 17, class: sgpr_128 }
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- { id: 18, class: sgpr_128 }
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- { id: 19, class: vgpr_32 }
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- { id: 20, class: vreg_64 }
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- { id: 21, class: vgpr_32 }
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- { id: 22, class: vreg_64 }
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- { id: 23, class: vgpr_32 }
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- { id: 24, class: vgpr_32 }
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- { id: 25, class: vgpr_32 }
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- { id: 26, class: vreg_64 }
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- { id: 27, class: vgpr_32 }
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- { id: 28, class: vreg_64 }
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- { id: 29, class: vreg_64 }
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liveins:
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- { reg: '%sgpr0_sgpr1', virtual-reg: '%0' }
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- { reg: '%vgpr0', virtual-reg: '%3' }
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body: |
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bb.0 (%ir-block.0):
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liveins: %sgpr0_sgpr1, %vgpr0
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%3 = COPY %vgpr0
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%0 = COPY %sgpr0_sgpr1
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%4 = S_LOAD_DWORDX2_IMM %0, 9, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
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%5 = S_LOAD_DWORDX2_IMM %0, 11, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
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%6 = S_LOAD_DWORDX2_IMM %0, 13, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
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%27 = V_ASHRREV_I32_e32 31, %3, implicit %exec
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%28 = REG_SEQUENCE %3, 1, %27, 2
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%11 = S_MOV_B32 61440
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%12 = S_MOV_B32 0
|
||||
%13 = REG_SEQUENCE killed %12, 1, killed %11, 2
|
||||
%14 = REG_SEQUENCE killed %5, 17, %13, 18
|
||||
%15 = S_MOV_B32 2
|
||||
%29 = V_LSHL_B64 killed %28, killed %15, implicit %exec
|
||||
%17 = REG_SEQUENCE killed %6, 17, %13, 18
|
||||
%18 = REG_SEQUENCE killed %4, 17, %13, 18
|
||||
%20 = COPY %29
|
||||
%19 = BUFFER_LOAD_DWORD_ADDR64 %20, killed %14, 0, 0, 0, 0, 0, implicit %exec
|
||||
%22 = COPY %29
|
||||
%21 = BUFFER_LOAD_DWORD_ADDR64 %22, killed %17, 0, 0, 0, 0, 0, implicit %exec
|
||||
%23 = V_MOV_B32_e32 1090519040, implicit %exec
|
||||
%24 = V_MAD_F32 0, killed %19, 0, killed %21, 0, %23, 0, 1, implicit %exec
|
||||
%26 = COPY %29
|
||||
BUFFER_STORE_DWORD_ADDR64 killed %24, %26, killed %18, 0, 0, 0, 0, 0, implicit %exec
|
||||
S_ENDPGM
|
||||
|
||||
...
|
||||
Loading…
x
Reference in New Issue
Block a user