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[PowerPC] Implement __int128 vector divide operations

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This patch implements __int128 vector divide operations for ISA3.1.

Differential Revision: https://reviews.llvm.org/D85453
This commit is contained in:
Albion Fung 2020-09-15 15:18:54 -04:00
parent 50c071e797
commit ef3cfcdc3b
3 changed files with 24 additions and 2 deletions
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2
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -888,6 +888,8 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
setOperationAction(ISD::SREM, MVT::v2i64, Legal);
setOperationAction(ISD::UREM, MVT::v4i32, Legal);
setOperationAction(ISD::SREM, MVT::v4i32, Legal);
setOperationAction(ISD::UDIV, MVT::v1i128, Legal);
setOperationAction(ISD::SDIV, MVT::v1i128, Legal);
}
setOperationAction(ISD::MUL, MVT::v8i16, Legal);

6
lib/Target/PowerPC/PPCInstrPrefix.td
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@ -1285,9 +1285,11 @@ let Predicates = [IsISA3_1] in {
[(set v1i128:$vD, (int_ppc_altivec_vmsumcud
v2i64:$vA, v2i64:$vB, v1i128:$vC))]>;
def VDIVSQ : VXForm_1<267, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vdivsq $vD, $vA, $vB", IIC_VecGeneral, []>;
"vdivsq $vD, $vA, $vB", IIC_VecGeneral,
[(set v1i128:$vD, (sdiv v1i128:$vA, v1i128:$vB))]>;
def VDIVUQ : VXForm_1<11, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vdivuq $vD, $vA, $vB", IIC_VecGeneral, []>;
"vdivuq $vD, $vA, $vB", IIC_VecGeneral,
[(set v1i128:$vD, (udiv v1i128:$vA, v1i128:$vB))]>;
def VDIVESQ : VXForm_1<779, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vdivesq $vD, $vA, $vB", IIC_VecGeneral, []>;
def VDIVEUQ : VXForm_1<523, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),

18
test/CodeGen/PowerPC/p10-vector-divide.ll
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@ -76,6 +76,24 @@ entry:
ret <4 x i32> %div
}
define <1 x i128> @test_vdivsq(<1 x i128> %x, <1 x i128> %y) nounwind readnone {
; CHECK-LABEL: test_vdivsq:
; CHECK: # %bb.0:
; CHECK-NEXT: vdivsq v2, v2, v3
; CHECK-NEXT: blr
%tmp = sdiv <1 x i128> %x, %y
ret <1 x i128> %tmp
}
define <1 x i128> @test_vdivuq(<1 x i128> %x, <1 x i128> %y) nounwind readnone {
; CHECK-LABEL: test_vdivuq:
; CHECK: # %bb.0:
; CHECK-NEXT: vdivuq v2, v2, v3
; CHECK-NEXT: blr
%tmp = udiv <1 x i128> %x, %y
ret <1 x i128> %tmp
}
define <2 x i64> @test_vdivesd(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: test_vdivesd:
; CHECK: # %bb.0: # %entry