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[RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w
Floating point positive zero can be selected using fmv.w.x / fmv.d.x / fcvt.d.w and the zero source register. Differential Revision: https://reviews.llvm.org/D75729
This commit is contained in:
Roger Ferrer Ibanez
parent
1f76f9f3fb
commit
ef495f25d0
@ -336,6 +336,17 @@ bool RISCVTargetLowering::isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const {
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return Subtarget.is64Bit() && SrcVT == MVT::i32 && DstVT == MVT::i64;
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}
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bool RISCVTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
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bool ForCodeSize) const {
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if (VT == MVT::f32 && !Subtarget.hasStdExtF())
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return false;
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if (VT == MVT::f64 && !Subtarget.hasStdExtD())
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return false;
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if (Imm.isNegZero())
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return false;
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return Imm.isZero();
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}
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bool RISCVTargetLowering::hasBitPreservingFPLogic(EVT VT) const {
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return (VT == MVT::f32 && Subtarget.hasStdExtF()) ||
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(VT == MVT::f64 && Subtarget.hasStdExtD());
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@ -74,6 +74,8 @@ public:
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bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
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bool isZExtFree(SDValue Val, EVT VT2) const override;
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bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
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bool isFPImmLegal(const APFloat &Imm, EVT VT,
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bool ForCodeSize) const override;
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bool hasBitPreservingFPLogic(EVT VT) const override;
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@ -339,6 +339,10 @@ def SplitF64Pseudo
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} // Predicates = [HasStdExtD]
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let Predicates = [HasStdExtD, IsRV32] in {
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/// Float constants
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def : Pat<(f64 (fpimm0)), (FCVT_D_W X0)>;
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// double->[u]int. Round-to-zero must be used.
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def : Pat<(fp_to_sint FPR64:$rs1), (FCVT_W_D FPR64:$rs1, 0b001)>;
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def : Pat<(fp_to_uint FPR64:$rs1), (FCVT_WU_D FPR64:$rs1, 0b001)>;
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@ -349,6 +353,10 @@ def : Pat<(uint_to_fp GPR:$rs1), (FCVT_D_WU GPR:$rs1)>;
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} // Predicates = [HasStdExtD, IsRV32]
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let Predicates = [HasStdExtD, IsRV64] in {
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/// Float constants
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def : Pat<(f64 (fpimm0)), (FMV_D_X X0)>;
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def : Pat<(bitconvert GPR:$rs1), (FMV_D_X GPR:$rs1)>;
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def : Pat<(bitconvert FPR64:$rs1), (FMV_X_D FPR64:$rs1)>;
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@ -286,6 +286,9 @@ def PseudoFSW : PseudoStore<"fsw", FPR32>;
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// Pseudo-instructions and codegen patterns
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//===----------------------------------------------------------------------===//
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/// Floating point constants
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def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>;
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/// Generic pattern classes
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class PatFpr32Fpr32<SDPatternOperator OpNode, RVInstR Inst>
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: Pat<(OpNode FPR32:$rs1, FPR32:$rs2), (Inst $rs1, $rs2)>;
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@ -295,6 +298,9 @@ class PatFpr32Fpr32DynFrm<SDPatternOperator OpNode, RVInstRFrm Inst>
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let Predicates = [HasStdExtF] in {
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/// Float constants
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def : Pat<(f32 (fpimm0)), (FMV_W_X X0)>;
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/// Float conversion operations
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// Moves (no conversion)
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@ -460,9 +460,7 @@ define double @fmsub_d(double %a, double %b, double %c) nounwind {
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; RV32IFD-NEXT: sw a4, 8(sp)
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; RV32IFD-NEXT: sw a5, 12(sp)
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; RV32IFD-NEXT: fld ft2, 8(sp)
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; RV32IFD-NEXT: lui a0, %hi(.LCPI15_0)
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; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI15_0)
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; RV32IFD-NEXT: fld ft3, 0(a0)
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; RV32IFD-NEXT: fcvt.d.w ft3, zero
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; RV32IFD-NEXT: fadd.d ft2, ft2, ft3
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; RV32IFD-NEXT: fmsub.d ft0, ft1, ft0, ft2
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; RV32IFD-NEXT: fsd ft0, 8(sp)
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@ -473,14 +471,12 @@ define double @fmsub_d(double %a, double %b, double %c) nounwind {
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;
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; RV64IFD-LABEL: fmsub_d:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: lui a3, %hi(.LCPI15_0)
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; RV64IFD-NEXT: addi a3, a3, %lo(.LCPI15_0)
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; RV64IFD-NEXT: fld ft0, 0(a3)
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; RV64IFD-NEXT: fmv.d.x ft1, a1
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; RV64IFD-NEXT: fmv.d.x ft2, a0
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; RV64IFD-NEXT: fmv.d.x ft3, a2
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; RV64IFD-NEXT: fadd.d ft0, ft3, ft0
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; RV64IFD-NEXT: fmsub.d ft0, ft2, ft1, ft0
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; RV64IFD-NEXT: fmv.d.x ft0, a1
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; RV64IFD-NEXT: fmv.d.x ft1, a0
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; RV64IFD-NEXT: fmv.d.x ft2, a2
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; RV64IFD-NEXT: fmv.d.x ft3, zero
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; RV64IFD-NEXT: fadd.d ft2, ft2, ft3
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; RV64IFD-NEXT: fmsub.d ft0, ft1, ft0, ft2
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; RV64IFD-NEXT: fmv.x.d a0, ft0
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; RV64IFD-NEXT: ret
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%c_ = fadd double 0.0, %c ; avoid negation using xor
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@ -502,9 +498,7 @@ define double @fnmadd_d(double %a, double %b, double %c) nounwind {
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft2, 8(sp)
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; RV32IFD-NEXT: lui a0, %hi(.LCPI16_0)
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; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI16_0)
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; RV32IFD-NEXT: fld ft3, 0(a0)
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; RV32IFD-NEXT: fcvt.d.w ft3, zero
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; RV32IFD-NEXT: fadd.d ft2, ft2, ft3
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; RV32IFD-NEXT: fadd.d ft1, ft1, ft3
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; RV32IFD-NEXT: fnmadd.d ft0, ft2, ft0, ft1
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@ -516,15 +510,13 @@ define double @fnmadd_d(double %a, double %b, double %c) nounwind {
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;
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; RV64IFD-LABEL: fnmadd_d:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: lui a3, %hi(.LCPI16_0)
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; RV64IFD-NEXT: addi a3, a3, %lo(.LCPI16_0)
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; RV64IFD-NEXT: fld ft0, 0(a3)
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; RV64IFD-NEXT: fmv.d.x ft1, a1
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; RV64IFD-NEXT: fmv.d.x ft2, a2
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; RV64IFD-NEXT: fmv.d.x ft3, a0
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; RV64IFD-NEXT: fadd.d ft3, ft3, ft0
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; RV64IFD-NEXT: fadd.d ft0, ft2, ft0
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; RV64IFD-NEXT: fnmadd.d ft0, ft3, ft1, ft0
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; RV64IFD-NEXT: fmv.d.x ft0, a1
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; RV64IFD-NEXT: fmv.d.x ft1, a2
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; RV64IFD-NEXT: fmv.d.x ft2, a0
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; RV64IFD-NEXT: fmv.d.x ft3, zero
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; RV64IFD-NEXT: fadd.d ft2, ft2, ft3
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; RV64IFD-NEXT: fadd.d ft1, ft1, ft3
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; RV64IFD-NEXT: fnmadd.d ft0, ft2, ft0, ft1
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; RV64IFD-NEXT: fmv.x.d a0, ft0
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; RV64IFD-NEXT: ret
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%a_ = fadd double 0.0, %a
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@ -548,9 +540,7 @@ define double @fnmsub_d(double %a, double %b, double %c) nounwind {
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft2, 8(sp)
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; RV32IFD-NEXT: lui a0, %hi(.LCPI17_0)
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; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI17_0)
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; RV32IFD-NEXT: fld ft3, 0(a0)
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; RV32IFD-NEXT: fcvt.d.w ft3, zero
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; RV32IFD-NEXT: fadd.d ft2, ft2, ft3
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; RV32IFD-NEXT: fnmsub.d ft0, ft2, ft1, ft0
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; RV32IFD-NEXT: fsd ft0, 8(sp)
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@ -561,14 +551,12 @@ define double @fnmsub_d(double %a, double %b, double %c) nounwind {
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;
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; RV64IFD-LABEL: fnmsub_d:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: lui a3, %hi(.LCPI17_0)
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; RV64IFD-NEXT: addi a3, a3, %lo(.LCPI17_0)
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; RV64IFD-NEXT: fld ft0, 0(a3)
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; RV64IFD-NEXT: fmv.d.x ft1, a2
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; RV64IFD-NEXT: fmv.d.x ft2, a1
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; RV64IFD-NEXT: fmv.d.x ft3, a0
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; RV64IFD-NEXT: fadd.d ft0, ft3, ft0
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; RV64IFD-NEXT: fnmsub.d ft0, ft0, ft2, ft1
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; RV64IFD-NEXT: fmv.d.x ft0, a2
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; RV64IFD-NEXT: fmv.d.x ft1, a1
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; RV64IFD-NEXT: fmv.d.x ft2, a0
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; RV64IFD-NEXT: fmv.d.x ft3, zero
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; RV64IFD-NEXT: fadd.d ft2, ft2, ft3
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; RV64IFD-NEXT: fnmsub.d ft0, ft2, ft1, ft0
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; RV64IFD-NEXT: fmv.x.d a0, ft0
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; RV64IFD-NEXT: ret
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%a_ = fadd double 0.0, %a
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@ -339,27 +339,23 @@ define float @fmadd_s(float %a, float %b, float %c) nounwind {
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define float @fmsub_s(float %a, float %b, float %c) nounwind {
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; RV32IF-LABEL: fmsub_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: lui a3, %hi(.LCPI15_0)
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; RV32IF-NEXT: addi a3, a3, %lo(.LCPI15_0)
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; RV32IF-NEXT: flw ft0, 0(a3)
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; RV32IF-NEXT: fmv.w.x ft1, a1
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; RV32IF-NEXT: fmv.w.x ft2, a0
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; RV32IF-NEXT: fmv.w.x ft3, a2
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; RV32IF-NEXT: fadd.s ft0, ft3, ft0
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; RV32IF-NEXT: fmsub.s ft0, ft2, ft1, ft0
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: fmv.w.x ft2, a2
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; RV32IF-NEXT: fmv.w.x ft3, zero
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; RV32IF-NEXT: fadd.s ft2, ft2, ft3
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; RV32IF-NEXT: fmsub.s ft0, ft1, ft0, ft2
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fmsub_s:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: lui a3, %hi(.LCPI15_0)
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; RV64IF-NEXT: addi a3, a3, %lo(.LCPI15_0)
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; RV64IF-NEXT: flw ft0, 0(a3)
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; RV64IF-NEXT: fmv.w.x ft1, a1
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; RV64IF-NEXT: fmv.w.x ft2, a0
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; RV64IF-NEXT: fmv.w.x ft3, a2
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; RV64IF-NEXT: fadd.s ft0, ft3, ft0
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; RV64IF-NEXT: fmsub.s ft0, ft2, ft1, ft0
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; RV64IF-NEXT: fmv.w.x ft0, a1
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; RV64IF-NEXT: fmv.w.x ft1, a0
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; RV64IF-NEXT: fmv.w.x ft2, a2
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; RV64IF-NEXT: fmv.w.x ft3, zero
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; RV64IF-NEXT: fadd.s ft2, ft2, ft3
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; RV64IF-NEXT: fmsub.s ft0, ft1, ft0, ft2
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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%c_ = fadd float 0.0, %c ; avoid negation using xor
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@ -371,29 +367,25 @@ define float @fmsub_s(float %a, float %b, float %c) nounwind {
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define float @fnmadd_s(float %a, float %b, float %c) nounwind {
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; RV32IF-LABEL: fnmadd_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: lui a3, %hi(.LCPI16_0)
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; RV32IF-NEXT: addi a3, a3, %lo(.LCPI16_0)
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; RV32IF-NEXT: flw ft0, 0(a3)
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; RV32IF-NEXT: fmv.w.x ft1, a1
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; RV32IF-NEXT: fmv.w.x ft2, a2
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; RV32IF-NEXT: fmv.w.x ft3, a0
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; RV32IF-NEXT: fadd.s ft3, ft3, ft0
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; RV32IF-NEXT: fadd.s ft0, ft2, ft0
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; RV32IF-NEXT: fnmadd.s ft0, ft3, ft1, ft0
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a2
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; RV32IF-NEXT: fmv.w.x ft2, a0
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; RV32IF-NEXT: fmv.w.x ft3, zero
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; RV32IF-NEXT: fadd.s ft2, ft2, ft3
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; RV32IF-NEXT: fadd.s ft1, ft1, ft3
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; RV32IF-NEXT: fnmadd.s ft0, ft2, ft0, ft1
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fnmadd_s:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: lui a3, %hi(.LCPI16_0)
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; RV64IF-NEXT: addi a3, a3, %lo(.LCPI16_0)
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; RV64IF-NEXT: flw ft0, 0(a3)
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; RV64IF-NEXT: fmv.w.x ft1, a1
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; RV64IF-NEXT: fmv.w.x ft2, a2
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; RV64IF-NEXT: fmv.w.x ft3, a0
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; RV64IF-NEXT: fadd.s ft3, ft3, ft0
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; RV64IF-NEXT: fadd.s ft0, ft2, ft0
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; RV64IF-NEXT: fnmadd.s ft0, ft3, ft1, ft0
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; RV64IF-NEXT: fmv.w.x ft0, a1
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; RV64IF-NEXT: fmv.w.x ft1, a2
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; RV64IF-NEXT: fmv.w.x ft2, a0
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; RV64IF-NEXT: fmv.w.x ft3, zero
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; RV64IF-NEXT: fadd.s ft2, ft2, ft3
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; RV64IF-NEXT: fadd.s ft1, ft1, ft3
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; RV64IF-NEXT: fnmadd.s ft0, ft2, ft0, ft1
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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%a_ = fadd float 0.0, %a
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@ -407,27 +399,23 @@ define float @fnmadd_s(float %a, float %b, float %c) nounwind {
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define float @fnmsub_s(float %a, float %b, float %c) nounwind {
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; RV32IF-LABEL: fnmsub_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: lui a3, %hi(.LCPI17_0)
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; RV32IF-NEXT: addi a3, a3, %lo(.LCPI17_0)
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; RV32IF-NEXT: flw ft0, 0(a3)
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; RV32IF-NEXT: fmv.w.x ft1, a2
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; RV32IF-NEXT: fmv.w.x ft2, a1
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; RV32IF-NEXT: fmv.w.x ft3, a0
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; RV32IF-NEXT: fadd.s ft0, ft3, ft0
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; RV32IF-NEXT: fnmsub.s ft0, ft0, ft2, ft1
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; RV32IF-NEXT: fmv.w.x ft0, a2
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; RV32IF-NEXT: fmv.w.x ft1, a1
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; RV32IF-NEXT: fmv.w.x ft2, a0
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; RV32IF-NEXT: fmv.w.x ft3, zero
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; RV32IF-NEXT: fadd.s ft2, ft2, ft3
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; RV32IF-NEXT: fnmsub.s ft0, ft2, ft1, ft0
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fnmsub_s:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: lui a3, %hi(.LCPI17_0)
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; RV64IF-NEXT: addi a3, a3, %lo(.LCPI17_0)
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; RV64IF-NEXT: flw ft0, 0(a3)
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; RV64IF-NEXT: fmv.w.x ft1, a2
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; RV64IF-NEXT: fmv.w.x ft2, a1
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; RV64IF-NEXT: fmv.w.x ft3, a0
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; RV64IF-NEXT: fadd.s ft0, ft3, ft0
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; RV64IF-NEXT: fnmsub.s ft0, ft0, ft2, ft1
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; RV64IF-NEXT: fmv.w.x ft0, a2
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; RV64IF-NEXT: fmv.w.x ft1, a1
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; RV64IF-NEXT: fmv.w.x ft2, a0
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; RV64IF-NEXT: fmv.w.x ft3, zero
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; RV64IF-NEXT: fadd.s ft2, ft2, ft3
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; RV64IF-NEXT: fnmsub.s ft0, ft2, ft1, ft0
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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%a_ = fadd float 0.0, %a
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@ -720,10 +720,8 @@ define i32 @br_fcmp_store_load_stack_slot(float %a, float %b) nounwind {
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; RV32IF-NEXT: sw ra, 12(sp)
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; RV32IF-NEXT: mv a0, zero
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; RV32IF-NEXT: call dummy
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; RV32IF-NEXT: lui a1, %hi(.LCPI17_0)
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; RV32IF-NEXT: addi a1, a1, %lo(.LCPI17_0)
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; RV32IF-NEXT: flw ft1, 0(a1)
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; RV32IF-NEXT: fmv.w.x ft0, a0
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; RV32IF-NEXT: fmv.w.x ft1, zero
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; RV32IF-NEXT: fsw ft1, 8(sp)
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; RV32IF-NEXT: feq.s a0, ft0, ft1
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; RV32IF-NEXT: beqz a0, .LBB17_3
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@ -747,9 +745,7 @@ define i32 @br_fcmp_store_load_stack_slot(float %a, float %b) nounwind {
|
||||
; RV64IF-NEXT: addi sp, sp, -32
|
||||
; RV64IF-NEXT: sd ra, 24(sp)
|
||||
; RV64IF-NEXT: sd s0, 16(sp)
|
||||
; RV64IF-NEXT: lui a0, %hi(.LCPI17_0)
|
||||
; RV64IF-NEXT: addi a0, a0, %lo(.LCPI17_0)
|
||||
; RV64IF-NEXT: flw ft0, 0(a0)
|
||||
; RV64IF-NEXT: fmv.w.x ft0, zero
|
||||
; RV64IF-NEXT: fsw ft0, 12(sp)
|
||||
; RV64IF-NEXT: fmv.x.w s0, ft0
|
||||
; RV64IF-NEXT: mv a0, s0
|
||||
|
||||
@ -11,30 +11,22 @@
|
||||
define float @f32_positive_zero(float *%pf) nounwind {
|
||||
; RV32F-LABEL: f32_positive_zero:
|
||||
; RV32F: # %bb.0:
|
||||
; RV32F-NEXT: lui a0, %hi(.LCPI0_0)
|
||||
; RV32F-NEXT: addi a0, a0, %lo(.LCPI0_0)
|
||||
; RV32F-NEXT: flw fa0, 0(a0)
|
||||
; RV32F-NEXT: fmv.w.x fa0, zero
|
||||
; RV32F-NEXT: ret
|
||||
;
|
||||
; RV32D-LABEL: f32_positive_zero:
|
||||
; RV32D: # %bb.0:
|
||||
; RV32D-NEXT: lui a0, %hi(.LCPI0_0)
|
||||
; RV32D-NEXT: addi a0, a0, %lo(.LCPI0_0)
|
||||
; RV32D-NEXT: flw fa0, 0(a0)
|
||||
; RV32D-NEXT: fmv.w.x fa0, zero
|
||||
; RV32D-NEXT: ret
|
||||
;
|
||||
; RV64F-LABEL: f32_positive_zero:
|
||||
; RV64F: # %bb.0:
|
||||
; RV64F-NEXT: lui a0, %hi(.LCPI0_0)
|
||||
; RV64F-NEXT: addi a0, a0, %lo(.LCPI0_0)
|
||||
; RV64F-NEXT: flw fa0, 0(a0)
|
||||
; RV64F-NEXT: fmv.w.x fa0, zero
|
||||
; RV64F-NEXT: ret
|
||||
;
|
||||
; RV64D-LABEL: f32_positive_zero:
|
||||
; RV64D: # %bb.0:
|
||||
; RV64D-NEXT: lui a0, %hi(.LCPI0_0)
|
||||
; RV64D-NEXT: addi a0, a0, %lo(.LCPI0_0)
|
||||
; RV64D-NEXT: flw fa0, 0(a0)
|
||||
; RV64D-NEXT: fmv.w.x fa0, zero
|
||||
; RV64D-NEXT: ret
|
||||
ret float 0.0
|
||||
}
|
||||
@ -79,9 +71,7 @@ define double @f64_positive_zero(double *%pd) nounwind {
|
||||
;
|
||||
; RV32D-LABEL: f64_positive_zero:
|
||||
; RV32D: # %bb.0:
|
||||
; RV32D-NEXT: lui a0, %hi(.LCPI2_0)
|
||||
; RV32D-NEXT: addi a0, a0, %lo(.LCPI2_0)
|
||||
; RV32D-NEXT: fld fa0, 0(a0)
|
||||
; RV32D-NEXT: fcvt.d.w fa0, zero
|
||||
; RV32D-NEXT: ret
|
||||
;
|
||||
; RV64F-LABEL: f64_positive_zero:
|
||||
@ -91,9 +81,7 @@ define double @f64_positive_zero(double *%pd) nounwind {
|
||||
;
|
||||
; RV64D-LABEL: f64_positive_zero:
|
||||
; RV64D: # %bb.0:
|
||||
; RV64D-NEXT: lui a0, %hi(.LCPI2_0)
|
||||
; RV64D-NEXT: addi a0, a0, %lo(.LCPI2_0)
|
||||
; RV64D-NEXT: fld fa0, 0(a0)
|
||||
; RV64D-NEXT: fmv.d.x fa0, zero
|
||||
; RV64D-NEXT: ret
|
||||
ret double 0.0
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user