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[RISCV] Use fcvt.h/d/f.w if the input is an assertsexti32 not just when the input is sext_inreg.

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This commit is contained in:
Craig Topper 2020-12-04 18:36:14 -08:00
parent 0a2da89f49
commit efd454d7c6
6 changed files with 6 additions and 6 deletions
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2
lib/Target/RISCV/RISCVInstrInfoD.td
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@ -373,7 +373,7 @@ def : Pat<(sext_inreg (assertzexti32 (fp_to_uint FPR64:$rs1)), i32),
(FCVT_WU_D $rs1, 0b001)>;
// [u]int32->fp
def : Pat<(sint_to_fp (sext_inreg GPR:$rs1, i32)), (FCVT_D_W $rs1)>;
def : Pat<(sint_to_fp (sexti32 GPR:$rs1)), (FCVT_D_W $rs1)>;
def : Pat<(uint_to_fp (zexti32 GPR:$rs1)), (FCVT_D_WU $rs1)>;
def : Pat<(fp_to_sint FPR64:$rs1), (FCVT_L_D FPR64:$rs1, 0b001)>;

2
lib/Target/RISCV/RISCVInstrInfoF.td
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@ -417,7 +417,7 @@ def : Pat<(fp_to_sint FPR32:$rs1), (FCVT_L_S $rs1, 0b001)>;
def : Pat<(fp_to_uint FPR32:$rs1), (FCVT_LU_S $rs1, 0b001)>;
// [u]int->fp. Match GCC and default to using dynamic rounding mode.
def : Pat<(sint_to_fp (sext_inreg GPR:$rs1, i32)), (FCVT_S_W $rs1, 0b111)>;
def : Pat<(sint_to_fp (sexti32 GPR:$rs1)), (FCVT_S_W $rs1, 0b111)>;
def : Pat<(uint_to_fp (zexti32 GPR:$rs1)), (FCVT_S_WU $rs1, 0b111)>;
def : Pat<(sint_to_fp GPR:$rs1), (FCVT_S_L $rs1, 0b111)>;
def : Pat<(uint_to_fp GPR:$rs1), (FCVT_S_LU $rs1, 0b111)>;

2
lib/Target/RISCV/RISCVInstrInfoZfh.td
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@ -374,7 +374,7 @@ def : Pat<(fp_to_sint FPR16:$rs1), (FCVT_L_H $rs1, 0b001)>;
def : Pat<(fp_to_uint FPR16:$rs1), (FCVT_LU_H $rs1, 0b001)>;
// [u]int->fp. Match GCC and default to using dynamic rounding mode.
def : Pat<(sint_to_fp (sext_inreg GPR:$rs1, i32)), (FCVT_H_W $rs1, 0b111)>;
def : Pat<(sint_to_fp (sexti32 GPR:$rs1)), (FCVT_H_W $rs1, 0b111)>;
def : Pat<(uint_to_fp (zexti32 GPR:$rs1)), (FCVT_H_WU $rs1, 0b111)>;
def : Pat<(sint_to_fp GPR:$rs1), (FCVT_H_L $rs1, 0b111)>;
def : Pat<(uint_to_fp GPR:$rs1), (FCVT_H_LU $rs1, 0b111)>;

2
test/CodeGen/RISCV/rv64d-double-convert.ll
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@ -112,7 +112,7 @@ define double @sitofp_aext_i32_to_f64(i32 %a) nounwind {
define double @sitofp_sext_i32_to_f64(i32 signext %a) nounwind {
; RV64ID-LABEL: sitofp_sext_i32_to_f64:
; RV64ID: # %bb.0:
; RV64ID-NEXT: fcvt.d.l ft0, a0
; RV64ID-NEXT: fcvt.d.w ft0, a0
; RV64ID-NEXT: fmv.x.d a0, ft0
; RV64ID-NEXT: ret
%1 = sitofp i32 %a to double

2
test/CodeGen/RISCV/rv64f-float-convert.ll
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@ -169,7 +169,7 @@ define float @sitofp_aext_i32_to_f32(i32 %a) nounwind {
define float @sitofp_sext_i32_to_f32(i32 signext %a) nounwind {
; RV64IF-LABEL: sitofp_sext_i32_to_f32:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.s.l ft0, a0
; RV64IF-NEXT: fcvt.s.w ft0, a0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
%1 = sitofp i32 %a to float

2
test/CodeGen/RISCV/rv64f-half-convert.ll
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@ -155,7 +155,7 @@ define half @sitofp_aext_i32_to_f16(i32 %a) nounwind {
define half @sitofp_sext_i32_to_f16(i32 signext %a) nounwind {
; RV64IZFH-LABEL: sitofp_sext_i32_to_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.h.l fa0, a0
; RV64IZFH-NEXT: fcvt.h.w fa0, a0
; RV64IZFH-NEXT: ret
%1 = sitofp i32 %a to half
ret half %1