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[AArch64] Fix UB about shift amount exceeds data bit-width

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Summary:
Fixes an UB caught by sanitizer. The shift amount might be larger than 32 so the operand should be 1ULL.
In this patch,  we replace the original expression with  existing API with uint64_t type.

Reviewers: eli.friedman, rengolin

Reviewed By: rengolin

Subscribers: rengolin, javed.absar, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D44234

llvm-svn: 326969
This commit is contained in:
Weiming Zhao 2018-03-08 00:28:25 +00:00
parent aea705310a
commit f016668754
1 changed files with 1 additions and 1 deletions
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lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
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@ -1512,7 +1512,7 @@ static bool isBitfieldExtractOpFromAnd(SelectionDAG *CurDAG, SDNode *N,
// Because of simplify-demanded-bits in DAGCombine, the mask may have been
// simplified. Try to undo that
AndImm |= (1 << NumberOfIgnoredLowBits) - 1;
AndImm |= maskTrailingOnes<uint64_t>(NumberOfIgnoredLowBits);
// The immediate is a mask of the low bits iff imm & (imm+1) == 0
if (AndImm & (AndImm + 1))