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[InstCombine] Add test cases for missing support for turning vector sdiv into udiv. NFC

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llvm-svn: 300434
This commit is contained in:
Craig Topper 2017-04-17 01:51:16 +00:00
parent fd5098109c
commit f025ffb446
2 changed files with 26 additions and 0 deletions
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15
test/Transforms/InstCombine/div-shift.ll
View File

@ -16,6 +16,21 @@ entry:
ret i32 %d
}
define <2 x i32> @t1vec(<2 x i16> %x, <2 x i32> %y) {
; CHECK-LABEL: @t1vec(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CONV:%.*]] = zext <2 x i16> [[X:%.*]] to <2 x i32>
; CHECK-NEXT: [[S:%.*]] = shl nuw <2 x i32> <i32 2, i32 2>, [[Y:%.*]]
; CHECK-NEXT: [[D:%.*]] = sdiv <2 x i32> [[CONV]], [[S]]
; CHECK-NEXT: ret <2 x i32> [[D]]
;
entry:
%conv = zext <2 x i16> %x to <2 x i32>
%s = shl <2 x i32> <i32 2, i32 2>, %y
%d = sdiv <2 x i32> %conv, %s
ret <2 x i32> %d
}
; rdar://11721329
define i64 @t2(i64 %x, i32 %y) {
; CHECK-LABEL: @t2(

11
test/Transforms/InstCombine/div.ll
View File

@ -388,6 +388,17 @@ define i32 @test35(i32 %A) {
ret i32 %mul
}
define <2 x i32> @test35vec(<2 x i32> %A) {
; CHECK-LABEL: @test35vec(
; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[A:%.*]], <i32 2147483647, i32 2147483647>
; CHECK-NEXT: [[MUL:%.*]] = sdiv exact <2 x i32> [[AND]], <i32 2147483647, i32 2147483647>
; CHECK-NEXT: ret <2 x i32> [[MUL]]
;
%and = and <2 x i32> %A, <i32 2147483647, i32 2147483647>
%mul = sdiv exact <2 x i32> %and, <i32 2147483647, i32 2147483647>
ret <2 x i32> %mul
}
define i32 @test36(i32 %A) {
; CHECK-LABEL: @test36(
; CHECK-NEXT: [[AND:%.*]] = and i32 %A, 2147483647