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[PowerPC] Remove UseVSXReg
The UseVSXReg flag can be safely removed and the code cleaned up. Patch By: Yi-Hong Liu Differential Revision: https://reviews.llvm.org/D58685 llvm-svn: 357028
This commit is contained in:
Stefan Pintilie
parent
244f929f25
commit
f062017e37
@ -168,10 +168,7 @@ void PPCAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
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switch (MO.getType()) {
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case MachineOperand::MO_Register: {
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// The MI is INLINEASM ONLY and UseVSXReg is always false.
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unsigned Reg =
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PPCInstrInfo::getRegNumForOperand(MI->getDesc(), MO.getReg(), OpNo);
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const char *RegName = PPCInstPrinter::getRegisterName(Reg);
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const char *RegName = PPCInstPrinter::getRegisterName(MO.getReg());
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// Linux assembler (Others?) does not take register mnemonics.
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// FIXME - What about special registers used in mfspr/mtspr?
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@ -37,14 +37,6 @@ class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
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let TSFlags{2} = PPC970_Cracked;
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let TSFlags{5-3} = PPC970_Unit;
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/// Indicate that the VSX instruction is to use VSX numbering/encoding.
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/// Since ISA 3.0, there are scalar instructions that use the upper
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/// half of the VSX register set only. Rather than adding further complexity
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/// to the register class set, the VSX registers just include the Altivec
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/// registers and this flag decides the numbering to be used for them.
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bits<1> UseVSXReg = 0;
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let TSFlags{6} = UseVSXReg;
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// Indicate that this instruction is of type X-Form Load or Store
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bits<1> XFormMemOp = 0;
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let TSFlags{7} = XFormMemOp;
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@ -73,7 +65,6 @@ class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; }
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class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; }
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class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; }
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class UseVSXReg { bits<1> UseVSXReg = 1; }
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class XFormMemOp { bits<1> XFormMemOp = 1; }
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// Two joined instructions; used to emit two adjacent instructions as one.
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@ -65,9 +65,6 @@ enum {
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/// Shift count to bypass PPC970 flags
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NewDef_Shift = 6,
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/// The VSX instruction that uses VSX register (vs0-vs63), instead of VMX
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/// register (v0-v31).
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UseVSXReg = 0x1 << NewDef_Shift,
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/// This instruction is an X-Form memory operation.
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XFormMemOp = 0x1 << (NewDef_Shift+1)
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};
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@ -440,11 +437,24 @@ public:
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/// operands).
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static unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg,
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unsigned OpNo) {
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if (Desc.TSFlags & PPCII::UseVSXReg) {
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if (isVRRegister(Reg))
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Reg = PPC::VSX32 + (Reg - PPC::V0);
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else if (isVFRegister(Reg))
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Reg = PPC::VSX32 + (Reg - PPC::VF0);
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int16_t regClass = Desc.OpInfo[OpNo].RegClass;
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switch (regClass) {
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// We store F0-F31, VF0-VF31 in MCOperand and it should be F0-F31,
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// VSX32-VSX63 during encoding/disassembling
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case PPC::VSSRCRegClassID:
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case PPC::VSFRCRegClassID:
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if (isVFRegister(Reg))
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return PPC::VSX32 + (Reg - PPC::VF0);
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break;
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// We store VSL0-VSL31, V0-V31 in MCOperand and it should be VSL0-VSL31,
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// VSX32-VSX63 during encoding/disassembling
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case PPC::VSRCRegClassID:
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if (isVRRegister(Reg))
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return PPC::VSX32 + (Reg - PPC::V0);
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break;
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// Other RegClass doesn't need mapping
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default:
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break;
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}
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return Reg;
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}
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@ -123,7 +123,6 @@ def HasOnlySwappingMemOps : Predicate<"!PPCSubTarget->hasP9Vector()">;
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let Predicates = [HasVSX] in {
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let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
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let UseVSXReg = 1 in {
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let hasSideEffects = 0 in { // VSX instructions don't have side effects.
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let Uses = [RM] in {
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@ -894,11 +893,10 @@ let Uses = [RM] in {
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(PPCxxsplt v4i32:$XB, imm32SExt16:$UIM))]>;
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let isCodeGenOnly = 1 in
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def XXSPLTWs : XX2Form_2<60, 164,
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(outs vsrc:$XT), (ins vfrc:$XB, u2imm:$UIM),
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(outs vsrc:$XT), (ins vsfrc:$XB, u2imm:$UIM),
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"xxspltw $XT, $XB, $UIM", IIC_VecPerm, []>;
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} // hasSideEffects
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} // UseVSXReg = 1
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// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
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// instruction selection into a branch sequence.
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@ -1247,7 +1245,7 @@ def HasDirectMove : Predicate<"PPCSubTarget->hasDirectMove()">;
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def NoP9Vector : Predicate<"!PPCSubTarget->hasP9Vector()">;
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let Predicates = [HasP8Vector] in {
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let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
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let isCommutable = 1, UseVSXReg = 1 in {
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let isCommutable = 1 in {
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def XXLEQV : XX3Form<60, 186,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xxleqv $XT, $XA, $XB", IIC_VecGeneral,
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@ -1257,12 +1255,11 @@ let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
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"xxlnand $XT, $XA, $XB", IIC_VecGeneral,
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[(set v4i32:$XT, (vnot_ppc (and v4i32:$XA,
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v4i32:$XB)))]>;
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} // isCommutable, UseVSXReg
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} // isCommutable
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def : Pat<(int_ppc_vsx_xxleqv v4i32:$A, v4i32:$B),
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(XXLEQV $A, $B)>;
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let UseVSXReg = 1 in {
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def XXLORC : XX3Form<60, 170,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xxlorc $XT, $XA, $XB", IIC_VecGeneral,
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@ -1311,7 +1308,6 @@ let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
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"#STIWX",
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[(PPCstfiwx f64:$XT, xoaddr:$dst)]>;
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} // mayStore
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} // UseVSXReg = 1
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def : Pat<(f64 (extloadf32 xoaddr:$src)),
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(COPY_TO_REGCLASS (XFLOADf32 xoaddr:$src), VSFRC)>;
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@ -1341,7 +1337,6 @@ let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
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def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)),
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(SELECT_VSSRC (CRXOR $lhs, $rhs), $tval, $fval)>;
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let UseVSXReg = 1 in {
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// VSX Elementary Scalar FP arithmetic (SP)
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let isCommutable = 1 in {
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def XSADDSP : XX3Form<60, 0,
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@ -1469,7 +1464,6 @@ let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
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"xscvdpspn $XT, $XB", IIC_VecFP, []>;
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def XSCVSPDPN : XX2Form<60, 331, (outs vssrc:$XT), (ins vsrc:$XB),
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"xscvspdpn $XT, $XB", IIC_VecFP, []>;
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} // UseVSXReg = 1
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let Predicates = [IsLittleEndian] in {
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def : Pat<DWToSPExtractConv.El0SS1,
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@ -1516,7 +1510,7 @@ let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
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} // AddedComplexity = 400
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} // HasP8Vector
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let UseVSXReg = 1, AddedComplexity = 400 in {
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let AddedComplexity = 400 in {
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let Predicates = [HasDirectMove] in {
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// VSX direct move instructions
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def MFVSRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vsfrc:$XT),
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@ -1524,7 +1518,7 @@ let Predicates = [HasDirectMove] in {
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[(set i64:$rA, (PPCmfvsr f64:$XT))]>,
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Requires<[In64BitMode]>;
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let isCodeGenOnly = 1 in
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def MFVRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vrrc:$XT),
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def MFVRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vsrc:$XT),
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"mfvsrd $rA, $XT", IIC_VecGeneral,
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[]>,
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Requires<[In64BitMode]>;
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@ -1556,7 +1550,7 @@ let Predicates = [IsISA3_0, HasDirectMove] in {
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[]>, Requires<[In64BitMode]>;
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} // IsISA3_0, HasDirectMove
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} // UseVSXReg = 1
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} // AddedComplexity = 400
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// We want to parse this from asm, but we don't want to emit this as it would
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// be emitted with a VSX reg. So leave Emit = 0 here.
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@ -2414,7 +2408,6 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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list<dag> pattern>
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: X_VT5_XO5_VB5_VSFR<opcode, xo2, xo, opc, pattern>, isDOT;
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let UseVSXReg = 1 in {
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// [PO T XO B XO BX /]
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class XX2_RT5_XO5_XB6<bits<6> opcode, bits<5> xo2, bits<9> xo, string opc,
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list<dag> pattern>
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@ -2433,7 +2426,6 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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InstrItinClass itin, list<dag> pattern>
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: XX3Form<opcode, xo, (outs xty:$XT), (ins aty:$XA, bty:$XB),
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!strconcat(opc, " $XT, $XA, $XB"), itin, pattern>;
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} // UseVSXReg = 1
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// [PO VRT VRA VRB XO /]
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class X_VT5_VA5_VB5<bits<6> opcode, bits<10> xo, string opc,
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@ -2571,8 +2563,7 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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// DP/QP Compare Exponents
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def XSCMPEXPDP : XX3Form_1<60, 59,
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(outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB),
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"xscmpexpdp $crD, $XA, $XB", IIC_FPCompare, []>,
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UseVSXReg;
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"xscmpexpdp $crD, $XA, $XB", IIC_FPCompare, []>;
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def XSCMPEXPQP : X_BF3_VA5_VB5<63, 164, "xscmpexpqp", []>;
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// DP Compare ==, >=, >, !=
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@ -2630,7 +2621,6 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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def : Pat<(f128 (uint_to_fp (i32 (load xoaddr:$src)))),
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(f128 (XSCVUDQP (LIWZX xoaddr:$src)))>;
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let UseVSXReg = 1 in {
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//===--------------------------------------------------------------------===//
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// Round to Floating-Point Integer Instructions
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@ -2647,8 +2637,6 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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[(set v4f32:$XT,
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(int_ppc_vsx_xvcvsphp v4f32:$XB))]>;
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} // UseVSXReg = 1
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// Pattern for matching Vector HP -> Vector SP intrinsic. Defined as a
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// separate pattern so that it can convert the input register class from
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// VRRC(v8i16) to VSRC.
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@ -2690,7 +2678,7 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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// Insert Exponent DP/QP
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// XT NOTE: XT.dword[1] = 0xUUUU_UUUU_UUUU_UUUU
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def XSIEXPDP : XX1Form <60, 918, (outs vsrc:$XT), (ins g8rc:$rA, g8rc:$rB),
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"xsiexpdp $XT, $rA, $rB", IIC_VecFP, []>, UseVSXReg;
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"xsiexpdp $XT, $rA, $rB", IIC_VecFP, []>;
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// vB NOTE: only vB.dword[0] is used, that's why we don't use
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// X_VT5_VA5_VB5 form
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def XSIEXPQP : XForm_18<63, 868, (outs vrrc:$vT), (ins vrrc:$vA, vsfrc:$vB),
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@ -2711,7 +2699,6 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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(v2i64 (XSXEXPQP $vA)), sub_64)))>;
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// Vector Insert Word
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let UseVSXReg = 1 in {
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// XB NOTE: Only XB.dword[1] is used, but we use vsrc on XB.
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def XXINSERTW :
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XX2_RD6_UIM5_RS6<60, 181, (outs vsrc:$XT),
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@ -2725,7 +2712,6 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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def XXEXTRACTUW : XX2_RD6_UIM5_RS6<60, 165,
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(outs vsfrc:$XT), (ins vsrc:$XB, u4imm:$UIMM),
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"xxextractuw $XT, $XB, $UIMM", IIC_VecFP, []>;
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} // UseVSXReg = 1
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// Vector Insert Exponent DP/SP
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def XVIEXPDP : XX3_XT5_XA5_XB5<60, 248, "xviexpdp", vsrc, vsrc, vsrc,
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@ -2758,20 +2744,17 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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//===--------------------------------------------------------------------===//
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// Test Data Class SP/DP/QP
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let UseVSXReg = 1 in {
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def XSTSTDCSP : XX2_BF3_DCMX7_RS6<60, 298,
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(outs crrc:$BF), (ins u7imm:$DCMX, vsfrc:$XB),
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"xststdcsp $BF, $XB, $DCMX", IIC_VecFP, []>;
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def XSTSTDCDP : XX2_BF3_DCMX7_RS6<60, 362,
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(outs crrc:$BF), (ins u7imm:$DCMX, vsfrc:$XB),
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"xststdcdp $BF, $XB, $DCMX", IIC_VecFP, []>;
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} // UseVSXReg = 1
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def XSTSTDCQP : X_BF3_DCMX7_RS5 <63, 708,
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(outs crrc:$BF), (ins u7imm:$DCMX, vrrc:$vB),
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"xststdcqp $BF, $vB, $DCMX", IIC_VecFP, []>;
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// Vector Test Data Class SP/DP
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let UseVSXReg = 1 in {
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def XVTSTDCSP : XX2_RD6_DCMX7_RS6<60, 13, 5,
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(outs vsrc:$XT), (ins u7imm:$DCMX, vsrc:$XB),
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"xvtstdcsp $XT, $XB, $DCMX", IIC_VecFP,
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@ -2782,7 +2765,6 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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"xvtstdcdp $XT, $XB, $DCMX", IIC_VecFP,
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[(set v2i64: $XT,
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(int_ppc_vsx_xvtstdcdp v2f64:$XB, imm:$DCMX))]>;
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} // UseVSXReg = 1
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//===--------------------------------------------------------------------===//
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@ -2823,7 +2805,7 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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// Vector Splat Immediate Byte
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def XXSPLTIB : X_RD6_IMM8<60, 360, (outs vsrc:$XT), (ins u8imm:$IMM8),
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"xxspltib $XT, $IMM8", IIC_VecPerm, []>, UseVSXReg;
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"xxspltib $XT, $IMM8", IIC_VecPerm, []>;
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//===--------------------------------------------------------------------===//
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// Vector/Scalar Load/Store Instructions
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@ -2833,7 +2815,7 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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let mayLoad = 1, mayStore = 0 in {
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// Load Vector
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def LXV : DQ_RD6_RS5_DQ12<61, 1, (outs vsrc:$XT), (ins memrix16:$src),
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"lxv $XT, $src", IIC_LdStLFD, []>, UseVSXReg;
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"lxv $XT, $src", IIC_LdStLFD, []>;
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// Load DWord
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def LXSD : DSForm_1<57, 2, (outs vfrc:$vD), (ins memrix:$src),
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"lxsd $vD, $src", IIC_LdStLFD, []>;
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@ -2846,7 +2828,7 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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class X_XT6_RA5_RB5<bits<6> opcode, bits<10> xo, string opc,
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RegisterOperand vtype, list<dag> pattern>
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: XX1Form_memOp<opcode, xo, (outs vtype:$XT), (ins memrr:$src),
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!strconcat(opc, " $XT, $src"), IIC_LdStLFD, pattern>, UseVSXReg;
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!strconcat(opc, " $XT, $src"), IIC_LdStLFD, pattern>;
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// Load as Integer Byte/Halfword & Zero Indexed
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def LXSIBZX : X_XT6_RA5_RB5<31, 781, "lxsibzx", vsfrc,
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@ -2864,12 +2846,10 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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// Load Vector (Left-justified) with Length
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def LXVL : XX1Form_memOp<31, 269, (outs vsrc:$XT), (ins memr:$src, g8rc:$rB),
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"lxvl $XT, $src, $rB", IIC_LdStLoad,
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[(set v4i32:$XT, (int_ppc_vsx_lxvl addr:$src, i64:$rB))]>,
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UseVSXReg;
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[(set v4i32:$XT, (int_ppc_vsx_lxvl addr:$src, i64:$rB))]>;
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def LXVLL : XX1Form_memOp<31,301, (outs vsrc:$XT), (ins memr:$src, g8rc:$rB),
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"lxvll $XT, $src, $rB", IIC_LdStLoad,
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[(set v4i32:$XT, (int_ppc_vsx_lxvll addr:$src, i64:$rB))]>,
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UseVSXReg;
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[(set v4i32:$XT, (int_ppc_vsx_lxvll addr:$src, i64:$rB))]>;
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// Load Vector Word & Splat Indexed
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def LXVWSX : X_XT6_RA5_RB5<31, 364, "lxvwsx" , vsrc, []>;
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@ -2880,7 +2860,7 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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let mayStore = 1, mayLoad = 0 in {
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// Store Vector
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def STXV : DQ_RD6_RS5_DQ12<61, 5, (outs), (ins vsrc:$XT, memrix16:$dst),
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"stxv $XT, $dst", IIC_LdStSTFD, []>, UseVSXReg;
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"stxv $XT, $dst", IIC_LdStSTFD, []>;
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// Store DWord
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def STXSD : DSForm_1<61, 2, (outs), (ins vfrc:$vS, memrix:$dst),
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"stxsd $vS, $dst", IIC_LdStSTFD, []>;
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@ -2892,7 +2872,7 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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class X_XS6_RA5_RB5<bits<6> opcode, bits<10> xo, string opc,
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RegisterOperand vtype, list<dag> pattern>
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: XX1Form_memOp<opcode, xo, (outs), (ins vtype:$XT, memrr:$dst),
|
||||
!strconcat(opc, " $XT, $dst"), IIC_LdStSTFD, pattern>, UseVSXReg;
|
||||
!strconcat(opc, " $XT, $dst"), IIC_LdStSTFD, pattern>;
|
||||
|
||||
// Store as Integer Byte/Halfword Indexed
|
||||
def STXSIBX : X_XS6_RA5_RB5<31, 909, "stxsibx" , vsfrc,
|
||||
@ -2900,8 +2880,8 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
|
||||
def STXSIHX : X_XS6_RA5_RB5<31, 941, "stxsihx" , vsfrc,
|
||||
[(PPCstxsix f64:$XT, xoaddr:$dst, 2)]>;
|
||||
let isCodeGenOnly = 1 in {
|
||||
def STXSIBXv : X_XS6_RA5_RB5<31, 909, "stxsibx" , vrrc, []>;
|
||||
def STXSIHXv : X_XS6_RA5_RB5<31, 941, "stxsihx" , vrrc, []>;
|
||||
def STXSIBXv : X_XS6_RA5_RB5<31, 909, "stxsibx" , vsrc, []>;
|
||||
def STXSIHXv : X_XS6_RA5_RB5<31, 941, "stxsihx" , vsrc, []>;
|
||||
}
|
||||
|
||||
// Store Vector Halfword*8/Byte*16 Indexed
|
||||
@ -2917,14 +2897,12 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
|
||||
(ins vsrc:$XT, memr:$dst, g8rc:$rB),
|
||||
"stxvl $XT, $dst, $rB", IIC_LdStLoad,
|
||||
[(int_ppc_vsx_stxvl v4i32:$XT, addr:$dst,
|
||||
i64:$rB)]>,
|
||||
UseVSXReg;
|
||||
i64:$rB)]>;
|
||||
def STXVLL : XX1Form_memOp<31, 429, (outs),
|
||||
(ins vsrc:$XT, memr:$dst, g8rc:$rB),
|
||||
"stxvll $XT, $dst, $rB", IIC_LdStLoad,
|
||||
[(int_ppc_vsx_stxvll v4i32:$XT, addr:$dst,
|
||||
i64:$rB)]>,
|
||||
UseVSXReg;
|
||||
i64:$rB)]>;
|
||||
} // mayStore
|
||||
|
||||
let Predicates = [IsLittleEndian] in {
|
||||
@ -3158,109 +3136,109 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
|
||||
let Predicates = [IsBigEndian, HasP9Vector] in {
|
||||
// Scalar stores of i8
|
||||
def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 0)), xoaddr:$dst),
|
||||
(STXSIBXv (v16i8 (VSLDOI $S, $S, 9)), xoaddr:$dst)>;
|
||||
(STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 9)), VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 1)), xoaddr:$dst),
|
||||
(STXSIBXv (v16i8 (VSLDOI $S, $S, 10)), xoaddr:$dst)>;
|
||||
(STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 10)), VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 2)), xoaddr:$dst),
|
||||
(STXSIBXv (v16i8 (VSLDOI $S, $S, 11)), xoaddr:$dst)>;
|
||||
(STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 11)), VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 3)), xoaddr:$dst),
|
||||
(STXSIBXv (v16i8 (VSLDOI $S, $S, 12)), xoaddr:$dst)>;
|
||||
(STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 12)), VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 4)), xoaddr:$dst),
|
||||
(STXSIBXv (v16i8 (VSLDOI $S, $S, 13)), xoaddr:$dst)>;
|
||||
(STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 13)), VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 5)), xoaddr:$dst),
|
||||
(STXSIBXv (v16i8 (VSLDOI $S, $S, 14)), xoaddr:$dst)>;
|
||||
(STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 14)), VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 6)), xoaddr:$dst),
|
||||
(STXSIBXv (v16i8 (VSLDOI $S, $S, 15)), xoaddr:$dst)>;
|
||||
(STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 15)), VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 7)), xoaddr:$dst),
|
||||
(STXSIBXv $S, xoaddr:$dst)>;
|
||||
(STXSIBXv (COPY_TO_REGCLASS $S, VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 8)), xoaddr:$dst),
|
||||
(STXSIBXv (v16i8 (VSLDOI $S, $S, 1)), xoaddr:$dst)>;
|
||||
(STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 1)), VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 9)), xoaddr:$dst),
|
||||
(STXSIBXv (v16i8 (VSLDOI $S, $S, 2)), xoaddr:$dst)>;
|
||||
(STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 2)), VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 10)), xoaddr:$dst),
|
||||
(STXSIBXv (v16i8 (VSLDOI $S, $S, 3)), xoaddr:$dst)>;
|
||||
(STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 3)), VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 11)), xoaddr:$dst),
|
||||
(STXSIBXv (v16i8 (VSLDOI $S, $S, 4)), xoaddr:$dst)>;
|
||||
(STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 4)), VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 12)), xoaddr:$dst),
|
||||
(STXSIBXv (v16i8 (VSLDOI $S, $S, 5)), xoaddr:$dst)>;
|
||||
(STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 5)), VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 13)), xoaddr:$dst),
|
||||
(STXSIBXv (v16i8 (VSLDOI $S, $S, 6)), xoaddr:$dst)>;
|
||||
(STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 6)), VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 14)), xoaddr:$dst),
|
||||
(STXSIBXv (v16i8 (VSLDOI $S, $S, 7)), xoaddr:$dst)>;
|
||||
(STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 7)), VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 15)), xoaddr:$dst),
|
||||
(STXSIBXv (v16i8 (VSLDOI $S, $S, 8)), xoaddr:$dst)>;
|
||||
(STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 8)), VSRC), xoaddr:$dst)>;
|
||||
|
||||
// Scalar stores of i16
|
||||
def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 0)), xoaddr:$dst),
|
||||
(STXSIHXv (v16i8 (VSLDOI $S, $S, 10)), xoaddr:$dst)>;
|
||||
(STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 10)), VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 1)), xoaddr:$dst),
|
||||
(STXSIHXv (v16i8 (VSLDOI $S, $S, 12)), xoaddr:$dst)>;
|
||||
(STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 12)), VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 2)), xoaddr:$dst),
|
||||
(STXSIHXv (v16i8 (VSLDOI $S, $S, 14)), xoaddr:$dst)>;
|
||||
(STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 14)), VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 3)), xoaddr:$dst),
|
||||
(STXSIHXv $S, xoaddr:$dst)>;
|
||||
(STXSIHXv (COPY_TO_REGCLASS $S, VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 4)), xoaddr:$dst),
|
||||
(STXSIHXv (v16i8 (VSLDOI $S, $S, 2)), xoaddr:$dst)>;
|
||||
(STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 2)), VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 5)), xoaddr:$dst),
|
||||
(STXSIHXv (v16i8 (VSLDOI $S, $S, 4)), xoaddr:$dst)>;
|
||||
(STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 4)), VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 6)), xoaddr:$dst),
|
||||
(STXSIHXv (v16i8 (VSLDOI $S, $S, 6)), xoaddr:$dst)>;
|
||||
(STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 6)), VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 7)), xoaddr:$dst),
|
||||
(STXSIHXv (v16i8 (VSLDOI $S, $S, 8)), xoaddr:$dst)>;
|
||||
(STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 8)), VSRC), xoaddr:$dst)>;
|
||||
} // IsBigEndian, HasP9Vector
|
||||
|
||||
let Predicates = [IsLittleEndian, HasP9Vector] in {
|
||||
// Scalar stores of i8
|
||||
def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 0)), xoaddr:$dst),
|
||||
(STXSIBXv (v16i8 (VSLDOI $S, $S, 8)), xoaddr:$dst)>;
|
||||
(STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 8)), VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 1)), xoaddr:$dst),
|
||||
(STXSIBXv (v16i8 (VSLDOI $S, $S, 7)), xoaddr:$dst)>;
|
||||
(STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 7)), VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 2)), xoaddr:$dst),
|
||||
(STXSIBXv (v16i8 (VSLDOI $S, $S, 6)), xoaddr:$dst)>;
|
||||
(STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 6)), VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 3)), xoaddr:$dst),
|
||||
(STXSIBXv (v16i8 (VSLDOI $S, $S, 5)), xoaddr:$dst)>;
|
||||
(STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 5)), VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 4)), xoaddr:$dst),
|
||||
(STXSIBXv (v16i8 (VSLDOI $S, $S, 4)), xoaddr:$dst)>;
|
||||
(STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 4)), VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 5)), xoaddr:$dst),
|
||||
(STXSIBXv (v16i8 (VSLDOI $S, $S, 3)), xoaddr:$dst)>;
|
||||
(STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 3)), VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 6)), xoaddr:$dst),
|
||||
(STXSIBXv (v16i8 (VSLDOI $S, $S, 2)), xoaddr:$dst)>;
|
||||
(STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 2)), VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 7)), xoaddr:$dst),
|
||||
(STXSIBXv (v16i8 (VSLDOI $S, $S, 1)), xoaddr:$dst)>;
|
||||
(STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 1)), VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 8)), xoaddr:$dst),
|
||||
(STXSIBXv $S, xoaddr:$dst)>;
|
||||
(STXSIBXv (COPY_TO_REGCLASS $S, VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 9)), xoaddr:$dst),
|
||||
(STXSIBXv (v16i8 (VSLDOI $S, $S, 15)), xoaddr:$dst)>;
|
||||
(STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 15)), VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 10)), xoaddr:$dst),
|
||||
(STXSIBXv (v16i8 (VSLDOI $S, $S, 14)), xoaddr:$dst)>;
|
||||
(STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 14)), VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 11)), xoaddr:$dst),
|
||||
(STXSIBXv (v16i8 (VSLDOI $S, $S, 13)), xoaddr:$dst)>;
|
||||
(STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 13)), VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 12)), xoaddr:$dst),
|
||||
(STXSIBXv (v16i8 (VSLDOI $S, $S, 12)), xoaddr:$dst)>;
|
||||
(STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 12)), VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 13)), xoaddr:$dst),
|
||||
(STXSIBXv (v16i8 (VSLDOI $S, $S, 11)), xoaddr:$dst)>;
|
||||
(STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 11)), VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 14)), xoaddr:$dst),
|
||||
(STXSIBXv (v16i8 (VSLDOI $S, $S, 10)), xoaddr:$dst)>;
|
||||
(STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 10)), VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 15)), xoaddr:$dst),
|
||||
(STXSIBXv (v16i8 (VSLDOI $S, $S, 9)), xoaddr:$dst)>;
|
||||
(STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 9)), VSRC), xoaddr:$dst)>;
|
||||
|
||||
// Scalar stores of i16
|
||||
def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 0)), xoaddr:$dst),
|
||||
(STXSIHXv (v16i8 (VSLDOI $S, $S, 8)), xoaddr:$dst)>;
|
||||
(STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 8)), VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 1)), xoaddr:$dst),
|
||||
(STXSIHXv (v16i8 (VSLDOI $S, $S, 6)), xoaddr:$dst)>;
|
||||
(STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 6)), VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 2)), xoaddr:$dst),
|
||||
(STXSIHXv (v16i8 (VSLDOI $S, $S, 4)), xoaddr:$dst)>;
|
||||
(STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 4)), VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 3)), xoaddr:$dst),
|
||||
(STXSIHXv (v16i8 (VSLDOI $S, $S, 2)), xoaddr:$dst)>;
|
||||
(STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 2)), VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 4)), xoaddr:$dst),
|
||||
(STXSIHXv $S, xoaddr:$dst)>;
|
||||
(STXSIHXv (COPY_TO_REGCLASS $S, VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 5)), xoaddr:$dst),
|
||||
(STXSIHXv (v16i8 (VSLDOI $S, $S, 14)), xoaddr:$dst)>;
|
||||
(STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 14)), VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 6)), xoaddr:$dst),
|
||||
(STXSIHXv (v16i8 (VSLDOI $S, $S, 12)), xoaddr:$dst)>;
|
||||
(STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 12)), VSRC), xoaddr:$dst)>;
|
||||
def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 7)), xoaddr:$dst),
|
||||
(STXSIHXv (v16i8 (VSLDOI $S, $S, 10)), xoaddr:$dst)>;
|
||||
(STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 10)), VSRC), xoaddr:$dst)>;
|
||||
} // IsLittleEndian, HasP9Vector
|
||||
|
||||
|
||||
|
||||
@ -41,11 +41,11 @@ entry:
|
||||
%splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
|
||||
ret <4 x i32> %splat.splat
|
||||
; CHECK-LABEL: vecuiuc
|
||||
; CHECK: lxsibzx 34, 0, 3
|
||||
; CHECK-NEXT: xxspltw 34, 34, 1
|
||||
; CHECK: lxsibzx 0, 0, 3
|
||||
; CHECK-NEXT: xxspltw 34, 0, 1
|
||||
; CHECK-BE-LABEL: vecuiuc
|
||||
; CHECK-BE: lxsibzx 34, 0, 3
|
||||
; CHECK-BE-NEXT: xxspltw 34, 34, 1
|
||||
; CHECK-BE: lxsibzx 0, 0, 3
|
||||
; CHECK-BE-NEXT: xxspltw 34, 0, 1
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readonly
|
||||
@ -104,11 +104,11 @@ entry:
|
||||
%splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
|
||||
ret <4 x i32> %splat.splat
|
||||
; CHECK-LABEL: vecsiuc
|
||||
; CHECK: lxsibzx 34, 0, 3
|
||||
; CHECK-NEXT: xxspltw 34, 34, 1
|
||||
; CHECK: lxsibzx 0, 0, 3
|
||||
; CHECK-NEXT: xxspltw 34, 0, 1
|
||||
; CHECK-BE-LABEL: vecsiuc
|
||||
; CHECK-BE: lxsibzx 34, 0, 3
|
||||
; CHECK-BE-NEXT: xxspltw 34, 34, 1
|
||||
; CHECK-BE: lxsibzx 0, 0, 3
|
||||
; CHECK-BE-NEXT: xxspltw 34, 0, 1
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readonly
|
||||
@ -350,11 +350,11 @@ entry:
|
||||
%splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
|
||||
ret <4 x i32> %splat.splat
|
||||
; CHECK-LABEL: vecuius
|
||||
; CHECK: lxsihzx 34, 0, 3
|
||||
; CHECK-NEXT: xxspltw 34, 34, 1
|
||||
; CHECK: lxsihzx 0, 0, 3
|
||||
; CHECK-NEXT: xxspltw 34, 0, 1
|
||||
; CHECK-BE-LABEL: vecuius
|
||||
; CHECK-BE: lxsihzx 34, 0, 3
|
||||
; CHECK-BE-NEXT: xxspltw 34, 34, 1
|
||||
; CHECK-BE: lxsihzx 0, 0, 3
|
||||
; CHECK-BE-NEXT: xxspltw 34, 0, 1
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readonly
|
||||
@ -414,11 +414,11 @@ entry:
|
||||
%splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
|
||||
ret <4 x i32> %splat.splat
|
||||
; CHECK-LABEL: vecsius
|
||||
; CHECK: lxsihzx 34, 0, 3
|
||||
; CHECK-NEXT: xxspltw 34, 34, 1
|
||||
; CHECK: lxsihzx 0, 0, 3
|
||||
; CHECK-NEXT: xxspltw 34, 0, 1
|
||||
; CHECK-BE-LABEL: vecsius
|
||||
; CHECK-BE: lxsihzx 34, 0, 3
|
||||
; CHECK-BE-NEXT: xxspltw 34, 34, 1
|
||||
; CHECK-BE: lxsihzx 0, 0, 3
|
||||
; CHECK-BE-NEXT: xxspltw 34, 0, 1
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readonly
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user