RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-01-31 20:51:52 +01:00
Code Issues Projects Releases Wiki Activity

[mips] Small update to the implementation of eh.return for Mips.

Browse Source 
This patch initializes t9 to the handler address, but only if the relocation
model is pic. This handles the case where handler to which eh.return jumps 
points to the start of the function.

Patch by Sasa Stankovic.

llvm-svn: 178588
This commit is contained in:
Akira Hatanaka 2013-04-02 23:02:07 +00:00
parent c6f97cf1a0
commit f08d3a5a83
3 changed files with 12 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
lib/Target/Mips/MipsSEInstrInfo.cpp
View File

@ -387,6 +387,7 @@ void MipsSEInstrInfo::ExpandEhReturn(MachineBasicBlock &MBB,
unsigned JR = STI.isABI_N64() ? Mips::JR64 : Mips::JR; unsigned JR = STI.isABI_N64() ? Mips::JR64 : Mips::JR;
unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP; unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
unsigned RA = STI.isABI_N64() ? Mips::RA_64 : Mips::RA; unsigned RA = STI.isABI_N64() ? Mips::RA_64 : Mips::RA;
unsigned T9 = STI.isABI_N64() ? Mips::T9_64 : Mips::T9;
unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
unsigned OffsetReg = I->getOperand(0).getReg(); unsigned OffsetReg = I->getOperand(0).getReg();
unsigned TargetReg = I->getOperand(1).getReg(); unsigned TargetReg = I->getOperand(1).getReg();
@ -394,6 +395,9 @@ void MipsSEInstrInfo::ExpandEhReturn(MachineBasicBlock &MBB,
// or $ra, $v0, $zero // or $ra, $v0, $zero
// addu $sp, $sp, $v1 // addu $sp, $sp, $v1
// jr $ra // jr $ra
if (TM.getRelocationModel() == Reloc::PIC_)
BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(OR), T9)
.addReg(TargetReg).addReg(ZERO);
BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(OR), RA) BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(OR), RA)
.addReg(TargetReg).addReg(ZERO); .addReg(TargetReg).addReg(ZERO);
BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), SP) BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), SP)

4
test/CodeGen/Mips/eh-return32.ll
View File

@ -37,7 +37,9 @@ entry:
; CHECK: lw $7, [[offset3]]($sp) ; CHECK: lw $7, [[offset3]]($sp)
; check that stack is adjusted by $v1 and that code returns to address in $v0 ; check that stack is adjusted by $v1 and that code returns to address in $v0
; also check that $25 contains handler value
; CHECK: addiu $sp, $sp, [[spoffset]] ; CHECK: addiu $sp, $sp, [[spoffset]]
; CHECK: move $25, $2
; CHECK: move $ra, $2 ; CHECK: move $ra, $2
; CHECK: jr $ra ; CHECK: jr $ra
; CHECK: addu $sp, $sp, $3 ; CHECK: addu $sp, $sp, $3
@ -74,7 +76,9 @@ entry:
; CHECK: lw $7, [[offset3]]($sp) ; CHECK: lw $7, [[offset3]]($sp)
; check that stack is adjusted by $v1 and that code returns to address in $v0 ; check that stack is adjusted by $v1 and that code returns to address in $v0
; also check that $25 contains handler value
; CHECK: addiu $sp, $sp, [[spoffset]] ; CHECK: addiu $sp, $sp, [[spoffset]]
; CHECK: move $25, $2
; CHECK: move $ra, $2 ; CHECK: move $ra, $2
; CHECK: jr $ra ; CHECK: jr $ra
; CHECK: addu $sp, $sp, $3 ; CHECK: addu $sp, $sp, $3

4
test/CodeGen/Mips/eh-return64.ll
View File

@ -37,7 +37,9 @@ entry:
; CHECK: ld $7, [[offset3]]($sp) ; CHECK: ld $7, [[offset3]]($sp)
; check that stack is adjusted by $v1 and that code returns to address in $v0 ; check that stack is adjusted by $v1 and that code returns to address in $v0
; also check that $25 contains handler value
; CHECK: daddiu $sp, $sp, [[spoffset]] ; CHECK: daddiu $sp, $sp, [[spoffset]]
; CHECK: move $25, $2
; CHECK: move $ra, $2 ; CHECK: move $ra, $2
; CHECK: jr $ra ; CHECK: jr $ra
; CHECK: daddu $sp, $sp, $3 ; CHECK: daddu $sp, $sp, $3
@ -75,7 +77,9 @@ entry:
; CHECK: ld $7, [[offset3]]($sp) ; CHECK: ld $7, [[offset3]]($sp)
; check that stack is adjusted by $v1 and that code returns to address in $v0 ; check that stack is adjusted by $v1 and that code returns to address in $v0
; also check that $25 contains handler value
; CHECK: daddiu $sp, $sp, [[spoffset]] ; CHECK: daddiu $sp, $sp, [[spoffset]]
; CHECK: move $25, $2
; CHECK: move $ra, $2 ; CHECK: move $ra, $2
; CHECK: jr $ra ; CHECK: jr $ra
; CHECK: daddu $sp, $sp, $3 ; CHECK: daddu $sp, $sp, $3