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https://github.com/RPCS3/llvm-mirror.git
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[PowerPC] folding rlwinm + rlwinm to rlwinm
For example:
x3 = rlwinm x3, 27, 5, 31
x3 = rlwinm x3, 19, 0, 12
can be combined to
x3 = rlwinm x3, 14, 0, 12
Reviewed by: steven.zhang, lkail
Differential Revision: https://reviews.llvm.org/D70374
This commit is contained in:
czhengsz
parent
5315599528
commit
f0adb8a850
@ -18,6 +18,7 @@
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//
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//===---------------------------------------------------------------------===//
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#include "MCTargetDesc/PPCMCTargetDesc.h"
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#include "MCTargetDesc/PPCPredicates.h"
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#include "PPC.h"
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#include "PPCInstrBuilder.h"
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@ -806,6 +807,143 @@ bool PPCMIPeephole::simplifyCode(void) {
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combineSEXTAndSHL(MI, ToErase);
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break;
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}
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case PPC::RLWINM:
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case PPC::RLWINMo:
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case PPC::RLWINM8:
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case PPC::RLWINM8o: {
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unsigned FoldingReg = MI.getOperand(1).getReg();
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if (!Register::isVirtualRegister(FoldingReg))
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break;
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MachineInstr *SrcMI = MRI->getVRegDef(FoldingReg);
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if (SrcMI->getOpcode() != PPC::RLWINM &&
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SrcMI->getOpcode() != PPC::RLWINMo &&
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SrcMI->getOpcode() != PPC::RLWINM8 &&
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SrcMI->getOpcode() != PPC::RLWINM8o)
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break;
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assert((MI.getOperand(2).isImm() && MI.getOperand(3).isImm() &&
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MI.getOperand(4).isImm() && SrcMI->getOperand(2).isImm() &&
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SrcMI->getOperand(3).isImm() && SrcMI->getOperand(4).isImm()) &&
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"Invalid PPC::RLWINM Instruction!");
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uint64_t SHSrc = SrcMI->getOperand(2).getImm();
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uint64_t SHMI = MI.getOperand(2).getImm();
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uint64_t MBSrc = SrcMI->getOperand(3).getImm();
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uint64_t MBMI = MI.getOperand(3).getImm();
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uint64_t MESrc = SrcMI->getOperand(4).getImm();
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uint64_t MEMI = MI.getOperand(4).getImm();
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assert((MEMI < 32 && MESrc < 32 && MBMI < 32 && MBSrc < 32) &&
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"Invalid PPC::RLWINM Instruction!");
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// If MBMI is bigger than MEMI, we always can not get run of ones.
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// RotatedSrcMask non-wrap:
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// 0........31|32........63
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// RotatedSrcMask: B---E B---E
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// MaskMI: -----------|--E B------
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// Result: ----- --- (Bad candidate)
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//
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// RotatedSrcMask wrap:
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// 0........31|32........63
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// RotatedSrcMask: --E B----|--E B----
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// MaskMI: -----------|--E B------
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// Result: --- -----|--- ----- (Bad candidate)
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//
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// One special case is RotatedSrcMask is a full set mask.
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// RotatedSrcMask full:
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// 0........31|32........63
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// RotatedSrcMask: ------EB---|-------EB---
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// MaskMI: -----------|--E B------
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// Result: -----------|--- ------- (Good candidate)
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// Mark special case.
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bool SrcMaskFull = (MBSrc - MESrc == 1) || (MBSrc == 0 && MESrc == 31);
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// For other MBMI > MEMI cases, just return.
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if ((MBMI > MEMI) && !SrcMaskFull)
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break;
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// Handle MBMI <= MEMI cases.
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APInt MaskMI = APInt::getBitsSetWithWrap(32, 32 - MEMI - 1, 32 - MBMI);
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// In MI, we only need low 32 bits of SrcMI, just consider about low 32
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// bit of SrcMI mask. Note that in APInt, lowerest bit is at index 0,
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// while in PowerPC ISA, lowerest bit is at index 63.
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APInt MaskSrc =
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APInt::getBitsSetWithWrap(32, 32 - MESrc - 1, 32 - MBSrc);
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// Current APInt::getBitsSetWithWrap sets all bits to 0 if loBit is
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// equal to highBit.
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// If MBSrc - MESrc == 1, we expect a full set mask instead of Null.
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if (SrcMaskFull && (MBSrc - MESrc == 1))
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MaskSrc.setAllBits();
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APInt RotatedSrcMask = MaskSrc.rotl(SHMI);
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APInt FinalMask = RotatedSrcMask & MaskMI;
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uint32_t NewMB, NewME;
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// If final mask is 0, MI result should be 0 too.
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if (FinalMask.isNullValue()) {
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bool Is64Bit = (MI.getOpcode() == PPC::RLWINM8 ||
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MI.getOpcode() == PPC::RLWINM8o);
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LLVM_DEBUG(dbgs() << "Replace Instr: ");
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LLVM_DEBUG(MI.dump());
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if (MI.getOpcode() == PPC::RLWINM || MI.getOpcode() == PPC::RLWINM8) {
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// Replace MI with "LI 0"
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MI.RemoveOperand(4);
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MI.RemoveOperand(3);
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MI.RemoveOperand(2);
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MI.getOperand(1).ChangeToImmediate(0);
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MI.setDesc(TII->get(Is64Bit ? PPC::LI8 : PPC::LI));
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} else {
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// Replace MI with "ANDIo reg, 0"
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MI.RemoveOperand(4);
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MI.RemoveOperand(3);
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MI.getOperand(2).setImm(0);
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MI.setDesc(TII->get(Is64Bit ? PPC::ANDIo8 : PPC::ANDIo));
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}
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Simplified = true;
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NumRotatesCollapsed++;
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LLVM_DEBUG(dbgs() << "With: ");
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LLVM_DEBUG(MI.dump());
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} else if (isRunOfOnes((unsigned)(FinalMask.getZExtValue()), NewMB,
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NewME) || SrcMaskFull) {
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// If FoldingReg has only one use and it it not RLWINMo and
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// RLWINM8o, safe to delete its def SrcMI. Otherwise keep it.
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if (MRI->hasOneNonDBGUse(FoldingReg) &&
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(SrcMI->getOpcode() == PPC::RLWINM ||
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SrcMI->getOpcode() == PPC::RLWINM8)) {
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ToErase = SrcMI;
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LLVM_DEBUG(dbgs() << "Delete dead instruction: ");
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LLVM_DEBUG(SrcMI->dump());
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}
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LLVM_DEBUG(dbgs() << "Converting Instr: ");
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LLVM_DEBUG(MI.dump());
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uint16_t NewSH = (SHSrc + SHMI) % 32;
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MI.getOperand(2).setImm(NewSH);
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// If SrcMI mask is full, no need to update MBMI and MEMI.
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if (!SrcMaskFull) {
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MI.getOperand(3).setImm(NewMB);
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MI.getOperand(4).setImm(NewME);
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}
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MI.getOperand(1).setReg(SrcMI->getOperand(1).getReg());
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if (SrcMI->getOperand(1).isKill()) {
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MI.getOperand(1).setIsKill(true);
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SrcMI->getOperand(1).setIsKill(false);
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} else
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// About to replace MI.getOperand(1), clear its kill flag.
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MI.getOperand(1).setIsKill(false);
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Simplified = true;
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NumRotatesCollapsed++;
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LLVM_DEBUG(dbgs() << "To: ");
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LLVM_DEBUG(MI.dump());
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}
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break;
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}
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}
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}
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@ -11,8 +11,7 @@ define void @foo(i32 signext %var1) {
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; CHECK-NEXT: xori r3, r3, 1
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; CHECK-NEXT: addis r4, r2, res@toc@ha
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; CHECK-NEXT: cntlzw r3, r3
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; CHECK-NEXT: srwi r3, r3, 5
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; CHECK-NEXT: slwi r3, r3, 19
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; CHECK-NEXT: rlwinm r3, r3, 14, 0, 12
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; CHECK-NEXT: stw r3, res@toc@l(r4)
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; CHECK-NEXT: blr
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entry:
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@ -30,10 +29,10 @@ define void @foo_multiple_use(i32 signext %var1) {
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; CHECK-NEXT: addis r4, r2, res2@toc@ha
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; CHECK-NEXT: addis r6, r2, res@toc@ha
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; CHECK-NEXT: cntlzw r3, r3
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; CHECK-NEXT: srwi r3, r3, 5
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; CHECK-NEXT: slwi r5, r3, 19
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; CHECK-NEXT: stw r3, res2@toc@l(r4)
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; CHECK-NEXT: stw r5, res@toc@l(r6)
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; CHECK-NEXT: srwi r5, r3, 5
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; CHECK-NEXT: rlwinm r3, r3, 14, 0, 12
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; CHECK-NEXT: stw r5, res2@toc@l(r4)
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; CHECK-NEXT: stw r3, res@toc@l(r6)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp eq i32 %var1, 1
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140
test/CodeGen/PowerPC/fold-rlwinm.mir
Normal file
140
test/CodeGen/PowerPC/fold-rlwinm.mir
Normal file
@ -0,0 +1,140 @@
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# RUN: llc -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu \
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# RUN: -run-pass ppc-mi-peepholes %s -o - -verify-machineinstrs | FileCheck %s
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---
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name: testFoldRLWINM
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#CHECK : name : testFoldRLWINM
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x3
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%0:g8rc = COPY $x3
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%1:gprc = COPY %0.sub_32:g8rc
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%2:gprc = RLWINM %1:gprc, 27, 5, 31
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; CHECK-NOT: %2:gprc = RLWINM %1:gprc, 27, 5, 31
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%3:gprc = RLWINM %2:gprc, 19, 0, 12
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; CHECK: %3:gprc = RLWINM %1, 14, 0, 12
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BLR8 implicit $lr8, implicit $rm
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...
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---
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name: testFoldRLWINMSrcFullMask1
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#CHECK : name : testFoldRLWINMSrcFullMask1
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x3
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%0:g8rc = COPY $x3
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%1:gprc = COPY %0.sub_32:g8rc
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%2:gprc = RLWINM %1:gprc, 27, 0, 31
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; CHECK-NOT: %2:gprc = RLWINM %1:gprc, 27, 0, 31
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%3:gprc = RLWINM %2:gprc, 19, 0, 12
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; CHECK: %3:gprc = RLWINM %1, 14, 0, 12
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BLR8 implicit $lr8, implicit $rm
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...
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---
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name: testFoldRLWINMSrcFullMask2
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#CHECK : name : testFoldRLWINMSrcFullMask2
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x3
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%0:g8rc = COPY $x3
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%1:gprc = COPY %0.sub_32:g8rc
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%2:gprc = RLWINM %1:gprc, 27, 10, 9
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; CHECK-NOT: %2:gprc = RLWINM %1:gprc, 27, 10, 9
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%3:gprc = RLWINM %2:gprc, 19, 10, 1
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; CHECK: %3:gprc = RLWINM %1, 14, 10, 1
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BLR8 implicit $lr8, implicit $rm
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...
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---
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name: testFoldRLWINMSrcWrapped
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#CHECK : name : testFoldRLWINMSrcWrapped
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x3
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%0:g8rc = COPY $x3
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%1:gprc = COPY %0.sub_32:g8rc
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%2:gprc = RLWINM %1:gprc, 27, 30, 10
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; CHECK-NOT: %2:gprc = RLWINM %1:gprc, 27, 30 ,10
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%3:gprc = RLWINM %2:gprc, 19, 0, 12
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; CHECK: %3:gprc = RLWINM %1, 14, 11, 12
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BLR8 implicit $lr8, implicit $rm
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...
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---
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name: testFoldRLWINMUserWrapped
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#CHECK : name : testFoldRLWINMUserWrapped
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x3
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%0:g8rc = COPY $x3
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%1:gprc = COPY %0.sub_32:g8rc
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%2:gprc = RLWINM %1:gprc, 10, 5, 31
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; CHECKT: %2:gprc = RLWINM %1:gprc, 10, 5, 31
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%3:gprc = RLWINM %2:gprc, 10, 30, 5
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; CHECK: %3:gprc = RLWINM %2, 10, 30, 5
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BLR8 implicit $lr8, implicit $rm
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...
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---
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name: testFoldRLWINMMultipleUses
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#CHECK : name : testFoldRLWINMMultipleUses
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x3
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%0:g8rc = COPY $x3
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%1:gprc = COPY %0.sub_32:g8rc
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%2:gprc = RLWINM killed %1:gprc, 27, 5, 31
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; CHECK: %2:gprc = RLWINM %1, 27, 5, 31
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%3:gprc = RLWINM %2:gprc, 19, 0, 12
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; CHECK: %3:gprc = RLWINM killed %1, 14, 0, 12
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STW %3:gprc, %2:gprc, 100
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; CHECK: STW %3, %2, 100
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BLR8 implicit $lr8, implicit $rm
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...
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---
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name: testFoldRLWINMToZero
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#CHECK : name : testFoldRLWINMToZero
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x3
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%0:g8rc = COPY $x3
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%1:gprc = COPY %0.sub_32:g8rc
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%2:gprc = RLWINM %1:gprc, 27, 5, 10
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; CHECK-NOT: %2:gprc = RLWINM %1:gprc, 27, 5, 10
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%3:gprc = RLWINM %2:gprc, 8, 5, 10
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; CHECK: %3:gprc = LI 0
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BLR8 implicit $lr8, implicit $rm
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...
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---
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name: testFoldRLWINMoToZero
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#CHECK : name : testFoldRLWINMoToZero
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x3
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%0:g8rc = COPY $x3
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%1:gprc = COPY %0.sub_32:g8rc
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%2:gprc = RLWINM %1:gprc, 27, 5, 10
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; CHECK-NOT: %2:gprc = RLWINM %1:gprc, 27, 5, 10
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%3:gprc = RLWINMo %2:gprc, 8, 5, 10, implicit-def $cr0
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; CHECK: %3:gprc = ANDIo %2, 0, implicit-def $cr0
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BLR8 implicit $lr8, implicit $rm
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...
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---
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name: testFoldRLWINMInvalidMask
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#CHECK : name : testFoldRLWINMInvalidMask
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x3
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%0:g8rc = COPY $x3
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%1:gprc = COPY %0.sub_32:g8rc
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%2:gprc = RLWINM %1:gprc, 20, 5, 31
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; CHECK: %2:gprc = RLWINM %1, 20, 5, 31
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%3:gprc = RLWINM %2:gprc, 19, 10, 20
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; CHECK: %3:gprc = RLWINM %2, 19, 10, 20
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BLR8 implicit $lr8, implicit $rm
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...
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