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handle the "mov reg1, reg2" case in isMoveInstr

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llvm-svn: 28945
This commit is contained in:
Rafael Espindola 2006-06-27 21:52:45 +00:00
parent 852423b469
commit f11f34a3d6
3 changed files with 20 additions and 6 deletions
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10
lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -183,10 +183,12 @@ void ARMDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
ScheduleAndEmitDAG(DAG);
}
static void SelectFrameIndex(SelectionDAG *CurDAG, SDOperand &Result, SDNode *N) {
static void SelectFrameIndex(SelectionDAG *CurDAG, SDOperand &Result, SDNode *N, SDOperand Op) {
int FI = cast<FrameIndexSDNode>(N)->getIndex();
Result = CurDAG->SelectNodeTo(N, ARM::movrr, MVT::i32,
CurDAG->getTargetFrameIndex(FI, MVT::i32));
SDOperand TFI = CurDAG->getTargetFrameIndex(FI, Op.getValueType());
Result = CurDAG->SelectNodeTo(N, ARM::movri, Op.getValueType(), TFI);
}
void ARMDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
@ -198,7 +200,7 @@ void ARMDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
break;
case ISD::FrameIndex:
SelectFrameIndex(CurDAG, Result, N);
SelectFrameIndex(CurDAG, Result, N, Op);
break;
}
}

14
lib/Target/ARM/ARMInstrInfo.cpp
View File

@ -27,7 +27,19 @@ ARMInstrInfo::ARMInstrInfo()
///
bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI,
unsigned &SrcReg, unsigned &DstReg) const {
return false;
MachineOpCode oc = MI.getOpcode();
switch (oc) {
default:
return false;
case ARM::movrr:
assert(MI.getNumOperands() == 2 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
"Invalid ARM MOV instruction");
SrcReg = MI.getOperand(1).getReg();;
DstReg = MI.getOperand(0).getReg();;
return true;
}
}
/// isLoadFromStackSlot - If the specified machine instruction is a direct

2
lib/Target/ARM/ARMRegisterInfo.cpp
View File

@ -81,7 +81,7 @@ ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
MachineBasicBlock &MBB = *MI.getParent();
MachineFunction &MF = *MBB.getParent();
assert (MI.getOpcode() == ARM::movrr);
assert (MI.getOpcode() == ARM::movri);
unsigned FrameIdx = 1;