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Add Rt2 to the asm format string for 32-bit Thumb load/store register dual

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instructions.  Thumb does not have the restriction that t2 = t+1.

llvm-svn: 92785
This commit is contained in:
Johnny Chen 2010-01-05 21:51:46 +00:00
parent fd23a9b6dd
commit f15fb27ffd
1 changed files with 3 additions and 3 deletions
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6
lib/Target/ARM/ARMInstrThumb2.td
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@ -818,10 +818,10 @@ let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
// Load doubleword
def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs GPR:$dst1, GPR:$dst2),
(ins t2addrmode_imm8s4:$addr),
IIC_iLoadi, "ldrd", "\t$dst1, $addr", []>;
IIC_iLoadi, "ldrd", "\t$dst1, $dst2, $addr", []>;
def t2LDRDpci : T2Ii8s4<?, ?, 1, (outs GPR:$dst1, GPR:$dst2),
(ins i32imm:$addr), IIC_iLoadi,
"ldrd", "\t$dst1, $addr", []> {
"ldrd", "\t$dst1, $dst2, $addr", []> {
let Inst{19-16} = 0b1111; // Rn
}
}
@ -934,7 +934,7 @@ defm t2STRH : T2I_st<0b01, "strh", BinOpFrag<(truncstorei16 node:$LHS, node:$RH
let mayLoad = 1, hasExtraSrcRegAllocReq = 1 in
def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
(ins GPR:$src1, GPR:$src2, t2addrmode_imm8s4:$addr),
IIC_iStorer, "strd", "\t$src1, $addr", []>;
IIC_iStorer, "strd", "\t$src1, $src2, $addr", []>;
// Indexed stores
def t2STR_PRE : T2Iidxldst<0, 0b10, 0, 1, (outs GPR:$base_wb),