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[SelectionDAG] ComputeNumSignBits - add ISD::ADD vector support

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Add missing handling for (ADD (AND X, 1), -1) uniform vectors
This commit is contained in:
Simon Pilgrim 2020-01-23 16:41:57 +00:00
parent 94ace0b9c4
commit f1b4b4c1bb
2 changed files with 8 additions and 25 deletions
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15
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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@ -3760,13 +3760,13 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
case ISD::ADDC:
// Add can have at most one carry bit. Thus we know that the output
// is, at worst, one more bit than the inputs.
Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
if (Tmp == 1) return 1; // Early out.
Tmp = ComputeNumSignBits(Op.getOperand(0), Depth + 1);
if (Tmp == 1) return 1; // Early out.
// Special case decrementing a value (ADD X, -1):
if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
if (ConstantSDNode *CRHS = isConstOrConstSplat(Op.getOperand(1)))
if (CRHS->isAllOnesValue()) {
KnownBits Known = computeKnownBits(Op.getOperand(0), Depth+1);
KnownBits Known = computeKnownBits(Op.getOperand(0), Depth + 1);
// If the input is known to be 0 or 1, the output is 0/-1, which is all
// sign bits set.
@ -3779,10 +3779,9 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
return Tmp;
}
Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1);
if (Tmp2 == 1) return 1;
return std::min(Tmp, Tmp2)-1;
Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth + 1);
if (Tmp2 == 1) return 1; // Early out.
return std::min(Tmp, Tmp2) - 1;
case ISD::SUB:
Tmp2 = ComputeNumSignBits(Op.getOperand(1), DemandedElts, Depth + 1);
if (Tmp2 == 1) return 1; // Early out.

18
test/CodeGen/X86/sar_fold64.ll
View File

@ -135,16 +135,7 @@ define <4 x i32> @all_sign_bit_ashr_vec2(<4 x i32> %x) {
; SSE: # %bb.0:
; SSE-NEXT: pand {{.*}}(%rip), %xmm0
; SSE-NEXT: pcmpeqd %xmm1, %xmm1
; SSE-NEXT: paddd %xmm0, %xmm1
; SSE-NEXT: movdqa %xmm1, %xmm0
; SSE-NEXT: psrad $5, %xmm0
; SSE-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
; SSE-NEXT: movdqa %xmm1, %xmm2
; SSE-NEXT: psrad $31, %xmm2
; SSE-NEXT: psrad $1, %xmm1
; SSE-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,3],xmm0[0,3]
; SSE-NEXT: movaps %xmm1, %xmm0
; SSE-NEXT: paddd %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX1-LABEL: all_sign_bit_ashr_vec2:
@ -152,12 +143,6 @@ define <4 x i32> @all_sign_bit_ashr_vec2(<4 x i32> %x) {
; AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpsrad $31, %xmm0, %xmm1
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm0[4,5,6,7]
; AVX1-NEXT: vpsrad $5, %xmm0, %xmm2
; AVX1-NEXT: vpsrad $1, %xmm0, %xmm0
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7]
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; AVX1-NEXT: retq
;
; AVX2-LABEL: all_sign_bit_ashr_vec2:
@ -166,7 +151,6 @@ define <4 x i32> @all_sign_bit_ashr_vec2(<4 x i32> %x) {
; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
%and = and <4 x i32> %x, <i32 1, i32 1, i32 1 , i32 1>
%add = add <4 x i32> %and, <i32 -1, i32 -1, i32 -1, i32 -1>