mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2025-01-31 20:51:52 +01:00
[mips][microMIPS] Implement JRADDIUSP instruction
Differential Revision: http://reviews.llvm.org/D5046 llvm-svn: 217681
This commit is contained in:
parent
b47e7e1e1d
commit
f1edd29dad
@ -344,6 +344,25 @@ getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned MipsMCCodeEmitter::
|
||||
getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo,
|
||||
SmallVectorImpl<MCFixup> &Fixups,
|
||||
const MCSubtargetInfo &STI) const {
|
||||
|
||||
const MCOperand &MO = MI.getOperand(OpNo);
|
||||
if (MO.isImm()) {
|
||||
// The immediate is encoded as 'immediate << 2'.
|
||||
unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
|
||||
assert((Res & 3) == 0);
|
||||
return Res >> 2;
|
||||
}
|
||||
|
||||
assert(MO.isExpr() &&
|
||||
"getUImm5Lsl2Encoding expects only expressions or an immediate");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned MipsMCCodeEmitter::
|
||||
getExprOpValue(const MCExpr *Expr,SmallVectorImpl<MCFixup> &Fixups,
|
||||
const MCSubtargetInfo &STI) const {
|
||||
|
@ -74,6 +74,12 @@ public:
|
||||
SmallVectorImpl<MCFixup> &Fixups,
|
||||
const MCSubtargetInfo &STI) const;
|
||||
|
||||
// getUImm5Lsl2Encoding - Return binary encoding of the microMIPS jump
|
||||
// target operand.
|
||||
unsigned getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo,
|
||||
SmallVectorImpl<MCFixup> &Fixups,
|
||||
const MCSubtargetInfo &STI) const;
|
||||
|
||||
// getBranchTargetOpValue - Return binary encoding of the branch
|
||||
// target operand. If the machine operand requires relocation,
|
||||
// record the relocation and return zero.
|
||||
|
@ -72,6 +72,17 @@ class MFHILO_FM_MM16<bits<5> funct> {
|
||||
let Inst{4-0} = rd;
|
||||
}
|
||||
|
||||
class JRADDIUSP_FM_MM16<bits<5> op> {
|
||||
bits<5> rs;
|
||||
bits<5> imm;
|
||||
|
||||
bits<16> Inst;
|
||||
|
||||
let Inst{15-10} = 0x11;
|
||||
let Inst{9-5} = op;
|
||||
let Inst{4-0} = imm;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// MicroMIPS 32-bit Instruction Formats
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
@ -4,6 +4,10 @@ def simm12 : Operand<i32> {
|
||||
let DecoderMethod = "DecodeSimm12";
|
||||
}
|
||||
|
||||
def uimm5_lsl2 : Operand<OtherVT> {
|
||||
let EncoderMethod = "getUImm5Lsl2Encoding";
|
||||
}
|
||||
|
||||
def mem_mm_12 : Operand<i32> {
|
||||
let PrintMethod = "printMemOperand";
|
||||
let MIOperandInfo = (ops GPR32, simm12);
|
||||
@ -104,6 +108,17 @@ class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
|
||||
let Defs = [RA];
|
||||
}
|
||||
|
||||
// Base class for JRADDIUSP instruction.
|
||||
class JumpRAddiuStackMM16 :
|
||||
MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jraddiusp\t$imm",
|
||||
[], IIBranch, FrmR> {
|
||||
let isTerminator = 1;
|
||||
let isBarrier = 1;
|
||||
let hasDelaySlot = 1;
|
||||
let isBranch = 1;
|
||||
let isIndirectBranch = 1;
|
||||
}
|
||||
|
||||
// MicroMIPS Jump and Link (Call) - Short Delay Slot
|
||||
let isCall = 1, hasDelaySlot = 1, Defs = [RA] in {
|
||||
class JumpLinkMM<string opstr, DAGOperand opnd> :
|
||||
@ -126,6 +141,7 @@ def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
|
||||
def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
|
||||
def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
|
||||
def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>;
|
||||
def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>;
|
||||
|
||||
class WaitMM<string opstr> :
|
||||
InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [],
|
||||
|
@ -13,6 +13,8 @@
|
||||
# CHECK-EL: mflo $9 # encoding: [0x49,0x46]
|
||||
# CHECK-EL: move $25, $1 # encoding: [0x21,0x0f]
|
||||
# CHECK-EL: jalr $9 # encoding: [0xc9,0x45]
|
||||
# CHECK-EL: jraddiusp 20 # encoding: [0x05,0x47]
|
||||
# CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
#------------------------------------------------------------------------------
|
||||
# Big endian
|
||||
#------------------------------------------------------------------------------
|
||||
@ -20,8 +22,11 @@
|
||||
# CHECK-EB: mflo $9 # encoding: [0x46,0x49]
|
||||
# CHECK-EB: move $25, $1 # encoding: [0x0f,0x21]
|
||||
# CHECK-EB: jalr $9 # encoding: [0x45,0xc9]
|
||||
# CHECK-EB: jraddiusp 20 # encoding: [0x47,0x05]
|
||||
# CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
|
||||
mfhi $9
|
||||
mflo $9
|
||||
move $25, $1
|
||||
jalr $9
|
||||
jraddiusp 20
|
||||
|
Loading…
x
Reference in New Issue
Block a user