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[ARM] Update ReconstructShuffle to handle mismatched types
Summary: Port the ReconstructShuffle function from AArch64 to ARM to handle mismatched incoming types in the BUILD_VECTOR node. This fixes an outstanding FIXME in the ReconstructShuffle code. Reviewers: t.p.northover, rengolin Subscribers: aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D11720 llvm-svn: 244314
This commit is contained in:
Silviu Baranga
parent
093484721d
commit
f1f3f2018c
@ -5529,18 +5529,46 @@ SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
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return SDValue();
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}
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/// getExtFactor - Determine the adjustment factor for the position when
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/// generating an "extract from vector registers" instruction.
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static unsigned getExtFactor(SDValue &V) {
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EVT EltType = V.getValueType().getVectorElementType();
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return EltType.getSizeInBits() / 8;
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}
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// Gather data to see if the operation can be modelled as a
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// shuffle in combination with VEXTs.
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SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
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SelectionDAG &DAG) const {
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assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
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SDLoc dl(Op);
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EVT VT = Op.getValueType();
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unsigned NumElts = VT.getVectorNumElements();
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SmallVector<SDValue, 2> SourceVecs;
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SmallVector<unsigned, 2> MinElts;
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SmallVector<unsigned, 2> MaxElts;
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struct ShuffleSourceInfo {
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SDValue Vec;
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unsigned MinElt;
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unsigned MaxElt;
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// We may insert some combination of BITCASTs and VEXT nodes to force Vec to
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// be compatible with the shuffle we intend to construct. As a result
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// ShuffleVec will be some sliding window into the original Vec.
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SDValue ShuffleVec;
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// Code should guarantee that element i in Vec starts at element "WindowBase
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// + i * WindowScale in ShuffleVec".
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int WindowBase;
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int WindowScale;
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bool operator ==(SDValue OtherVec) { return Vec == OtherVec; }
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ShuffleSourceInfo(SDValue Vec)
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: Vec(Vec), MinElt(UINT_MAX), MaxElt(0), ShuffleVec(Vec), WindowBase(0),
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WindowScale(1) {}
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};
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// First gather all vectors used as an immediate source for this BUILD_VECTOR
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// node.
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SmallVector<ShuffleSourceInfo, 2> Sources;
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for (unsigned i = 0; i < NumElts; ++i) {
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SDValue V = Op.getOperand(i);
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if (V.getOpcode() == ISD::UNDEF)
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@ -5549,127 +5577,161 @@ SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
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// A shuffle can only come from building a vector from various
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// elements of other vectors.
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return SDValue();
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} else if (V.getOperand(0).getValueType().getVectorElementType() !=
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VT.getVectorElementType()) {
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// This code doesn't know how to handle shuffles where the vector
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// element types do not match (this happens because type legalization
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// promotes the return type of EXTRACT_VECTOR_ELT).
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// FIXME: It might be appropriate to extend this code to handle
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// mismatched types.
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return SDValue();
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}
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// Record this extraction against the appropriate vector if possible...
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// Add this element source to the list if it's not already there.
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SDValue SourceVec = V.getOperand(0);
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// If the element number isn't a constant, we can't effectively
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// analyze what's going on.
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if (!isa<ConstantSDNode>(V.getOperand(1)))
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return SDValue();
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unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
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bool FoundSource = false;
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for (unsigned j = 0; j < SourceVecs.size(); ++j) {
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if (SourceVecs[j] == SourceVec) {
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if (MinElts[j] > EltNo)
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MinElts[j] = EltNo;
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if (MaxElts[j] < EltNo)
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MaxElts[j] = EltNo;
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FoundSource = true;
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break;
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}
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}
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auto Source = std::find(Sources.begin(), Sources.end(), SourceVec);
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if (Source == Sources.end())
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Source = Sources.insert(Sources.end(), ShuffleSourceInfo(SourceVec));
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// Or record a new source if not...
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if (!FoundSource) {
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SourceVecs.push_back(SourceVec);
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MinElts.push_back(EltNo);
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MaxElts.push_back(EltNo);
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}
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// Update the minimum and maximum lane number seen.
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unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
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Source->MinElt = std::min(Source->MinElt, EltNo);
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Source->MaxElt = std::max(Source->MaxElt, EltNo);
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}
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// Currently only do something sane when at most two source vectors
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// involved.
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if (SourceVecs.size() > 2)
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// are involved.
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if (Sources.size() > 2)
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return SDValue();
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SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
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int VEXTOffsets[2] = {0, 0};
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// Find out the smallest element size among result and two sources, and use
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// it as element size to build the shuffle_vector.
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EVT SmallestEltTy = VT.getVectorElementType();
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for (auto &Source : Sources) {
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EVT SrcEltTy = Source.Vec.getValueType().getVectorElementType();
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if (SrcEltTy.bitsLT(SmallestEltTy))
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SmallestEltTy = SrcEltTy;
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}
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unsigned ResMultiplier =
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VT.getVectorElementType().getSizeInBits() / SmallestEltTy.getSizeInBits();
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NumElts = VT.getSizeInBits() / SmallestEltTy.getSizeInBits();
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EVT ShuffleVT = EVT::getVectorVT(*DAG.getContext(), SmallestEltTy, NumElts);
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// This loop extracts the usage patterns of the source vectors
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// and prepares appropriate SDValues for a shuffle if possible.
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for (unsigned i = 0; i < SourceVecs.size(); ++i) {
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if (SourceVecs[i].getValueType() == VT) {
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// No VEXT necessary
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ShuffleSrcs[i] = SourceVecs[i];
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VEXTOffsets[i] = 0;
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// If the source vector is too wide or too narrow, we may nevertheless be able
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// to construct a compatible shuffle either by concatenating it with UNDEF or
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// extracting a suitable range of elements.
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for (auto &Src : Sources) {
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EVT SrcVT = Src.ShuffleVec.getValueType();
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if (SrcVT.getSizeInBits() == VT.getSizeInBits())
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continue;
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} else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) {
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// It probably isn't worth padding out a smaller vector just to
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// break it down again in a shuffle.
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// This stage of the search produces a source with the same element type as
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// the original, but with a total width matching the BUILD_VECTOR output.
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EVT EltVT = SrcVT.getVectorElementType();
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unsigned NumSrcElts = VT.getSizeInBits() / EltVT.getSizeInBits();
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EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts);
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if (SrcVT.getSizeInBits() < VT.getSizeInBits()) {
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if (2 * SrcVT.getSizeInBits() != VT.getSizeInBits())
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return SDValue();
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// We can pad out the smaller vector for free, so if it's part of a
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// shuffle...
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Src.ShuffleVec =
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DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec,
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DAG.getUNDEF(Src.ShuffleVec.getValueType()));
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continue;
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}
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// Since only 64-bit and 128-bit vectors are legal on ARM and
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// we've eliminated the other cases...
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assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts &&
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"unexpected vector sizes in ReconstructShuffle");
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if (SrcVT.getSizeInBits() != 2 * VT.getSizeInBits())
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return SDValue();
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if (MaxElts[i] - MinElts[i] >= NumElts) {
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if (Src.MaxElt - Src.MinElt >= NumSrcElts) {
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// Span too large for a VEXT to cope
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return SDValue();
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}
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if (MinElts[i] >= NumElts) {
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if (Src.MinElt >= NumSrcElts) {
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// The extraction can just take the second half
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VEXTOffsets[i] = NumElts;
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ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
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SourceVecs[i],
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DAG.getIntPtrConstant(NumElts, dl));
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} else if (MaxElts[i] < NumElts) {
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Src.ShuffleVec =
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DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
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DAG.getConstant(NumSrcElts, dl, MVT::i32));
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Src.WindowBase = -NumSrcElts;
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} else if (Src.MaxElt < NumSrcElts) {
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// The extraction can just take the first half
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VEXTOffsets[i] = 0;
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ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
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SourceVecs[i],
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DAG.getIntPtrConstant(0, dl));
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Src.ShuffleVec =
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DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
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DAG.getConstant(0, dl, MVT::i32));
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} else {
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// An actual VEXT is needed
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VEXTOffsets[i] = MinElts[i];
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SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
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SourceVecs[i],
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DAG.getIntPtrConstant(0, dl));
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SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
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SourceVecs[i],
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DAG.getIntPtrConstant(NumElts, dl));
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ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2,
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DAG.getConstant(VEXTOffsets[i], dl,
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MVT::i32));
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SDValue VEXTSrc1 =
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DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
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DAG.getConstant(0, dl, MVT::i32));
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SDValue VEXTSrc2 =
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DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
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DAG.getConstant(NumSrcElts, dl, MVT::i32));
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unsigned Imm = Src.MinElt * getExtFactor(VEXTSrc1);
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Src.ShuffleVec = DAG.getNode(ARMISD::VEXT, dl, DestVT, VEXTSrc1,
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VEXTSrc2,
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DAG.getConstant(Imm, dl, MVT::i32));
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Src.WindowBase = -Src.MinElt;
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}
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}
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SmallVector<int, 8> Mask;
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for (unsigned i = 0; i < NumElts; ++i) {
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SDValue Entry = Op.getOperand(i);
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if (Entry.getOpcode() == ISD::UNDEF) {
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Mask.push_back(-1);
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// Another possible incompatibility occurs from the vector element types. We
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// can fix this by bitcasting the source vectors to the same type we intend
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// for the shuffle.
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for (auto &Src : Sources) {
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EVT SrcEltTy = Src.ShuffleVec.getValueType().getVectorElementType();
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if (SrcEltTy == SmallestEltTy)
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continue;
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assert(ShuffleVT.getVectorElementType() == SmallestEltTy);
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Src.ShuffleVec = DAG.getNode(ISD::BITCAST, dl, ShuffleVT, Src.ShuffleVec);
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Src.WindowScale = SrcEltTy.getSizeInBits() / SmallestEltTy.getSizeInBits();
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Src.WindowBase *= Src.WindowScale;
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}
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SDValue ExtractVec = Entry.getOperand(0);
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int ExtractElt = cast<ConstantSDNode>(Op.getOperand(i)
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.getOperand(1))->getSExtValue();
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if (ExtractVec == SourceVecs[0]) {
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Mask.push_back(ExtractElt - VEXTOffsets[0]);
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} else {
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Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]);
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}
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// Final sanity check before we try to actually produce a shuffle.
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for (auto Src : Sources)
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assert(Src.ShuffleVec.getValueType() == ShuffleVT);
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// The stars all align, our next step is to produce the mask for the shuffle.
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SmallVector<int, 8> Mask(ShuffleVT.getVectorNumElements(), -1);
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int BitsPerShuffleLane = ShuffleVT.getVectorElementType().getSizeInBits();
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for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
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SDValue Entry = Op.getOperand(i);
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if (Entry.getOpcode() == ISD::UNDEF)
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continue;
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auto Src = std::find(Sources.begin(), Sources.end(), Entry.getOperand(0));
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int EltNo = cast<ConstantSDNode>(Entry.getOperand(1))->getSExtValue();
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// EXTRACT_VECTOR_ELT performs an implicit any_ext; BUILD_VECTOR an implicit
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// trunc. So only std::min(SrcBits, DestBits) actually get defined in this
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// segment.
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EVT OrigEltTy = Entry.getOperand(0).getValueType().getVectorElementType();
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int BitsDefined = std::min(OrigEltTy.getSizeInBits(),
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VT.getVectorElementType().getSizeInBits());
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int LanesDefined = BitsDefined / BitsPerShuffleLane;
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// This source is expected to fill ResMultiplier lanes of the final shuffle,
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// starting at the appropriate offset.
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int *LaneMask = &Mask[i * ResMultiplier];
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int ExtractBase = EltNo * Src->WindowScale + Src->WindowBase;
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ExtractBase += NumElts * (Src - Sources.begin());
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for (int j = 0; j < LanesDefined; ++j)
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LaneMask[j] = ExtractBase + j;
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}
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// Final check before we try to produce nonsense...
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if (isShuffleMaskLegal(Mask, VT))
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return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
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&Mask[0]);
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if (!isShuffleMaskLegal(Mask, ShuffleVT))
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return SDValue();
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// We can't handle more than two sources. This should have already
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// been checked before this point.
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assert(Sources.size() <= 2 && "Too many sources!");
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SDValue ShuffleOps[] = { DAG.getUNDEF(ShuffleVT), DAG.getUNDEF(ShuffleVT) };
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for (unsigned i = 0; i < Sources.size(); ++i)
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ShuffleOps[i] = Sources[i].ShuffleVec;
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SDValue Shuffle = DAG.getVectorShuffle(ShuffleVT, dl, ShuffleOps[0],
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ShuffleOps[1], &Mask[0]);
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return DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
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}
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/// isShuffleMaskLegal - Targets can use this to indicate that they only
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@ -335,3 +335,39 @@ entry:
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%0 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 5, i32 3, i32 7>
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ret <8 x i16> %0
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}
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; Here we get a build_vector node, where all the incoming extract_element
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; values do modify the type. However, we get different input types, as some of
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; them get truncated from i32 to i8 (from comparing cmp0 with cmp1) and some of
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; them get truncated from i16 to i8 (from comparing cmp2 with cmp3).
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define <8 x i8> @vtrn_mismatched_builvector0(<8 x i8> %tr0, <8 x i8> %tr1,
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<4 x i32> %cmp0, <4 x i32> %cmp1,
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<4 x i16> %cmp2, <4 x i16> %cmp3) {
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; CHECK-LABEL: vtrn_mismatched_builvector0
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; CHECK: vmovn.i32
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; CHECK: vtrn
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; CHECK: vbsl
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%c0 = icmp ult <4 x i32> %cmp0, %cmp1
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%c1 = icmp ult <4 x i16> %cmp2, %cmp3
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%c = shufflevector <4 x i1> %c0, <4 x i1> %c1, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
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%rv = select <8 x i1> %c, <8 x i8> %tr0, <8 x i8> %tr1
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ret <8 x i8> %rv
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}
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; Here we get a build_vector node, where half the incoming extract_element
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; values do not modify the type (the values form cmp2), but half of them do
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; (from the icmp operation).
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define <8 x i8> @vtrn_mismatched_builvector1(<8 x i8> %tr0, <8 x i8> %tr1,
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<4 x i32> %cmp0, <4 x i32> %cmp1, <4 x i8> *%cmp2_ptr) {
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; CHECK-LABEL: vtrn_mismatched_builvector1
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; We need to extend the 4 x i8 to 4 x i16 in order to perform the vtrn
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; CHECK: vmovl
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; CHECK: vtrn.8
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; CHECK: vbsl
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%cmp2_load = load <4 x i8>, <4 x i8> * %cmp2_ptr, align 4
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%cmp2 = trunc <4 x i8> %cmp2_load to <4 x i1>
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%c0 = icmp ult <4 x i32> %cmp0, %cmp1
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%c = shufflevector <4 x i1> %c0, <4 x i1> %cmp2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
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%rv = select <8 x i1> %c, <8 x i8> %tr0, <8 x i8> %tr1
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ret <8 x i8> %rv
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}
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@ -285,3 +285,76 @@ entry:
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%0 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <4 x i32> <i32 0, i32 0, i32 1, i32 3>
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ret <4 x i32> %0
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}
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define <8 x i8> @vuzp_trunc(<8 x i8> %in0, <8 x i8> %in1, <8 x i32> %cmp0, <8 x i32> %cmp1) {
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; In order to create the select we need to truncate the vcgt result from a vector of i32 to a vector of i8.
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; This results in a build_vector with mismatched types. We will generate two vmovn.i32 instructions to
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; truncate from i32 to i16 and one vuzp to perform the final truncation for i8.
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; CHECK-LABEL: vuzp_trunc
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; CHECK: vmovn.i32
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; CHECK: vmovn.i32
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; CHECK: vuzp
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; CHECK: vbsl
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%c = icmp ult <8 x i32> %cmp0, %cmp1
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%res = select <8 x i1> %c, <8 x i8> %in0, <8 x i8> %in1
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ret <8 x i8> %res
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}
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; Shuffle the result from the compare with a <4 x i8>.
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; We need to extend the loaded <4 x i8> to <4 x i16>. Otherwise we wouldn't be able
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; to perform the vuzp and get the vbsl mask.
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define <8 x i8> @vuzp_trunc_and_shuffle(<8 x i8> %tr0, <8 x i8> %tr1,
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<4 x i32> %cmp0, <4 x i32> %cmp1, <4 x i8> *%cmp2_ptr) {
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; CHECK-LABEL: vuzp_trunc_and_shuffle
|
||||
; CHECK: vmovl
|
||||
; CHECK: vuzp
|
||||
; CHECK: vbsl
|
||||
%cmp2_load = load <4 x i8>, <4 x i8> * %cmp2_ptr, align 4
|
||||
%cmp2 = trunc <4 x i8> %cmp2_load to <4 x i1>
|
||||
%c0 = icmp ult <4 x i32> %cmp0, %cmp1
|
||||
%c = shufflevector <4 x i1> %c0, <4 x i1> %cmp2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
%rv = select <8 x i1> %c, <8 x i8> %tr0, <8 x i8> %tr1
|
||||
ret <8 x i8> %rv
|
||||
}
|
||||
|
||||
; Use an undef value for the <4 x i8> that is being shuffled with the compare result.
|
||||
; This produces a build_vector with some of the operands undefs.
|
||||
define <8 x i8> @vuzp_trunc_and_shuffle_undef_right(<8 x i8> %tr0, <8 x i8> %tr1,
|
||||
<4 x i32> %cmp0, <4 x i32> %cmp1, <4 x i8> *%cmp2_ptr) {
|
||||
; CHECK-LABEL: vuzp_trunc_and_shuffle_undef_right
|
||||
; CHECK: vuzp
|
||||
; CHECK: vbsl
|
||||
%cmp2_load = load <4 x i8>, <4 x i8> * %cmp2_ptr, align 4
|
||||
%cmp2 = trunc <4 x i8> %cmp2_load to <4 x i1>
|
||||
%c0 = icmp ult <4 x i32> %cmp0, %cmp1
|
||||
%c = shufflevector <4 x i1> %c0, <4 x i1> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
%rv = select <8 x i1> %c, <8 x i8> %tr0, <8 x i8> %tr1
|
||||
ret <8 x i8> %rv
|
||||
}
|
||||
|
||||
define <8 x i8> @vuzp_trunc_and_shuffle_undef_left(<8 x i8> %tr0, <8 x i8> %tr1,
|
||||
<4 x i32> %cmp0, <4 x i32> %cmp1, <4 x i8> *%cmp2_ptr) {
|
||||
; CHECK-LABEL: vuzp_trunc_and_shuffle_undef_left
|
||||
; CHECK: vuzp
|
||||
; CHECK: vbsl
|
||||
%cmp2_load = load <4 x i8>, <4 x i8> * %cmp2_ptr, align 4
|
||||
%cmp2 = trunc <4 x i8> %cmp2_load to <4 x i1>
|
||||
%c0 = icmp ult <4 x i32> %cmp0, %cmp1
|
||||
%c = shufflevector <4 x i1> undef, <4 x i1> %c0, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
%rv = select <8 x i1> %c, <8 x i8> %tr0, <8 x i8> %tr1
|
||||
ret <8 x i8> %rv
|
||||
}
|
||||
|
||||
; We're using large data types here, and we have to fill with undef values until we
|
||||
; get some vector size that we can represent.
|
||||
define <10 x i8> @vuzp_wide_type(<10 x i8> %tr0, <10 x i8> %tr1,
|
||||
<5 x i32> %cmp0, <5 x i32> %cmp1, <5 x i8> *%cmp2_ptr) {
|
||||
; CHECK-LABEL: vuzp_wide_type
|
||||
; CHECK: vbsl
|
||||
%cmp2_load = load <5 x i8>, <5 x i8> * %cmp2_ptr, align 4
|
||||
%cmp2 = trunc <5 x i8> %cmp2_load to <5 x i1>
|
||||
%c0 = icmp ult <5 x i32> %cmp0, %cmp1
|
||||
%c = shufflevector <5 x i1> %c0, <5 x i1> %cmp2, <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
|
||||
%rv = select <10 x i1> %c, <10 x i8> %tr0, <10 x i8> %tr1
|
||||
ret <10 x i8> %rv
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user