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Delete Default and JITDefault code models

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IMHO it is an antipattern to have a enum value that is Default.

At any given piece of code it is not clear if we have to handle
Default or if has already been mapped to a concrete value. In this
case in particular, only the target can do the mapping and it is nice
to make sure it is always done.

This deletes the two default enum values of CodeModel and uses an
explicit Optional<CodeModel> when it is possible that it is
unspecified.

llvm-svn: 309911
This commit is contained in:
Rafael Espindola 2017-08-03 02:16:21 +00:00
parent 6663c348ab
commit f2011a3ae7
64 changed files with 420 additions and 468 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
include/llvm/CodeGen/CommandFlags.h
View File

@ -77,20 +77,20 @@ TMModel("thread-model",
clEnumValN(ThreadModel::Single, "single",
"Single thread model")));
cl::opt<llvm::CodeModel::Model>
CMModel("code-model",
cl::desc("Choose code model"),
cl::init(CodeModel::Default),
cl::values(clEnumValN(CodeModel::Default, "default",
"Target default code model"),
clEnumValN(CodeModel::Small, "small",
"Small code model"),
clEnumValN(CodeModel::Kernel, "kernel",
"Kernel code model"),
clEnumValN(CodeModel::Medium, "medium",
"Medium code model"),
clEnumValN(CodeModel::Large, "large",
"Large code model")));
cl::opt<llvm::CodeModel::Model> CMModel(
"code-model", cl::desc("Choose code model"),
cl::values(clEnumValN(CodeModel::Small, "small", "Small code model"),
clEnumValN(CodeModel::Kernel, "kernel", "Kernel code model"),
clEnumValN(CodeModel::Medium, "medium", "Medium code model"),
clEnumValN(CodeModel::Large, "large", "Large code model")));
static inline Optional<CodeModel::Model> getCodeModel() {
if (CMModel.getNumOccurrences()) {
CodeModel::Model M = CMModel;
return M;
}
return None;
}
cl::opt<llvm::ExceptionHandling>
ExceptionModel("exception-model",

2
include/llvm/ExecutionEngine/ExecutionEngine.h
View File

@ -535,7 +535,7 @@ private:
std::shared_ptr<JITSymbolResolver> Resolver;
TargetOptions Options;
Optional<Reloc::Model> RelocModel;
CodeModel::Model CMModel;
Optional<CodeModel::Model> CMModel;
std::string MArch;
std::string MCPU;
SmallVector<std::string, 4> MAttrs;

2
include/llvm/LTO/Config.h
View File

@ -40,7 +40,7 @@ struct Config {
TargetOptions Options;
std::vector<std::string> MAttrs;
Optional<Reloc::Model> RelocModel = Reloc::PIC_;
CodeModel::Model CodeModel = CodeModel::Default;
Optional<CodeModel::Model> CodeModel = None;
CodeGenOpt::Level CGOptLevel = CodeGenOpt::Default;
TargetMachine::CodeGenFileType CGFileType = TargetMachine::CGFT_ObjectFile;
unsigned OptLevel = 2;

2
include/llvm/Support/CodeGen.h
View File

@ -25,7 +25,7 @@ namespace llvm {
// Code model types.
namespace CodeModel {
// Sync changes with CodeGenCWrappers.h.
enum Model { Default, JITDefault, Small, Kernel, Medium, Large };
enum Model { Small, Kernel, Medium, Large };
}
namespace PICLevel {

15
include/llvm/Support/CodeGenCWrappers.h
View File

@ -22,12 +22,13 @@
namespace llvm {
inline CodeModel::Model unwrap(LLVMCodeModel Model) {
inline Optional<CodeModel::Model> unwrap(LLVMCodeModel Model, bool &JIT) {
JIT = false;
switch (Model) {
case LLVMCodeModelDefault:
return CodeModel::Default;
case LLVMCodeModelJITDefault:
return CodeModel::JITDefault;
JIT = true;
case LLVMCodeModelDefault:
return None;
case LLVMCodeModelSmall:
return CodeModel::Small;
case LLVMCodeModelKernel:
@ -37,15 +38,11 @@ inline CodeModel::Model unwrap(LLVMCodeModel Model) {
case LLVMCodeModelLarge:
return CodeModel::Large;
}
return CodeModel::Default;
return CodeModel::Small;
}
inline LLVMCodeModel wrap(CodeModel::Model Model) {
switch (Model) {
case CodeModel::Default:
return LLVMCodeModelDefault;
case CodeModel::JITDefault:
return LLVMCodeModelJITDefault;
case CodeModel::Small:
return LLVMCodeModelSmall;
case CodeModel::Kernel:

55
include/llvm/Support/TargetRegistry.h
View File

@ -101,19 +101,16 @@ public:
using MCAsmInfoCtorFnTy = MCAsmInfo *(*)(const MCRegisterInfo &MRI,
const Triple &TT);
using MCAdjustCodeGenOptsFnTy = void (*)(const Triple &TT, Reloc::Model RM,
CodeModel::Model &CM);
using MCInstrInfoCtorFnTy = MCInstrInfo *(*)();
using MCInstrAnalysisCtorFnTy = MCInstrAnalysis *(*)(const MCInstrInfo *Info);
using MCRegInfoCtorFnTy = MCRegisterInfo *(*)(const Triple &TT);
using MCSubtargetInfoCtorFnTy = MCSubtargetInfo *(*)(const Triple &TT,
StringRef CPU,
StringRef Features);
using TargetMachineCtorTy = TargetMachine *(*)(
const Target &T, const Triple &TT, StringRef CPU, StringRef Features,
const TargetOptions &Options, Optional<Reloc::Model> RM,
CodeModel::Model CM, CodeGenOpt::Level OL);
using TargetMachineCtorTy = TargetMachine
*(*)(const Target &T, const Triple &TT, StringRef CPU, StringRef Features,
const TargetOptions &Options, Optional<Reloc::Model> RM,
Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT);
// If it weren't for layering issues (this header is in llvm/Support, but
// depends on MC?) this should take the Streamer by value rather than rvalue
// reference.
@ -191,8 +188,6 @@ private:
/// registered.
MCAsmInfoCtorFnTy MCAsmInfoCtorFn;
MCAdjustCodeGenOptsFnTy MCAdjustCodeGenOptsFn;
/// MCInstrInfoCtorFn - Constructor function for this target's MCInstrInfo,
/// if registered.
MCInstrInfoCtorFnTy MCInstrInfoCtorFn;
@ -312,12 +307,6 @@ public:
return MCAsmInfoCtorFn(MRI, Triple(TheTriple));
}
void adjustCodeGenOpts(const Triple &TT, Reloc::Model RM,
CodeModel::Model &CM) const {
if (MCAdjustCodeGenOptsFn)
MCAdjustCodeGenOptsFn(TT, RM, CM);
}
/// createMCInstrInfo - Create a MCInstrInfo implementation.
///
MCInstrInfo *createMCInstrInfo() const {
@ -365,15 +354,17 @@ public:
/// feature set; it should always be provided. Generally this should be
/// either the target triple from the module, or the target triple of the
/// host if that does not exist.
TargetMachine *
createTargetMachine(StringRef TT, StringRef CPU, StringRef Features,
const TargetOptions &Options, Optional<Reloc::Model> RM,
CodeModel::Model CM = CodeModel::Default,
CodeGenOpt::Level OL = CodeGenOpt::Default) const {
TargetMachine *createTargetMachine(StringRef TT, StringRef CPU,
StringRef Features,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
Optional<CodeModel::Model> CM = None,
CodeGenOpt::Level OL = CodeGenOpt::Default,
bool JIT = false) const {
if (!TargetMachineCtorFn)
return nullptr;
return TargetMachineCtorFn(*this, Triple(TT), CPU, Features, Options, RM,
CM, OL);
CM, OL, JIT);
}
/// createMCAsmBackend - Create a target specific assembly parser.
@ -663,11 +654,6 @@ struct TargetRegistry {
T.MCAsmInfoCtorFn = Fn;
}
static void registerMCAdjustCodeGenOpts(Target &T,
Target::MCAdjustCodeGenOptsFnTy Fn) {
T.MCAdjustCodeGenOptsFn = Fn;
}
/// RegisterMCInstrInfo - Register a MCInstrInfo implementation for the
/// given target.
///
@ -929,12 +915,6 @@ struct RegisterMCAsmInfoFn {
}
};
struct RegisterMCAdjustCodeGenOptsFn {
RegisterMCAdjustCodeGenOptsFn(Target &T, Target::MCAdjustCodeGenOptsFnTy Fn) {
TargetRegistry::registerMCAdjustCodeGenOpts(T, Fn);
}
};
/// RegisterMCInstrInfo - Helper template for registering a target instruction
/// info implementation. This invokes the static "Create" method on the class
/// to actually do the construction. Usage:
@ -1080,12 +1060,11 @@ template <class TargetMachineImpl> struct RegisterTargetMachine {
}
private:
static TargetMachine *Allocator(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
CodeModel::Model CM, CodeGenOpt::Level OL) {
return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL);
static TargetMachine *
Allocator(const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
const TargetOptions &Options, Optional<Reloc::Model> RM,
Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
}
};

2
include/llvm/Target/TargetMachine.h
View File

@ -78,7 +78,7 @@ protected: // Can only create subclasses.
std::string TargetFS;
Reloc::Model RM = Reloc::Static;
CodeModel::Model CMModel = CodeModel::Default;
CodeModel::Model CMModel = CodeModel::Small;
CodeGenOpt::Level OptLevel = CodeGenOpt::Default;
/// Contains target specific asm information.

1
lib/CodeGen/LLVMTargetMachine.cpp
View File

@ -77,7 +77,6 @@ LLVMTargetMachine::LLVMTargetMachine(const Target &T,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL)
: TargetMachine(T, DataLayoutString, TT, CPU, FS, Options) {
T.adjustCodeGenOpts(TT, RM, CM);
this->RM = RM;
this->CMModel = CM;
this->OptLevel = OL;

2
lib/ExecutionEngine/ExecutionEngine.cpp
View File

@ -476,7 +476,7 @@ EngineBuilder::EngineBuilder() : EngineBuilder(nullptr) {}
EngineBuilder::EngineBuilder(std::unique_ptr<Module> M)
: M(std::move(M)), WhichEngine(EngineKind::Either), ErrorStr(nullptr),
OptLevel(CodeGenOpt::Default), MemMgr(nullptr), Resolver(nullptr),
CMModel(CodeModel::JITDefault), UseOrcMCJITReplacement(false) {
UseOrcMCJITReplacement(false) {
// IR module verification is enabled by default in debug builds, and disabled
// by default in release builds.
#ifndef NDEBUG

4
lib/ExecutionEngine/ExecutionEngineBindings.cpp
View File

@ -198,8 +198,10 @@ LLVMBool LLVMCreateMCJITCompilerForModule(
builder.setEngineKind(EngineKind::JIT)
.setErrorStr(&Error)
.setOptLevel((CodeGenOpt::Level)options.OptLevel)
.setCodeModel(unwrap(options.CodeModel))
.setTargetOptions(targetOptions);
bool JIT;
if (Optional<CodeModel::Model> CM = unwrap(options.CodeModel, JIT))
builder.setCodeModel(*CM);
if (options.MCJMM)
builder.setMCJITMemoryManager(
std::unique_ptr<RTDyldMemoryManager>(unwrap(options.MCJMM)));

9
lib/ExecutionEngine/TargetSelect.cpp
View File

@ -92,11 +92,10 @@ TargetMachine *EngineBuilder::selectTarget(const Triple &TargetTriple,
}
// Allocate a target...
TargetMachine *Target = TheTarget->createTargetMachine(TheTriple.getTriple(),
MCPU, FeaturesStr,
Options,
RelocModel, CMModel,
OptLevel);
TargetMachine *Target =
TheTarget->createTargetMachine(TheTriple.getTriple(), MCPU, FeaturesStr,
Options, RelocModel, CMModel, OptLevel,
/*JIT*/ true);
assert(Target && "Could not allocate target machine!");
return Target;
}

5
lib/LTO/LTO.cpp
View File

@ -118,7 +118,10 @@ static void computeCacheKey(
AddUnsigned(*Conf.RelocModel);
else
AddUnsigned(-1);
AddUnsigned(Conf.CodeModel);
if (Conf.CodeModel)
AddUnsigned(*Conf.CodeModel);
else
AddUnsigned(-1);
AddUnsigned(Conf.CGOptLevel);
AddUnsigned(Conf.CGFileType);
AddUnsigned(Conf.OptLevel);

5
lib/LTO/LTOCodeGenerator.cpp
View File

@ -368,9 +368,8 @@ bool LTOCodeGenerator::determineTarget() {
}
std::unique_ptr<TargetMachine> LTOCodeGenerator::createTargetMachine() {
return std::unique_ptr<TargetMachine>(
MArch->createTargetMachine(TripleStr, MCpu, FeatureStr, Options,
RelocModel, CodeModel::Default, CGOptLevel));
return std::unique_ptr<TargetMachine>(MArch->createTargetMachine(
TripleStr, MCpu, FeatureStr, Options, RelocModel, None, CGOptLevel));
}
// If a linkonce global is present in the MustPreserveSymbols, we need to make

6
lib/LTO/ThinLTOCodeGenerator.cpp
View File

@ -583,9 +583,9 @@ std::unique_ptr<TargetMachine> TargetMachineBuilder::create() const {
Features.getDefaultSubtargetFeatures(TheTriple);
std::string FeatureStr = Features.getString();
return std::unique_ptr<TargetMachine>(TheTarget->createTargetMachine(
TheTriple.str(), MCpu, FeatureStr, Options, RelocModel,
CodeModel::Default, CGOptLevel));
return std::unique_ptr<TargetMachine>(
TheTarget->createTargetMachine(TheTriple.str(), MCpu, FeatureStr, Options,
RelocModel, None, CGOptLevel));
}
/**

52
lib/Target/AArch64/AArch64TargetMachine.cpp
View File

@ -206,18 +206,42 @@ static Reloc::Model getEffectiveRelocModel(const Triple &TT,
return *RM;
}
static CodeModel::Model getEffectiveCodeModel(const Triple &TT,
Optional<CodeModel::Model> CM,
bool JIT) {
if (CM) {
if (*CM != CodeModel::Small && *CM != CodeModel::Large) {
if (!TT.isOSFuchsia())
report_fatal_error(
"Only small and large code models are allowed on AArch64");
else if (CM != CodeModel::Kernel)
report_fatal_error(
"Only small, kernel, and large code models are allowed on AArch64");
}
return *CM;
}
// The default MCJIT memory managers make no guarantees about where they can
// find an executable page; JITed code needs to be able to refer to globals
// no matter how far away they are.
if (JIT)
return CodeModel::Large;
return CodeModel::Small;
}
/// Create an AArch64 architecture model.
///
AArch64TargetMachine::AArch64TargetMachine(
const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
const TargetOptions &Options, Optional<Reloc::Model> RM,
CodeModel::Model CM, CodeGenOpt::Level OL, bool LittleEndian)
: LLVMTargetMachine(T, computeDataLayout(TT, Options.MCOptions,
LittleEndian),
TT, CPU, FS, Options,
getEffectiveRelocModel(TT, RM), CM, OL),
TLOF(createTLOF(getTargetTriple())),
isLittle(LittleEndian) {
AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT,
bool LittleEndian)
: LLVMTargetMachine(T,
computeDataLayout(TT, Options.MCOptions, LittleEndian),
TT, CPU, FS, Options, getEffectiveRelocModel(TT, RM),
getEffectiveCodeModel(TT, CM, JIT), OL),
TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) {
initAsmInfo();
}
@ -252,16 +276,16 @@ void AArch64leTargetMachine::anchor() { }
AArch64leTargetMachine::AArch64leTargetMachine(
const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
const TargetOptions &Options, Optional<Reloc::Model> RM,
CodeModel::Model CM, CodeGenOpt::Level OL)
: AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
: AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
void AArch64beTargetMachine::anchor() { }
AArch64beTargetMachine::AArch64beTargetMachine(
const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
const TargetOptions &Options, Optional<Reloc::Model> RM,
CodeModel::Model CM, CodeGenOpt::Level OL)
: AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
: AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
namespace {

14
lib/Target/AArch64/AArch64TargetMachine.h
View File

@ -31,8 +31,8 @@ protected:
public:
AArch64TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM, CodeModel::Model CM,
CodeGenOpt::Level OL, bool IsLittleEndian);
Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT, bool IsLittleEndian);
~AArch64TargetMachine() override;
const AArch64Subtarget *getSubtargetImpl(const Function &F) const override;
@ -62,8 +62,9 @@ class AArch64leTargetMachine : public AArch64TargetMachine {
public:
AArch64leTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
Optional<Reloc::Model> RM,
Optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
bool JIT);
};
// AArch64 big endian target machine.
@ -73,8 +74,9 @@ class AArch64beTargetMachine : public AArch64TargetMachine {
public:
AArch64beTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
Optional<Reloc::Model> RM,
Optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
bool JIT);
};
} // end namespace llvm

25
lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
View File

@ -84,28 +84,6 @@ static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI,
return MAI;
}
static void adjustCodeGenOpts(const Triple &TT, Reloc::Model RM,
CodeModel::Model &CM) {
assert((TT.isOSBinFormatELF() || TT.isOSBinFormatMachO() ||
TT.isOSBinFormatCOFF()) && "Invalid target");
if (CM == CodeModel::Default)
CM = CodeModel::Small;
// The default MCJIT memory managers make no guarantees about where they can
// find an executable page; JITed code needs to be able to refer to globals
// no matter how far away they are.
else if (CM == CodeModel::JITDefault)
CM = CodeModel::Large;
else if (CM != CodeModel::Small && CM != CodeModel::Large) {
if (!TT.isOSFuchsia())
report_fatal_error(
"Only small and large code models are allowed on AArch64");
else if (CM != CodeModel::Kernel)
report_fatal_error(
"Only small, kernel, and large code models are allowed on AArch64");
}
}
static MCInstPrinter *createAArch64MCInstPrinter(const Triple &T,
unsigned SyntaxVariant,
const MCAsmInfo &MAI,
@ -153,9 +131,6 @@ extern "C" void LLVMInitializeAArch64TargetMC() {
// Register the MC asm info.
RegisterMCAsmInfoFn X(*T, createAArch64MCAsmInfo);
// Register the MC codegen info.
TargetRegistry::registerMCAdjustCodeGenOpts(*T, adjustCodeGenOpts);
// Register the MC instruction info.
TargetRegistry::RegisterMCInstrInfo(*T, createAArch64MCInstrInfo);

25
lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
View File

@ -266,15 +266,22 @@ static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
return Reloc::PIC_;
}
static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
if (CM)
return *CM;
return CodeModel::Small;
}
AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
TargetOptions Options,
Optional<Reloc::Model> RM,
CodeModel::Model CM,
Optional<CodeModel::Model> CM,
CodeGenOpt::Level OptLevel)
: LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
FS, Options, getEffectiveRelocModel(RM), CM, OptLevel),
TLOF(createTLOF(getTargetTriple())) {
: LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
FS, Options, getEffectiveRelocModel(RM),
getEffectiveCodeModel(CM), OptLevel),
TLOF(createTLOF(getTargetTriple())) {
AS = AMDGPU::getAMDGPUAS(TT);
initAsmInfo();
}
@ -378,8 +385,9 @@ R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
TargetOptions Options,
Optional<Reloc::Model> RM,
CodeModel::Model CM, CodeGenOpt::Level OL)
: AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
setRequiresStructuredCFG(true);
}
@ -411,8 +419,9 @@ GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
TargetOptions Options,
Optional<Reloc::Model> RM,
CodeModel::Model CM, CodeGenOpt::Level OL)
: AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
const SISubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
StringRef GPU = getGPUName(F);

10
lib/Target/AMDGPU/AMDGPUTargetMachine.h
View File

@ -43,7 +43,7 @@ protected:
public:
AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, TargetOptions Options,
Optional<Reloc::Model> RM, CodeModel::Model CM,
Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL);
~AMDGPUTargetMachine() override;
@ -85,8 +85,8 @@ private:
public:
R600TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, TargetOptions Options,
Optional<Reloc::Model> RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT);
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
@ -108,8 +108,8 @@ private:
public:
GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, TargetOptions Options,
Optional<Reloc::Model> RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT);
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;

2
lib/Target/ARM/ARMFrameLowering.cpp
View File

@ -512,7 +512,6 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF,
switch (TM.getCodeModel()) {
case CodeModel::Small:
case CodeModel::Medium:
case CodeModel::Default:
case CodeModel::Kernel:
BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL))
.add(predOps(ARMCC::AL))
@ -521,7 +520,6 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF,
.setMIFlags(MachineInstr::FrameSetup);
break;
case CodeModel::Large:
case CodeModel::JITDefault:
BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12)
.addExternalSymbol("__chkstk")
.setMIFlags(MachineInstr::FrameSetup);

4
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -8783,7 +8783,6 @@ ARMTargetLowering::EmitLowered__chkstk(MachineInstr &MI,
switch (TM.getCodeModel()) {
case CodeModel::Small:
case CodeModel::Medium:
case CodeModel::Default:
case CodeModel::Kernel:
BuildMI(*MBB, MI, DL, TII.get(ARM::tBL))
.add(predOps(ARMCC::AL))
@ -8793,8 +8792,7 @@ ARMTargetLowering::EmitLowered__chkstk(MachineInstr &MI,
.addReg(ARM::R12,
RegState::Implicit | RegState::Define | RegState::Dead);
break;
case CodeModel::Large:
case CodeModel::JITDefault: {
case CodeModel::Large: {
MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
unsigned Reg = MRI.createVirtualRegister(&ARM::rGPRRegClass);

21
lib/Target/ARM/ARMTargetMachine.cpp
View File

@ -190,17 +190,23 @@ static Reloc::Model getEffectiveRelocModel(const Triple &TT,
return *RM;
}
static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
if (CM)
return *CM;
return CodeModel::Small;
}
/// Create an ARM architecture model.
///
ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
CodeModel::Model CM,
Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool isLittle)
: LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
CPU, FS, Options, getEffectiveRelocModel(TT, RM), CM,
OL),
CPU, FS, Options, getEffectiveRelocModel(TT, RM),
getEffectiveCodeModel(CM), OL),
TargetABI(computeTargetABI(TT, CPU, Options)),
TLOF(createTLOF(getTargetTriple())), isLittle(isLittle) {
@ -276,21 +282,20 @@ TargetIRAnalysis ARMBaseTargetMachine::getTargetIRAnalysis() {
});
}
ARMLETargetMachine::ARMLETargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
CodeModel::Model CM,
CodeGenOpt::Level OL)
Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
ARMBETargetMachine::ARMBETargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
CodeModel::Model CM,
CodeGenOpt::Level OL)
Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
namespace {

10
lib/Target/ARM/ARMTargetMachine.h
View File

@ -42,7 +42,7 @@ protected:
public:
ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM, CodeModel::Model CM,
Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool isLittle);
~ARMBaseTargetMachine() override;
@ -74,8 +74,8 @@ class ARMLETargetMachine : public ARMBaseTargetMachine {
public:
ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT);
};
/// ARM/Thumb big endian target machine.
@ -84,8 +84,8 @@ class ARMBETargetMachine : public ARMBaseTargetMachine {
public:
ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT);
};
} // end namespace llvm

12
lib/Target/BPF/BPFTargetMachine.cpp
View File

@ -43,13 +43,21 @@ static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
return *RM;
}
static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
if (CM)
return *CM;
return CodeModel::Small;
}
BPFTargetMachine::BPFTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
CodeModel::Model CM, CodeGenOpt::Level OL)
Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
getEffectiveRelocModel(RM), CM, OL),
getEffectiveRelocModel(RM), getEffectiveCodeModel(CM),
OL),
TLOF(make_unique<TargetLoweringObjectFileELF>()),
Subtarget(TT, CPU, FS, *this) {
initAsmInfo();

4
lib/Target/BPF/BPFTargetMachine.h
View File

@ -25,8 +25,8 @@ class BPFTargetMachine : public LLVMTargetMachine {
public:
BPFTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT);
const BPFSubtarget *getSubtargetImpl() const { return &Subtarget; }
const BPFSubtarget *getSubtargetImpl(const Function &) const override {

21
lib/Target/Hexagon/HexagonTargetMachine.cpp
View File

@ -152,6 +152,12 @@ static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
return *RM;
}
static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
if (CM)
return *CM;
return CodeModel::Small;
}
extern "C" void LLVMInitializeHexagonTarget() {
// Register the target.
RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
@ -168,17 +174,18 @@ HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
CodeModel::Model CM,
CodeGenOpt::Level OL)
Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
// Specify the vector alignment explicitly. For v512x1, the calculated
// alignment would be 512*alignment(i1), which is 512 bytes, instead of
// the required minimum of 64 bytes.
: LLVMTargetMachine(
T, "e-m:e-p:32:32:32-a:0-n16:32-"
"i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
"v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
TT, CPU, FS, Options, getEffectiveRelocModel(RM), CM,
(HexagonNoOpt ? CodeGenOpt::None : OL)),
T,
"e-m:e-p:32:32:32-a:0-n16:32-"
"i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
"v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
TT, CPU, FS, Options, getEffectiveRelocModel(RM),
getEffectiveCodeModel(CM), (HexagonNoOpt ? CodeGenOpt::None : OL)),
TLOF(make_unique<HexagonTargetObjectFile>()) {
initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
initAsmInfo();

4
lib/Target/Hexagon/HexagonTargetMachine.h
View File

@ -30,8 +30,8 @@ class HexagonTargetMachine : public LLVMTargetMachine {
public:
HexagonTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT);
~HexagonTargetMachine() override;
const HexagonSubtarget *getSubtargetImpl(const Function &F) const override;

16
lib/Target/Lanai/LanaiTargetMachine.cpp
View File

@ -53,15 +53,23 @@ static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
return *RM;
}
static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
if (CM)
return *CM;
return CodeModel::Medium;
}
LanaiTargetMachine::LanaiTargetMachine(const Target &T, const Triple &TT,
StringRef Cpu, StringRef FeatureString,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
CodeModel::Model CodeModel,
CodeGenOpt::Level OptLevel)
Optional<CodeModel::Model> CodeModel,
CodeGenOpt::Level OptLevel, bool JIT)
: LLVMTargetMachine(T, computeDataLayout(), TT, Cpu, FeatureString, Options,
getEffectiveRelocModel(RM), CodeModel, OptLevel),
Subtarget(TT, Cpu, FeatureString, *this, Options, CodeModel, OptLevel),
getEffectiveRelocModel(RM),
getEffectiveCodeModel(CodeModel), OptLevel),
Subtarget(TT, Cpu, FeatureString, *this, Options, getCodeModel(),
OptLevel),
TLOF(new LanaiTargetObjectFile()) {
initAsmInfo();
}

3
lib/Target/Lanai/LanaiTargetMachine.h
View File

@ -34,7 +34,8 @@ public:
StringRef Cpu, StringRef FeatureString,
const TargetOptions &Options,
Optional<Reloc::Model> RelocationModel,
CodeModel::Model CodeModel, CodeGenOpt::Level OptLevel);
Optional<CodeModel::Model> CodeModel,
CodeGenOpt::Level OptLevel, bool JIT);
const LanaiSubtarget *
getSubtargetImpl(const llvm::Function & /*Fn*/) const override {

13
lib/Target/MSP430/MSP430TargetMachine.cpp
View File

@ -32,6 +32,12 @@ static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
return *RM;
}
static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
if (CM)
return *CM;
return CodeModel::Small;
}
static std::string computeDataLayout(const Triple &TT, StringRef CPU,
const TargetOptions &Options) {
return "e-m:e-p:16:16-i32:16-i64:16-f32:16-f64:16-a:8-n8:16-S16";
@ -41,10 +47,11 @@ MSP430TargetMachine::MSP430TargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
CodeModel::Model CM,
CodeGenOpt::Level OL)
Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options), TT, CPU, FS,
Options, getEffectiveRelocModel(RM), CM, OL),
Options, getEffectiveRelocModel(RM),
getEffectiveCodeModel(CM), OL),
TLOF(make_unique<TargetLoweringObjectFileELF>()),
Subtarget(TT, CPU, FS, *this) {
initAsmInfo();

4
lib/Target/MSP430/MSP430TargetMachine.h
View File

@ -30,8 +30,8 @@ class MSP430TargetMachine : public LLVMTargetMachine {
public:
MSP430TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT);
~MSP430TargetMachine() override;
const MSP430Subtarget *getSubtargetImpl(const Function &F) const override {

29
lib/Target/Mips/MipsTargetMachine.cpp
View File

@ -84,13 +84,19 @@ static std::string computeDataLayout(const Triple &TT, StringRef CPU,
return Ret;
}
static Reloc::Model getEffectiveRelocModel(CodeModel::Model CM,
static Reloc::Model getEffectiveRelocModel(bool JIT,
Optional<Reloc::Model> RM) {
if (!RM.hasValue() || CM == CodeModel::JITDefault)
if (!RM.hasValue() || JIT)
return Reloc::Static;
return *RM;
}
static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
if (CM)
return *CM;
return CodeModel::Small;
}
// On function prologue, the stack is created by decrementing
// its pointer. Once decremented, all references are done with positive
// offset from the stack/frame pointer, using StackGrowsUp enables
@ -100,11 +106,12 @@ MipsTargetMachine::MipsTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
CodeModel::Model CM, CodeGenOpt::Level OL,
Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT,
bool isLittle)
: LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
CPU, FS, Options, getEffectiveRelocModel(CM, RM), CM,
OL),
CPU, FS, Options, getEffectiveRelocModel(JIT, RM),
getEffectiveCodeModel(CM), OL),
isLittle(isLittle), TLOF(llvm::make_unique<MipsTargetObjectFile>()),
ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)),
Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this),
@ -124,9 +131,9 @@ MipsebTargetMachine::MipsebTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
CodeModel::Model CM,
CodeGenOpt::Level OL)
: MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
void MipselTargetMachine::anchor() {}
@ -134,9 +141,9 @@ MipselTargetMachine::MipselTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
CodeModel::Model CM,
CodeGenOpt::Level OL)
: MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
const MipsSubtarget *
MipsTargetMachine::getSubtargetImpl(const Function &F) const {

12
lib/Target/Mips/MipsTargetMachine.h
View File

@ -40,8 +40,8 @@ class MipsTargetMachine : public LLVMTargetMachine {
public:
MipsTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM, CodeModel::Model CM,
CodeGenOpt::Level OL, bool isLittle);
Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT, bool isLittle);
~MipsTargetMachine() override;
TargetIRAnalysis getTargetIRAnalysis() override;
@ -80,8 +80,8 @@ class MipsebTargetMachine : public MipsTargetMachine {
public:
MipsebTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT);
};
/// Mips32/64 little endian target machine.
@ -92,8 +92,8 @@ class MipselTargetMachine : public MipsTargetMachine {
public:
MipselTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT);
};
} // end namespace llvm

21
lib/Target/NVPTX/NVPTXTargetMachine.cpp
View File

@ -86,18 +86,23 @@ static std::string computeDataLayout(bool is64Bit) {
return Ret;
}
static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
if (CM)
return *CM;
return CodeModel::Small;
}
NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
CodeModel::Model CM,
Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool is64bit)
// The pic relocation model is used regardless of what the client has
// specified, as it is the only relocation model currently supported.
: LLVMTargetMachine(T, computeDataLayout(is64bit), TT, CPU, FS, Options,
Reloc::PIC_, CM, OL),
is64bit(is64bit),
TLOF(llvm::make_unique<NVPTXTargetObjectFile>()),
Reloc::PIC_, getEffectiveCodeModel(CM), OL),
is64bit(is64bit), TLOF(llvm::make_unique<NVPTXTargetObjectFile>()),
Subtarget(TT, CPU, FS, *this) {
if (TT.getOS() == Triple::NVCL)
drvInterface = NVPTX::NVCL;
@ -114,8 +119,8 @@ NVPTXTargetMachine32::NVPTXTargetMachine32(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
CodeModel::Model CM,
CodeGenOpt::Level OL)
Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
void NVPTXTargetMachine64::anchor() {}
@ -124,8 +129,8 @@ NVPTXTargetMachine64::NVPTXTargetMachine64(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
CodeModel::Model CM,
CodeGenOpt::Level OL)
Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
namespace {

10
lib/Target/NVPTX/NVPTXTargetMachine.h
View File

@ -36,7 +36,7 @@ class NVPTXTargetMachine : public LLVMTargetMachine {
public:
NVPTXTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM, CodeModel::Model CM,
Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
CodeGenOpt::Level OP, bool is64bit);
~NVPTXTargetMachine() override;
@ -75,8 +75,8 @@ class NVPTXTargetMachine32 : public NVPTXTargetMachine {
public:
NVPTXTargetMachine32(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT);
};
class NVPTXTargetMachine64 : public NVPTXTargetMachine {
@ -84,8 +84,8 @@ class NVPTXTargetMachine64 : public NVPTXTargetMachine {
public:
NVPTXTargetMachine64(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT);
};
} // end namespace llvm

12
lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
View File

@ -94,15 +94,6 @@ static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MRI,
return MAI;
}
static void adjustCodeGenOpts(const Triple &TT, Reloc::Model RM,
CodeModel::Model &CM) {
if (CM == CodeModel::Default) {
if (!TT.isOSDarwin() &&
(TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le))
CM = CodeModel::Medium;
}
}
namespace {
class PPCTargetAsmStreamer : public PPCTargetStreamer {
@ -257,9 +248,6 @@ extern "C" void LLVMInitializePowerPCTargetMC() {
// Register the MC asm info.
RegisterMCAsmInfoFn C(*T, createPPCMCAsmInfo);
// Register the MC codegen info.
TargetRegistry::registerMCAdjustCodeGenOpts(*T, adjustCodeGenOpts);
// Register the MC instruction info.
TargetRegistry::RegisterMCInstrInfo(*T, createPPCMCInstrInfo);

4
lib/Target/PowerPC/PPCFastISel.cpp
View File

@ -1930,7 +1930,7 @@ unsigned PPCFastISel::PPCMaterializeFP(const ConstantFP *CFP, MVT VT) {
PPCFuncInfo->setUsesTOCBasePtr();
// For small code model, generate a LF[SD](0, LDtocCPT(Idx, X2)).
if (CModel == CodeModel::Small || CModel == CodeModel::JITDefault) {
if (CModel == CodeModel::Small) {
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocCPT),
TmpReg)
.addConstantPoolIndex(Idx).addReg(PPC::X2);
@ -1981,7 +1981,7 @@ unsigned PPCFastISel::PPCMaterializeGV(const GlobalValue *GV, MVT VT) {
PPCFuncInfo->setUsesTOCBasePtr();
// For small code model, generate a simple TOC load.
if (CModel == CodeModel::Small || CModel == CodeModel::JITDefault)
if (CModel == CodeModel::Small)
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtoc),
DestReg)
.addGlobalAddress(GV)

2
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -2476,7 +2476,6 @@ SDValue PPCTargetLowering::getPICJumpTableRelocBase(SDValue Table,
return TargetLowering::getPICJumpTableRelocBase(Table, DAG);
switch (getTargetMachine().getCodeModel()) {
case CodeModel::Default:
case CodeModel::Small:
case CodeModel::Medium:
return TargetLowering::getPICJumpTableRelocBase(Table, DAG);
@ -2494,7 +2493,6 @@ PPCTargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
switch (getTargetMachine().getCodeModel()) {
case CodeModel::Default:
case CodeModel::Small:
case CodeModel::Medium:
return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);

16
lib/Target/PowerPC/PPCTargetMachine.cpp
View File

@ -208,6 +208,16 @@ static Reloc::Model getEffectiveRelocModel(const Triple &TT,
return Reloc::Static;
}
static CodeModel::Model getEffectiveCodeModel(const Triple &TT,
Optional<CodeModel::Model> CM) {
if (CM)
return *CM;
if (!TT.isOSDarwin() &&
(TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le))
return CodeModel::Medium;
return CodeModel::Small;
}
// The FeatureString here is a little subtle. We are modifying the feature
// string with what are (currently) non-function specific overrides as it goes
// into the LLVMTargetMachine constructor and then using the stored value in the
@ -216,10 +226,12 @@ PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
CodeModel::Model CM, CodeGenOpt::Level OL)
Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU,
computeFSAdditions(FS, OL, TT), Options,
getEffectiveRelocModel(TT, RM), CM, OL),
getEffectiveRelocModel(TT, RM),
getEffectiveCodeModel(TT, CM), OL),
TLOF(createTLOF(getTargetTriple())),
TargetABI(computeTargetABI(TT, Options)) {
initAsmInfo();

4
lib/Target/PowerPC/PPCTargetMachine.h
View File

@ -35,8 +35,8 @@ private:
public:
PPCTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT);
~PPCTargetMachine() override;

13
lib/Target/RISCV/RISCVTargetMachine.cpp
View File

@ -43,14 +43,21 @@ static Reloc::Model getEffectiveRelocModel(const Triple &TT,
return *RM;
}
static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
if (CM)
return *CM;
return CodeModel::Small;
}
RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
CodeModel::Model CM,
CodeGenOpt::Level OL)
Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
getEffectiveRelocModel(TT, RM), CM, OL),
getEffectiveRelocModel(TT, RM),
getEffectiveCodeModel(CM), OL),
TLOF(make_unique<TargetLoweringObjectFileELF>()) {
initAsmInfo();
}

4
lib/Target/RISCV/RISCVTargetMachine.h
View File

@ -26,8 +26,8 @@ class RISCVTargetMachine : public LLVMTargetMachine {
public:
RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT);
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;

45
lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
View File

@ -69,43 +69,6 @@ createSparcMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
return createSparcMCSubtargetInfoImpl(TT, CPU, FS);
}
// Code models. Some only make sense for 64-bit code.
//
// SunCC Reloc CodeModel Constraints
// abs32 Static Small text+data+bss linked below 2^32 bytes
// abs44 Static Medium text+data+bss linked below 2^44 bytes
// abs64 Static Large text smaller than 2^31 bytes
// pic13 PIC_ Small GOT < 2^13 bytes
// pic32 PIC_ Medium GOT < 2^32 bytes
//
// All code models require that the text segment is smaller than 2GB.
static void adjustCodeGenOpts(const Triple &TT, Reloc::Model RM,
CodeModel::Model &CM) {
// The default 32-bit code model is abs32/pic32 and the default 32-bit
// code model for JIT is abs32.
switch (CM) {
default: break;
case CodeModel::Default:
case CodeModel::JITDefault: CM = CodeModel::Small; break;
}
}
static void adjustCodeGenOptsV9(const Triple &TT, Reloc::Model RM,
CodeModel::Model &CM) {
// The default 64-bit code model is abs44/pic32 and the default 64-bit
// code model for JIT is abs64.
switch (CM) {
default: break;
case CodeModel::Default:
CM = RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium;
break;
case CodeModel::JITDefault:
CM = CodeModel::Large;
break;
}
}
static MCTargetStreamer *
createObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
return new SparcTargetELFStreamer(S);
@ -159,12 +122,4 @@ extern "C" void LLVMInitializeSparcTargetMC() {
// Register the MCInstPrinter
TargetRegistry::RegisterMCInstPrinter(*T, createSparcMCInstPrinter);
}
// Register the MC codegen info.
TargetRegistry::registerMCAdjustCodeGenOpts(getTheSparcTarget(),
adjustCodeGenOpts);
TargetRegistry::registerMCAdjustCodeGenOpts(getTheSparcV9Target(),
adjustCodeGenOptsV9);
TargetRegistry::registerMCAdjustCodeGenOpts(getTheSparcelTarget(),
adjustCodeGenOpts);
}

58
lib/Target/Sparc/SparcTargetMachine.cpp
View File

@ -60,15 +60,39 @@ static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
return *RM;
}
// Code models. Some only make sense for 64-bit code.
//
// SunCC Reloc CodeModel Constraints
// abs32 Static Small text+data+bss linked below 2^32 bytes
// abs44 Static Medium text+data+bss linked below 2^44 bytes
// abs64 Static Large text smaller than 2^31 bytes
// pic13 PIC_ Small GOT < 2^13 bytes
// pic32 PIC_ Medium GOT < 2^32 bytes
//
// All code models require that the text segment is smaller than 2GB.
static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM,
Reloc::Model RM, bool Is64Bit,
bool JIT) {
if (CM)
return *CM;
if (Is64Bit) {
if (JIT)
return CodeModel::Large;
return RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium;
}
return CodeModel::Small;
}
/// Create an ILP32 architecture model
SparcTargetMachine::SparcTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
CodeModel::Model CM,
CodeGenOpt::Level OL, bool is64bit)
: LLVMTargetMachine(T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options,
getEffectiveRelocModel(RM), CM, OL),
SparcTargetMachine::SparcTargetMachine(
const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
const TargetOptions &Options, Optional<Reloc::Model> RM,
Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT, bool is64bit)
: LLVMTargetMachine(
T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options,
getEffectiveRelocModel(RM),
getEffectiveCodeModel(CM, getEffectiveRelocModel(RM), is64bit, JIT),
OL),
TLOF(make_unique<SparcELFTargetObjectFile>()),
Subtarget(TT, CPU, FS, *this, is64bit), is64Bit(is64bit) {
initAsmInfo();
@ -164,9 +188,9 @@ SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
CodeModel::Model CM,
CodeGenOpt::Level OL)
: SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
void SparcV9TargetMachine::anchor() { }
@ -174,9 +198,9 @@ SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
CodeModel::Model CM,
CodeGenOpt::Level OL)
: SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
void SparcelTargetMachine::anchor() {}
@ -184,6 +208,6 @@ SparcelTargetMachine::SparcelTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
CodeModel::Model CM,
CodeGenOpt::Level OL)
: SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}

16
lib/Target/Sparc/SparcTargetMachine.h
View File

@ -28,8 +28,8 @@ class SparcTargetMachine : public LLVMTargetMachine {
public:
SparcTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM, CodeModel::Model CM,
CodeGenOpt::Level OL, bool is64bit);
Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT, bool is64bit);
~SparcTargetMachine() override;
const SparcSubtarget *getSubtargetImpl() const { return &Subtarget; }
@ -53,8 +53,8 @@ class SparcV8TargetMachine : public SparcTargetMachine {
public:
SparcV8TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT);
};
/// Sparc 64-bit target machine
@ -64,8 +64,8 @@ class SparcV9TargetMachine : public SparcTargetMachine {
public:
SparcV9TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT);
};
class SparcelTargetMachine : public SparcTargetMachine {
@ -74,8 +74,8 @@ class SparcelTargetMachine : public SparcTargetMachine {
public:
SparcelTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT);
};
} // end namespace llvm

41
lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
View File

@ -173,43 +173,6 @@ createSystemZMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
return createSystemZMCSubtargetInfoImpl(TT, CPU, FS);
}
static void adjustCodeGenOpts(const Triple &TT, Reloc::Model RM,
CodeModel::Model &CM) {
// For SystemZ we define the models as follows:
//
// Small: BRASL can call any function and will use a stub if necessary.
// Locally-binding symbols will always be in range of LARL.
//
// Medium: BRASL can call any function and will use a stub if necessary.
// GOT slots and locally-defined text will always be in range
// of LARL, but other symbols might not be.
//
// Large: Equivalent to Medium for now.
//
// Kernel: Equivalent to Medium for now.
//
// This means that any PIC module smaller than 4GB meets the
// requirements of Small, so Small seems like the best default there.
//
// All symbols bind locally in a non-PIC module, so the choice is less
// obvious. There are two cases:
//
// - When creating an executable, PLTs and copy relocations allow
// us to treat external symbols as part of the executable.
// Any executable smaller than 4GB meets the requirements of Small,
// so that seems like the best default.
//
// - When creating JIT code, stubs will be in range of BRASL if the
// image is less than 4GB in size. GOT entries will likewise be
// in range of LARL. However, the JIT environment has no equivalent
// of copy relocs, so locally-binding data symbols might not be in
// the range of LARL. We need the Medium model in that case.
if (CM == CodeModel::Default)
CM = CodeModel::Small;
else if (CM == CodeModel::JITDefault)
CM = RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium;
}
static MCInstPrinter *createSystemZMCInstPrinter(const Triple &T,
unsigned SyntaxVariant,
const MCAsmInfo &MAI,
@ -223,10 +186,6 @@ extern "C" void LLVMInitializeSystemZTargetMC() {
TargetRegistry::RegisterMCAsmInfo(getTheSystemZTarget(),
createSystemZMCAsmInfo);
// Register the adjustCodeGenOpts.
TargetRegistry::registerMCAdjustCodeGenOpts(getTheSystemZTarget(),
adjustCodeGenOpts);
// Register the MCCodeEmitter.
TargetRegistry::RegisterMCCodeEmitter(getTheSystemZTarget(),
createSystemZMCCodeEmitter);

48
lib/Target/SystemZ/SystemZTargetMachine.cpp
View File

@ -99,14 +99,54 @@ static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
return *RM;
}
// For SystemZ we define the models as follows:
//
// Small: BRASL can call any function and will use a stub if necessary.
// Locally-binding symbols will always be in range of LARL.
//
// Medium: BRASL can call any function and will use a stub if necessary.
// GOT slots and locally-defined text will always be in range
// of LARL, but other symbols might not be.
//
// Large: Equivalent to Medium for now.
//
// Kernel: Equivalent to Medium for now.
//
// This means that any PIC module smaller than 4GB meets the
// requirements of Small, so Small seems like the best default there.
//
// All symbols bind locally in a non-PIC module, so the choice is less
// obvious. There are two cases:
//
// - When creating an executable, PLTs and copy relocations allow
// us to treat external symbols as part of the executable.
// Any executable smaller than 4GB meets the requirements of Small,
// so that seems like the best default.
//
// - When creating JIT code, stubs will be in range of BRASL if the
// image is less than 4GB in size. GOT entries will likewise be
// in range of LARL. However, the JIT environment has no equivalent
// of copy relocs, so locally-binding data symbols might not be in
// the range of LARL. We need the Medium model in that case.
static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM,
Reloc::Model RM, bool JIT) {
if (CM)
return *CM;
if (JIT)
return RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium;
return CodeModel::Small;
}
SystemZTargetMachine::SystemZTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
CodeModel::Model CM,
CodeGenOpt::Level OL)
: LLVMTargetMachine(T, computeDataLayout(TT, CPU, FS), TT, CPU, FS, Options,
getEffectiveRelocModel(RM), CM, OL),
Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: LLVMTargetMachine(
T, computeDataLayout(TT, CPU, FS), TT, CPU, FS, Options,
getEffectiveRelocModel(RM),
getEffectiveCodeModel(CM, getEffectiveRelocModel(RM), JIT), OL),
TLOF(llvm::make_unique<TargetLoweringObjectFileELF>()),
Subtarget(TT, CPU, FS, *this) {
initAsmInfo();

4
lib/Target/SystemZ/SystemZTargetMachine.h
View File

@ -32,8 +32,8 @@ class SystemZTargetMachine : public LLVMTargetMachine {
public:
SystemZTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT);
~SystemZTargetMachine() override;
const SystemZSubtarget *getSubtargetImpl() const { return &Subtarget; }

7
lib/Target/TargetMachineC.cpp
View File

@ -119,7 +119,8 @@ LLVMTargetMachineRef LLVMCreateTargetMachine(LLVMTargetRef T,
break;
}
CodeModel::Model CM = unwrap(CodeModel);
bool JIT;
Optional<CodeModel::Model> CM = unwrap(CodeModel, JIT);
CodeGenOpt::Level OL;
switch (Level) {
@ -138,8 +139,8 @@ LLVMTargetMachineRef LLVMCreateTargetMachine(LLVMTargetRef T,
}
TargetOptions opt;
return wrap(unwrap(T)->createTargetMachine(Triple, CPU, Features, opt, RM,
CM, OL));
return wrap(unwrap(T)->createTargetMachine(Triple, CPU, Features, opt, RM, CM,
OL, JIT));
}
void LLVMDisposeTargetMachine(LLVMTargetMachineRef T) { delete unwrap(T); }

15
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
View File

@ -198,18 +198,6 @@ static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI,
return MAI;
}
static void adjustCodeGenOpts(const Triple &TT, Reloc::Model RM,
CodeModel::Model &CM) {
bool is64Bit = TT.getArch() == Triple::x86_64;
// For static codegen, if we're not already set, use Small codegen.
if (CM == CodeModel::Default)
CM = CodeModel::Small;
else if (CM == CodeModel::JITDefault)
// 64-bit JIT places everything in the same buffer except external funcs.
CM = is64Bit ? CodeModel::Large : CodeModel::Small;
}
static MCInstPrinter *createX86MCInstPrinter(const Triple &T,
unsigned SyntaxVariant,
const MCAsmInfo &MAI,
@ -238,9 +226,6 @@ extern "C" void LLVMInitializeX86TargetMC() {
// Register the MC asm info.
RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo);
// Register the MC codegen info.
RegisterMCAdjustCodeGenOptsFn Y(*T, adjustCodeGenOpts);
// Register the MC instruction info.
TargetRegistry::RegisterMCInstrInfo(*T, createX86MCInstrInfo);

18
lib/Target/X86/X86TargetMachine.cpp
View File

@ -181,15 +181,27 @@ static Reloc::Model getEffectiveRelocModel(const Triple &TT,
return *RM;
}
static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM,
bool JIT, bool Is64Bit) {
if (CM)
return *CM;
if (JIT)
return Is64Bit ? CodeModel::Large : CodeModel::Small;
return CodeModel::Small;
}
/// Create an X86 target.
///
X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
CodeModel::Model CM, CodeGenOpt::Level OL)
: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
getEffectiveRelocModel(TT, RM), CM, OL),
Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: LLVMTargetMachine(
T, computeDataLayout(TT), TT, CPU, FS, Options,
getEffectiveRelocModel(TT, RM),
getEffectiveCodeModel(CM, JIT, TT.getArch() == Triple::x86_64), OL),
TLOF(createTLOF(getTargetTriple())) {
// Windows stack unwinder gets confused when execution flow "falls through"
// after a call to 'noreturn' function.

4
lib/Target/X86/X86TargetMachine.h
View File

@ -35,8 +35,8 @@ class X86TargetMachine final : public LLVMTargetMachine {
public:
X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT);
~X86TargetMachine() override;
const X86Subtarget *getSubtargetImpl(const Function &F) const override;

13
lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp
View File

@ -65,15 +65,6 @@ static MCAsmInfo *createXCoreMCAsmInfo(const MCRegisterInfo &MRI,
return MAI;
}
static void adjustCodeGenOpts(const Triple &TT, Reloc::Model RM,
CodeModel::Model &CM) {
if (CM == CodeModel::Default) {
CM = CodeModel::Small;
}
if (CM != CodeModel::Small && CM != CodeModel::Large)
report_fatal_error("Target only supports CodeModel Small or Large");
}
static MCInstPrinter *createXCoreMCInstPrinter(const Triple &T,
unsigned SyntaxVariant,
const MCAsmInfo &MAI,
@ -134,10 +125,6 @@ extern "C" void LLVMInitializeXCoreTargetMC() {
// Register the MC asm info.
RegisterMCAsmInfoFn X(getTheXCoreTarget(), createXCoreMCAsmInfo);
// Register the MC codegen info.
TargetRegistry::registerMCAdjustCodeGenOpts(getTheXCoreTarget(),
adjustCodeGenOpts);
// Register the MC instruction info.
TargetRegistry::RegisterMCInstrInfo(getTheXCoreTarget(),
createXCoreMCInstrInfo);

16
lib/Target/XCore/XCoreTargetMachine.cpp
View File

@ -31,17 +31,27 @@ static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
return *RM;
}
static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
if (CM) {
if (*CM != CodeModel::Small && *CM != CodeModel::Large)
report_fatal_error("Target only supports CodeModel Small or Large");
return *CM;
}
return CodeModel::Small;
}
/// Create an ILP32 architecture model
///
XCoreTargetMachine::XCoreTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
CodeModel::Model CM,
CodeGenOpt::Level OL)
Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: LLVMTargetMachine(
T, "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32-f64:32-a:0:32-n32",
TT, CPU, FS, Options, getEffectiveRelocModel(RM), CM, OL),
TT, CPU, FS, Options, getEffectiveRelocModel(RM),
getEffectiveCodeModel(CM), OL),
TLOF(llvm::make_unique<XCoreTargetObjectFile>()),
Subtarget(TT, CPU, FS, *this) {
initAsmInfo();

4
lib/Target/XCore/XCoreTargetMachine.h
View File

@ -31,8 +31,8 @@ class XCoreTargetMachine : public LLVMTargetMachine {
public:
XCoreTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT);
~XCoreTargetMachine() override;
const XCoreSubtarget *getSubtargetImpl() const { return &Subtarget; }

2
test/CodeGen/ARM/legalize-unaligned-load.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -O3 -code-model=default -mtriple=armv7l-unknown-linux-gnueabihf -mcpu=generic %s -o - | FileCheck %s
; RUN: llc -O3 -mtriple=armv7l-unknown-linux-gnueabihf -mcpu=generic %s -o - | FileCheck %s
; Check that we respect the existing chain between loads and stores when we
; legalize unaligned loads.
; Test case from PR24669.

2
test/CodeGen/XCore/codemodel.ll
View File

@ -4,7 +4,7 @@
; BAD_CM: Target only supports CodeModel Small or Large
; RUN: llc < %s -march=xcore -code-model=default | FileCheck %s
; RUN: llc < %s -march=xcore | FileCheck %s
; RUN: llc < %s -march=xcore -code-model=small | FileCheck %s
; RUN: llc < %s -march=xcore -code-model=large | FileCheck %s -check-prefix=LARGE

6
tools/llc/llc.cpp
View File

@ -448,9 +448,9 @@ static int compileModule(char **argv, LLVMContext &Context) {
Options.MCOptions.IASSearchPaths = IncludeDirs;
Options.MCOptions.SplitDwarfFile = SplitDwarfFile;
std::unique_ptr<TargetMachine> Target(
TheTarget->createTargetMachine(TheTriple.getTriple(), CPUStr, FeaturesStr,
Options, getRelocModel(), CMModel, OLvl));
std::unique_ptr<TargetMachine> Target(TheTarget->createTargetMachine(
TheTriple.getTriple(), CPUStr, FeaturesStr, Options, getRelocModel(),
getCodeModel(), OLvl));
assert(Target && "Could not allocate target machine!");

60
tools/lli/lli.cpp
View File

@ -15,20 +15,21 @@
#include "OrcLazyJIT.h"
#include "RemoteJITUtils.h"
#include "llvm/IR/LLVMContext.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/Triple.h"
#include "llvm/Bitcode/BitcodeReader.h"
#include "llvm/CodeGen/CommandFlags.h"
#include "llvm/CodeGen/LinkAllCodegenComponents.h"
#include "llvm/ExecutionEngine/GenericValue.h"
#include "llvm/ExecutionEngine/Interpreter.h"
#include "llvm/ExecutionEngine/JITEventListener.h"
#include "llvm/ExecutionEngine/MCJIT.h"
#include "llvm/ExecutionEngine/ObjectCache.h"
#include "llvm/ExecutionEngine/Orc/OrcRemoteTargetClient.h"
#include "llvm/ExecutionEngine/OrcMCJITReplacement.h"
#include "llvm/ExecutionEngine/SectionMemoryManager.h"
#include "llvm/ExecutionEngine/Orc/OrcRemoteTargetClient.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/LLVMContext.h"
#include "llvm/IR/Module.h"
#include "llvm/IR/Type.h"
#include "llvm/IR/TypeBuilder.h"
@ -123,22 +124,6 @@ namespace {
cl::opt<std::string>
TargetTriple("mtriple", cl::desc("Override target triple for module"));
cl::opt<std::string>
MArch("march",
cl::desc("Architecture to generate assembly for (see --version)"));
cl::opt<std::string>
MCPU("mcpu",
cl::desc("Target a specific cpu type (-mcpu=help for details)"),
cl::value_desc("cpu-name"),
cl::init(""));
cl::list<std::string>
MAttrs("mattr",
cl::CommaSeparated,
cl::desc("Target specific attributes (-mattr=help for details)"),
cl::value_desc("a1,+a2,-a3,..."));
cl::opt<std::string>
EntryFunc("entry-function",
cl::desc("Specify the entry function (default = 'main') "
@ -186,47 +171,11 @@ namespace {
cl::desc("Disable JIT lazy compilation"),
cl::init(false));
cl::opt<Reloc::Model> RelocModel(
"relocation-model", cl::desc("Choose relocation model"),
cl::values(
clEnumValN(Reloc::Static, "static", "Non-relocatable code"),
clEnumValN(Reloc::PIC_, "pic",
"Fully relocatable, position independent code"),
clEnumValN(Reloc::DynamicNoPIC, "dynamic-no-pic",
"Relocatable external references, non-relocatable code")));
cl::opt<llvm::CodeModel::Model>
CMModel("code-model",
cl::desc("Choose code model"),
cl::init(CodeModel::JITDefault),
cl::values(clEnumValN(CodeModel::JITDefault, "default",
"Target default JIT code model"),
clEnumValN(CodeModel::Small, "small",
"Small code model"),
clEnumValN(CodeModel::Kernel, "kernel",
"Kernel code model"),
clEnumValN(CodeModel::Medium, "medium",
"Medium code model"),
clEnumValN(CodeModel::Large, "large",
"Large code model")));
cl::opt<bool>
GenerateSoftFloatCalls("soft-float",
cl::desc("Generate software floating point library calls"),
cl::init(false));
cl::opt<llvm::FloatABI::ABIType>
FloatABIForCalls("float-abi",
cl::desc("Choose float ABI type"),
cl::init(FloatABI::Default),
cl::values(
clEnumValN(FloatABI::Default, "default",
"Target default float ABI type"),
clEnumValN(FloatABI::Soft, "soft",
"Soft float ABI (implied by -soft-float)"),
clEnumValN(FloatABI::Hard, "hard",
"Hard float ABI (uses FP registers)")));
ExitOnError ExitOnErr;
}
@ -433,7 +382,8 @@ int main(int argc, char **argv, char * const *envp) {
builder.setMAttrs(MAttrs);
if (RelocModel.getNumOccurrences())
builder.setRelocationModel(RelocModel);
builder.setCodeModel(CMModel);
if (CMModel.getNumOccurrences())
builder.setCodeModel(CMModel);
builder.setErrorStr(&ErrorMsg);
builder.setEngineKind(ForceInterpreter
? EngineKind::Interpreter

2
tools/llvm-lto2/llvm-lto2.cpp
View File

@ -197,7 +197,7 @@ static int run(int argc, char **argv) {
Conf.MAttrs = MAttrs;
if (auto RM = getRelocModel())
Conf.RelocModel = *RM;
Conf.CodeModel = CMModel;
Conf.CodeModel = getCodeModel();
Conf.DebugPassManager = DebugPassManager;

2
tools/opt/opt.cpp
View File

@ -349,7 +349,7 @@ static TargetMachine* GetTargetMachine(Triple TheTriple, StringRef CPUStr,
return TheTarget->createTargetMachine(TheTriple.getTriple(), CPUStr,
FeaturesStr, Options, getRelocModel(),
CMModel, GetCodeGenOptLevel());
getCodeModel(), GetCodeGenOptLevel());
}
#ifdef LINK_POLLY_INTO_TOOLS

10
unittests/ExecutionEngine/MCJIT/MCJITTestBase.h
View File

@ -278,14 +278,9 @@ protected:
class MCJITTestBase : public MCJITTestAPICommon, public TrivialModuleBuilder {
protected:
MCJITTestBase()
: TrivialModuleBuilder(HostTriple)
, OptLevel(CodeGenOpt::None)
, CodeModel(CodeModel::Default)
, MArch("")
, MM(new SectionMemoryManager)
{
: TrivialModuleBuilder(HostTriple), OptLevel(CodeGenOpt::None),
CodeModel(CodeModel::Small), MArch(""), MM(new SectionMemoryManager) {
// The architectures below are known to be compatible with MCJIT as they
// are copied from test/ExecutionEngine/MCJIT/lit.local.cfg and should be
// kept in sync.
@ -320,7 +315,6 @@ protected:
.setMCJITMemoryManager(std::move(MM))
.setErrorStr(&Error)
.setOptLevel(CodeGenOpt::None)
.setCodeModel(CodeModel::JITDefault)
.setMArch(MArch)
.setMCPU(sys::getHostCPUName())
//.setMAttrs(MAttrs)

5
unittests/MI/LiveIntervalTest.cpp
View File

@ -45,9 +45,8 @@ std::unique_ptr<TargetMachine> createTargetMachine() {
return nullptr;
TargetOptions Options;
return std::unique_ptr<TargetMachine>(
T->createTargetMachine("AMDGPU", "", "", Options, None,
CodeModel::Default, CodeGenOpt::Aggressive));
return std::unique_ptr<TargetMachine>(T->createTargetMachine(
"AMDGPU", "", "", Options, None, None, CodeGenOpt::Aggressive));
}
std::unique_ptr<Module> parseMIR(LLVMContext &Context,

5
unittests/Target/AArch64/InstSizes.cpp
View File

@ -22,9 +22,8 @@ std::unique_ptr<TargetMachine> createTargetMachine() {
std::string Error;
const Target *TheTarget = TargetRegistry::lookupTarget(TT, Error);
return std::unique_ptr<TargetMachine>(
TheTarget->createTargetMachine(TT, CPU, FS, TargetOptions(), None,
CodeModel::Default, CodeGenOpt::Default));
return std::unique_ptr<TargetMachine>(TheTarget->createTargetMachine(
TT, CPU, FS, TargetOptions(), None, None, CodeGenOpt::Default));
}
std::unique_ptr<AArch64InstrInfo> createInstrInfo(TargetMachine *TM) {