1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-19 11:02:59 +02:00

Resolving MSVC warnings about switch statements with a default label, but no case labels. No functional changes intended.

llvm-svn: 209126
This commit is contained in:
Aaron Ballman 2014-05-19 14:29:04 +00:00
parent 337b997df4
commit f2386ff79f
2 changed files with 6 additions and 11 deletions

View File

@ -827,14 +827,11 @@ bool ARM64InstrInfo::optimizeCompareInstr(
/// Return true if this is this instruction has a non-zero immediate /// Return true if this is this instruction has a non-zero immediate
bool ARM64InstrInfo::hasNonZeroImm(const MachineInstr *MI) const { bool ARM64InstrInfo::hasNonZeroImm(const MachineInstr *MI) const {
switch (MI->getOpcode()) {
default:
if (MI->getOperand(3).isImm()) { if (MI->getOperand(3).isImm()) {
unsigned val = MI->getOperand(3).getImm(); unsigned val = MI->getOperand(3).getImm();
return (val != 0); return (val != 0);
} }
break;
}
return false; return false;
} }

View File

@ -37,10 +37,8 @@ AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx, const AMDGPUSubtarget &st):
{ } { }
enum AMDGPUMCInstLower::SISubtarget enum AMDGPUMCInstLower::SISubtarget
AMDGPUMCInstLower::AMDGPUSubtargetToSISubtarget(unsigned Gen) const { AMDGPUMCInstLower::AMDGPUSubtargetToSISubtarget(unsigned) const {
switch (Gen) { return AMDGPUMCInstLower::SI;
default: return AMDGPUMCInstLower::SI;
}
} }
unsigned AMDGPUMCInstLower::getMCOpcode(unsigned MIOpcode) const { unsigned AMDGPUMCInstLower::getMCOpcode(unsigned MIOpcode) const {