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https://github.com/RPCS3/llvm-mirror.git
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[MIPS GlobalISel] Select sub
Lower G_USUBO and G_USUBE. Add narrowScalar for G_SUB. Legalize and select G_SUB for MIPS 32. Differential Revision: https://reviews.llvm.org/D53416 llvm-svn: 352351
This commit is contained in:
Petar Avramovic
parent
a34c28f735
commit
f2aa5201c3
@ -343,6 +343,38 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_SUB: {
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// FIXME: add support for when SizeOp0 isn't an exact multiple of
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// NarrowSize.
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if (SizeOp0 % NarrowSize != 0)
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return UnableToLegalize;
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int NumParts = SizeOp0 / NarrowTy.getSizeInBits();
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SmallVector<unsigned, 2> Src1Regs, Src2Regs, DstRegs;
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extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
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extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
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unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
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unsigned BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
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MIRBuilder.buildInstr(TargetOpcode::G_USUBO, {DstReg, BorrowOut},
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{Src1Regs[0], Src2Regs[0]});
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DstRegs.push_back(DstReg);
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unsigned BorrowIn = BorrowOut;
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for (int i = 1; i < NumParts; ++i) {
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DstReg = MRI.createGenericVirtualRegister(NarrowTy);
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BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
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MIRBuilder.buildInstr(TargetOpcode::G_USUBE, {DstReg, BorrowOut},
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{Src1Regs[i], Src2Regs[i], BorrowIn});
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DstRegs.push_back(DstReg);
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BorrowIn = BorrowOut;
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}
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MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_MUL:
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return narrowScalarMul(MI, TypeIdx, NarrowTy);
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case TargetOpcode::G_EXTRACT: {
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@ -1242,6 +1274,40 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
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MI.eraseFromParent();
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return Legalized;
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}
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case G_USUBO: {
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unsigned Res = MI.getOperand(0).getReg();
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unsigned BorrowOut = MI.getOperand(1).getReg();
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unsigned LHS = MI.getOperand(2).getReg();
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unsigned RHS = MI.getOperand(3).getReg();
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MIRBuilder.buildSub(Res, LHS, RHS);
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MIRBuilder.buildICmp(CmpInst::ICMP_ULT, BorrowOut, LHS, RHS);
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MI.eraseFromParent();
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return Legalized;
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}
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case G_USUBE: {
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unsigned Res = MI.getOperand(0).getReg();
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unsigned BorrowOut = MI.getOperand(1).getReg();
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unsigned LHS = MI.getOperand(2).getReg();
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unsigned RHS = MI.getOperand(3).getReg();
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unsigned BorrowIn = MI.getOperand(4).getReg();
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unsigned TmpRes = MRI.createGenericVirtualRegister(Ty);
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unsigned ZExtBorrowIn = MRI.createGenericVirtualRegister(Ty);
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unsigned LHS_EQ_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1));
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unsigned LHS_ULT_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1));
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MIRBuilder.buildSub(TmpRes, LHS, RHS);
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MIRBuilder.buildZExt(ZExtBorrowIn, BorrowIn);
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MIRBuilder.buildSub(Res, TmpRes, ZExtBorrowIn);
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MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LHS_EQ_RHS, LHS, RHS);
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MIRBuilder.buildICmp(CmpInst::ICMP_ULT, LHS_ULT_RHS, LHS, RHS);
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MIRBuilder.buildSelect(BorrowOut, LHS_EQ_RHS, BorrowIn, LHS_ULT_RHS);
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MI.eraseFromParent();
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return Legalized;
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}
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}
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}
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@ -24,11 +24,11 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
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const LLT s64 = LLT::scalar(64);
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const LLT p0 = LLT::pointer(0, 32);
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getActionDefinitionsBuilder(G_ADD)
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getActionDefinitionsBuilder({G_ADD, G_SUB})
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.legalFor({s32})
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.clampScalar(0, s32, s32);
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getActionDefinitionsBuilder(G_UADDE)
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getActionDefinitionsBuilder({G_UADDE, G_USUBO, G_USUBE})
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.lowerFor({{s32, s1}});
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getActionDefinitionsBuilder({G_LOAD, G_STORE})
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@ -82,7 +82,9 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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const ValueMapping *OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
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switch (Opc) {
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case G_TRUNC:
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case G_ADD:
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case G_SUB:
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case G_LOAD:
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case G_STORE:
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case G_ZEXTLOAD:
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31
test/CodeGen/Mips/GlobalISel/instruction-select/sub.mir
Normal file
31
test/CodeGen/Mips/GlobalISel/instruction-select/sub.mir
Normal file
@ -0,0 +1,31 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
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--- |
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define void @sub_i32(i32 %x, i32 %y) {entry: ret void}
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...
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---
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name: sub_i32
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: sub_i32
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
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; MIPS32: [[SUBu:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[COPY1]]
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; MIPS32: $v0 = COPY [[SUBu]]
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; MIPS32: RetRA implicit $v0
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%0:gprb(s32) = COPY $a0
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%1:gprb(s32) = COPY $a1
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%2:gprb(s32) = G_SUB %0, %1
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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342
test/CodeGen/Mips/GlobalISel/legalizer/sub.mir
Normal file
342
test/CodeGen/Mips/GlobalISel/legalizer/sub.mir
Normal file
@ -0,0 +1,342 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
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--- |
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define void @sub_i32() {entry: ret void}
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define void @sub_i8_sext() {entry: ret void}
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define void @sub_i8_zext() {entry: ret void}
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define void @sub_i8_aext() {entry: ret void}
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define void @sub_i16_sext() {entry: ret void}
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define void @sub_i16_zext() {entry: ret void}
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define void @sub_i16_aext() {entry: ret void}
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define void @sub_i64() {entry: ret void}
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define void @sub_i128() {entry: ret void}
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...
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---
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name: sub_i32
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: sub_i32
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]]
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; MIPS32: $v0 = COPY [[SUB]](s32)
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; MIPS32: RetRA implicit $v0
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%0:_(s32) = COPY $a0
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%1:_(s32) = COPY $a1
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%2:_(s32) = G_SUB %0, %1
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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---
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name: sub_i8_sext
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: sub_i8_sext
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
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; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]]
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
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; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
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; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]]
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; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
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; MIPS32: $v0 = COPY [[ASHR]](s32)
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; MIPS32: RetRA implicit $v0
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%2:_(s32) = COPY $a0
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%0:_(s8) = G_TRUNC %2(s32)
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%3:_(s32) = COPY $a1
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%1:_(s8) = G_TRUNC %3(s32)
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%4:_(s8) = G_SUB %1, %0
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%5:_(s32) = G_SEXT %4(s8)
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$v0 = COPY %5(s32)
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RetRA implicit $v0
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...
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---
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name: sub_i8_zext
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: sub_i8_zext
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
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; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]]
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
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; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
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; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
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; MIPS32: $v0 = COPY [[AND]](s32)
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; MIPS32: RetRA implicit $v0
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%2:_(s32) = COPY $a0
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%0:_(s8) = G_TRUNC %2(s32)
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%3:_(s32) = COPY $a1
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%1:_(s8) = G_TRUNC %3(s32)
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%4:_(s8) = G_SUB %1, %0
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%5:_(s32) = G_ZEXT %4(s8)
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$v0 = COPY %5(s32)
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RetRA implicit $v0
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...
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---
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name: sub_i8_aext
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: sub_i8_aext
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
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; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]]
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; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
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; MIPS32: $v0 = COPY [[COPY4]](s32)
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; MIPS32: RetRA implicit $v0
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%2:_(s32) = COPY $a0
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%0:_(s8) = G_TRUNC %2(s32)
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%3:_(s32) = COPY $a1
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%1:_(s8) = G_TRUNC %3(s32)
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%4:_(s8) = G_SUB %1, %0
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%5:_(s32) = G_ANYEXT %4(s8)
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$v0 = COPY %5(s32)
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RetRA implicit $v0
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...
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---
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name: sub_i16_sext
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: sub_i16_sext
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
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; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]]
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
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; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]]
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; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
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; MIPS32: $v0 = COPY [[ASHR]](s32)
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; MIPS32: RetRA implicit $v0
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%2:_(s32) = COPY $a0
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%0:_(s16) = G_TRUNC %2(s32)
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%3:_(s32) = COPY $a1
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%1:_(s16) = G_TRUNC %3(s32)
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%4:_(s16) = G_SUB %1, %0
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%5:_(s32) = G_SEXT %4(s16)
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$v0 = COPY %5(s32)
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RetRA implicit $v0
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...
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---
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name: sub_i16_zext
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: sub_i16_zext
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
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; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]]
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
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; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
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; MIPS32: $v0 = COPY [[AND]](s32)
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; MIPS32: RetRA implicit $v0
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%2:_(s32) = COPY $a0
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%0:_(s16) = G_TRUNC %2(s32)
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%3:_(s32) = COPY $a1
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%1:_(s16) = G_TRUNC %3(s32)
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%4:_(s16) = G_SUB %1, %0
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%5:_(s32) = G_ZEXT %4(s16)
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$v0 = COPY %5(s32)
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RetRA implicit $v0
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...
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---
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name: sub_i16_aext
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: sub_i16_aext
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
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; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]]
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; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
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; MIPS32: $v0 = COPY [[COPY4]](s32)
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; MIPS32: RetRA implicit $v0
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%2:_(s32) = COPY $a0
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%0:_(s16) = G_TRUNC %2(s32)
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%3:_(s32) = COPY $a1
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%1:_(s16) = G_TRUNC %3(s32)
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%4:_(s16) = G_SUB %1, %0
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%5:_(s32) = G_ANYEXT %4(s16)
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$v0 = COPY %5(s32)
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RetRA implicit $v0
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...
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---
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name: sub_i64
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1, $a2, $a3
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; MIPS32-LABEL: name: sub_i64
|
||||
; MIPS32: liveins: $a0, $a1, $a2, $a3
|
||||
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
|
||||
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
|
||||
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
|
||||
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
|
||||
; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY3]], [[COPY1]]
|
||||
; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY3]](s32), [[COPY1]]
|
||||
; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY]]
|
||||
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
|
||||
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
|
||||
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
|
||||
; MIPS32: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[AND]]
|
||||
; MIPS32: $v0 = COPY [[SUB2]](s32)
|
||||
; MIPS32: $v1 = COPY [[SUB]](s32)
|
||||
; MIPS32: RetRA implicit $v0, implicit $v1
|
||||
%2:_(s32) = COPY $a0
|
||||
%3:_(s32) = COPY $a1
|
||||
%0:_(s64) = G_MERGE_VALUES %3(s32), %2(s32)
|
||||
%4:_(s32) = COPY $a2
|
||||
%5:_(s32) = COPY $a3
|
||||
%1:_(s64) = G_MERGE_VALUES %5(s32), %4(s32)
|
||||
%6:_(s64) = G_SUB %1, %0
|
||||
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
|
||||
$v0 = COPY %8(s32)
|
||||
$v1 = COPY %7(s32)
|
||||
RetRA implicit $v0, implicit $v1
|
||||
|
||||
...
|
||||
---
|
||||
name: sub_i128
|
||||
alignment: 2
|
||||
tracksRegLiveness: true
|
||||
fixedStack:
|
||||
- { id: 0, offset: 28, size: 4, alignment: 4, stack-id: 0, isImmutable: true }
|
||||
- { id: 1, offset: 24, size: 4, alignment: 8, stack-id: 0, isImmutable: true }
|
||||
- { id: 2, offset: 20, size: 4, alignment: 4, stack-id: 0, isImmutable: true }
|
||||
- { id: 3, offset: 16, size: 4, alignment: 8, stack-id: 0, isImmutable: true }
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0, $a1, $a2, $a3
|
||||
|
||||
; MIPS32-LABEL: name: sub_i128
|
||||
; MIPS32: liveins: $a0, $a1, $a2, $a3
|
||||
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
|
||||
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
|
||||
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
|
||||
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
|
||||
; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
|
||||
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 0)
|
||||
; MIPS32: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
|
||||
; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load 4 from %fixed-stack.1, align 0)
|
||||
; MIPS32: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
|
||||
; MIPS32: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p0) :: (load 4 from %fixed-stack.2, align 0)
|
||||
; MIPS32: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
|
||||
; MIPS32: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p0) :: (load 4 from %fixed-stack.3, align 0)
|
||||
; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[LOAD]], [[COPY]]
|
||||
; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[LOAD]](s32), [[COPY]]
|
||||
; MIPS32: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[LOAD1]], [[COPY1]]
|
||||
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
|
||||
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
|
||||
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
|
||||
; MIPS32: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[AND]]
|
||||
; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[LOAD1]](s32), [[COPY1]]
|
||||
; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[LOAD1]](s32), [[COPY1]]
|
||||
; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
|
||||
; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
|
||||
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
|
||||
; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
|
||||
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
|
||||
; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), [[COPY5]], [[COPY6]]
|
||||
; MIPS32: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[SELECT]](s32)
|
||||
; MIPS32: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[LOAD2]], [[COPY2]]
|
||||
; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
|
||||
; MIPS32: [[COPY8:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
|
||||
; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C2]]
|
||||
; MIPS32: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SUB3]], [[AND2]]
|
||||
; MIPS32: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[LOAD2]](s32), [[COPY2]]
|
||||
; MIPS32: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[LOAD2]](s32), [[COPY2]]
|
||||
; MIPS32: [[COPY9:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
|
||||
; MIPS32: [[COPY10:%[0-9]+]]:_(s32) = COPY [[ICMP4]](s32)
|
||||
; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
|
||||
; MIPS32: [[COPY11:%[0-9]+]]:_(s32) = COPY [[ICMP3]](s32)
|
||||
; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
|
||||
; MIPS32: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND3]](s32), [[COPY9]], [[COPY10]]
|
||||
; MIPS32: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[LOAD3]], [[COPY3]]
|
||||
; MIPS32: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
|
||||
; MIPS32: [[COPY12:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
|
||||
; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C4]]
|
||||
; MIPS32: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB5]], [[AND4]]
|
||||
; MIPS32: $v0 = COPY [[SUB]](s32)
|
||||
; MIPS32: $v1 = COPY [[SUB2]](s32)
|
||||
; MIPS32: $a0 = COPY [[SUB4]](s32)
|
||||
; MIPS32: $a1 = COPY [[SUB6]](s32)
|
||||
; MIPS32: RetRA implicit $v0, implicit $v1, implicit $a0, implicit $a1
|
||||
%2:_(s32) = COPY $a0
|
||||
%3:_(s32) = COPY $a1
|
||||
%4:_(s32) = COPY $a2
|
||||
%5:_(s32) = COPY $a3
|
||||
%0:_(s128) = G_MERGE_VALUES %2(s32), %3(s32), %4(s32), %5(s32)
|
||||
%10:_(p0) = G_FRAME_INDEX %fixed-stack.3
|
||||
%6:_(s32) = G_LOAD %10(p0) :: (load 4 from %fixed-stack.3, align 0)
|
||||
%11:_(p0) = G_FRAME_INDEX %fixed-stack.2
|
||||
%7:_(s32) = G_LOAD %11(p0) :: (load 4 from %fixed-stack.2, align 0)
|
||||
%12:_(p0) = G_FRAME_INDEX %fixed-stack.1
|
||||
%8:_(s32) = G_LOAD %12(p0) :: (load 4 from %fixed-stack.1, align 0)
|
||||
%13:_(p0) = G_FRAME_INDEX %fixed-stack.0
|
||||
%9:_(s32) = G_LOAD %13(p0) :: (load 4 from %fixed-stack.0, align 0)
|
||||
%1:_(s128) = G_MERGE_VALUES %6(s32), %7(s32), %8(s32), %9(s32)
|
||||
%14:_(s128) = G_SUB %1, %0
|
||||
%15:_(s32), %16:_(s32), %17:_(s32), %18:_(s32) = G_UNMERGE_VALUES %14(s128)
|
||||
$v0 = COPY %15(s32)
|
||||
$v1 = COPY %16(s32)
|
||||
$a0 = COPY %17(s32)
|
||||
$a1 = COPY %18(s32)
|
||||
RetRA implicit $v0, implicit $v1, implicit $a0, implicit $a1
|
||||
|
||||
...
|
||||
158
test/CodeGen/Mips/GlobalISel/llvm-ir/sub.ll
Normal file
158
test/CodeGen/Mips/GlobalISel/llvm-ir/sub.ll
Normal file
@ -0,0 +1,158 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
|
||||
|
||||
define i32 @sub_i32(i32 %x, i32 %y) {
|
||||
; MIPS32-LABEL: sub_i32:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: subu $2, $4, $5
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%z = sub i32 %x, %y
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
define signext i8 @sub_i8_sext(i8 signext %a, i8 signext %b) {
|
||||
; MIPS32-LABEL: sub_i8_sext:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: subu $4, $5, $4
|
||||
; MIPS32-NEXT: sll $4, $4, 24
|
||||
; MIPS32-NEXT: sra $2, $4, 24
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%sub = sub i8 %b, %a
|
||||
ret i8 %sub
|
||||
}
|
||||
|
||||
define zeroext i8 @sub_i8_zext(i8 zeroext %a, i8 zeroext %b) {
|
||||
; MIPS32-LABEL: sub_i8_zext:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: subu $4, $5, $4
|
||||
; MIPS32-NEXT: lui $5, 0
|
||||
; MIPS32-NEXT: ori $5, $5, 255
|
||||
; MIPS32-NEXT: and $2, $4, $5
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%sub = sub i8 %b, %a
|
||||
ret i8 %sub
|
||||
}
|
||||
|
||||
define i8 @sub_i8_aext(i8 %a, i8 %b) {
|
||||
; MIPS32-LABEL: sub_i8_aext:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: subu $2, $5, $4
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%sub = sub i8 %b, %a
|
||||
ret i8 %sub
|
||||
}
|
||||
|
||||
define signext i16 @sub_i16_sext(i16 signext %a, i16 signext %b) {
|
||||
; MIPS32-LABEL: sub_i16_sext:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: subu $4, $5, $4
|
||||
; MIPS32-NEXT: sll $4, $4, 16
|
||||
; MIPS32-NEXT: sra $2, $4, 16
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%sub = sub i16 %b, %a
|
||||
ret i16 %sub
|
||||
}
|
||||
|
||||
define zeroext i16 @sub_i16_zext(i16 zeroext %a, i16 zeroext %b) {
|
||||
; MIPS32-LABEL: sub_i16_zext:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: subu $4, $5, $4
|
||||
; MIPS32-NEXT: lui $5, 0
|
||||
; MIPS32-NEXT: ori $5, $5, 65535
|
||||
; MIPS32-NEXT: and $2, $4, $5
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%sub = sub i16 %b, %a
|
||||
ret i16 %sub
|
||||
}
|
||||
|
||||
define i16 @sub_i16_aext(i16 %a, i16 %b) {
|
||||
; MIPS32-LABEL: sub_i16_aext:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: subu $2, $5, $4
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%sub = sub i16 %b, %a
|
||||
ret i16 %sub
|
||||
}
|
||||
|
||||
define i64 @sub_i64(i64 %a, i64 %b) {
|
||||
; MIPS32-LABEL: sub_i64:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: subu $2, $6, $4
|
||||
; MIPS32-NEXT: sltu $4, $6, $4
|
||||
; MIPS32-NEXT: subu $5, $7, $5
|
||||
; MIPS32-NEXT: lui $6, 0
|
||||
; MIPS32-NEXT: ori $6, $6, 1
|
||||
; MIPS32-NEXT: and $4, $4, $6
|
||||
; MIPS32-NEXT: subu $3, $5, $4
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%sub = sub i64 %b, %a
|
||||
ret i64 %sub
|
||||
}
|
||||
|
||||
define i128 @sub_i128(i128 %a, i128 %b) {
|
||||
; MIPS32-LABEL: sub_i128:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: addiu $1, $sp, 16
|
||||
; MIPS32-NEXT: lw $1, 0($1)
|
||||
; MIPS32-NEXT: addiu $2, $sp, 20
|
||||
; MIPS32-NEXT: lw $2, 0($2)
|
||||
; MIPS32-NEXT: addiu $3, $sp, 24
|
||||
; MIPS32-NEXT: lw $3, 0($3)
|
||||
; MIPS32-NEXT: addiu $8, $sp, 28
|
||||
; MIPS32-NEXT: lw $8, 0($8)
|
||||
; MIPS32-NEXT: subu $9, $1, $4
|
||||
; MIPS32-NEXT: sltu $1, $1, $4
|
||||
; MIPS32-NEXT: subu $4, $2, $5
|
||||
; MIPS32-NEXT: lui $10, 0
|
||||
; MIPS32-NEXT: ori $10, $10, 1
|
||||
; MIPS32-NEXT: and $10, $1, $10
|
||||
; MIPS32-NEXT: subu $4, $4, $10
|
||||
; MIPS32-NEXT: xor $10, $2, $5
|
||||
; MIPS32-NEXT: sltiu $10, $10, 1
|
||||
; MIPS32-NEXT: sltu $2, $2, $5
|
||||
; MIPS32-NEXT: lui $5, 0
|
||||
; MIPS32-NEXT: ori $5, $5, 1
|
||||
; MIPS32-NEXT: and $5, $10, $5
|
||||
; MIPS32-NEXT: movn $2, $1, $5
|
||||
; MIPS32-NEXT: subu $1, $3, $6
|
||||
; MIPS32-NEXT: lui $5, 0
|
||||
; MIPS32-NEXT: ori $5, $5, 1
|
||||
; MIPS32-NEXT: and $5, $2, $5
|
||||
; MIPS32-NEXT: subu $1, $1, $5
|
||||
; MIPS32-NEXT: xor $5, $3, $6
|
||||
; MIPS32-NEXT: sltiu $5, $5, 1
|
||||
; MIPS32-NEXT: sltu $3, $3, $6
|
||||
; MIPS32-NEXT: lui $6, 0
|
||||
; MIPS32-NEXT: ori $6, $6, 1
|
||||
; MIPS32-NEXT: and $5, $5, $6
|
||||
; MIPS32-NEXT: movn $3, $2, $5
|
||||
; MIPS32-NEXT: subu $2, $8, $7
|
||||
; MIPS32-NEXT: lui $5, 0
|
||||
; MIPS32-NEXT: ori $5, $5, 1
|
||||
; MIPS32-NEXT: and $3, $3, $5
|
||||
; MIPS32-NEXT: subu $5, $2, $3
|
||||
; MIPS32-NEXT: move $2, $9
|
||||
; MIPS32-NEXT: move $3, $4
|
||||
; MIPS32-NEXT: move $4, $1
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%sub = sub i128 %b, %a
|
||||
ret i128 %sub
|
||||
}
|
||||
30
test/CodeGen/Mips/GlobalISel/regbankselect/sub.mir
Normal file
30
test/CodeGen/Mips/GlobalISel/regbankselect/sub.mir
Normal file
@ -0,0 +1,30 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
|
||||
--- |
|
||||
|
||||
define void @sub_i32(i32 %x, i32 %y) {entry: ret void}
|
||||
|
||||
...
|
||||
---
|
||||
name: sub_i32
|
||||
alignment: 2
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0.entry:
|
||||
liveins: $a0, $a1
|
||||
|
||||
; MIPS32-LABEL: name: sub_i32
|
||||
; MIPS32: liveins: $a0, $a1
|
||||
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
|
||||
; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
|
||||
; MIPS32: [[SUB:%[0-9]+]]:gprb(s32) = G_SUB [[COPY]], [[COPY1]]
|
||||
; MIPS32: $v0 = COPY [[SUB]](s32)
|
||||
; MIPS32: RetRA implicit $v0
|
||||
%0:_(s32) = COPY $a0
|
||||
%1:_(s32) = COPY $a1
|
||||
%2:_(s32) = G_SUB %0, %1
|
||||
$v0 = COPY %2(s32)
|
||||
RetRA implicit $v0
|
||||
|
||||
...
|
||||
Loading…
Reference in New Issue
Block a user