From f2d53ff2dd2e98d288ecee25b278a2371eefd654 Mon Sep 17 00:00:00 2001 From: Francis Visoiu Mistrih Date: Thu, 18 Jan 2018 14:52:14 +0000 Subject: [PATCH] [CodeGen][NFC] Refactor MachineInstr::print * Handle more cases where the MI is not attached yet * Add similar asserts like in MIRPrinter::print llvm-svn: 322848 --- lib/CodeGen/MachineInstr.cpp | 66 ++++++++++++++++++++++++------------ 1 file changed, 45 insertions(+), 21 deletions(-) diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp index ed1238c121b..2a0ebc607c7 100644 --- a/lib/CodeGen/MachineInstr.cpp +++ b/lib/CodeGen/MachineInstr.cpp @@ -74,6 +74,29 @@ using namespace llvm; +static const MachineFunction *getMFIfAvailable(const MachineInstr &MI) { + if (const MachineBasicBlock *MBB = MI.getParent()) + if (const MachineFunction *MF = MBB->getParent()) + return MF; + return nullptr; +} + +// Try to crawl up to the machine function and get TRI and IntrinsicInfo from +// it. +static void tryToGetTargetInfo(const MachineInstr &MI, + const TargetRegisterInfo *&TRI, + const MachineRegisterInfo *&MRI, + const TargetIntrinsicInfo *&IntrinsicInfo, + const TargetInstrInfo *&TII) { + + if (const MachineFunction *MF = getMFIfAvailable(MI)) { + TRI = MF->getSubtarget().getRegisterInfo(); + MRI = &MF->getRegInfo(); + IntrinsicInfo = MF->getTarget().getIntrinsicInfo(); + TII = MF->getSubtarget().getInstrInfo(); + } +} + void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) { if (MCID->ImplicitDefs) for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; @@ -1209,11 +1232,15 @@ LLVM_DUMP_METHOD void MachineInstr::dump() const { void MachineInstr::print(raw_ostream &OS, bool SkipOpers, bool SkipDebugLoc, const TargetInstrInfo *TII) const { const Module *M = nullptr; - if (const MachineBasicBlock *MBB = getParent()) - if (const MachineFunction *MF = MBB->getParent()) - M = MF->getFunction().getParent(); + const Function *F = nullptr; + if (const MachineFunction *MF = getMFIfAvailable(*this)) { + F = &MF->getFunction(); + M = F->getParent(); + } ModuleSlotTracker MST(M); + if (F) + MST.incorporateFunction(*F); print(OS, MST, SkipOpers, SkipDebugLoc, TII); } @@ -1225,18 +1252,10 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST, const TargetRegisterInfo *TRI = nullptr; const MachineRegisterInfo *MRI = nullptr; const TargetIntrinsicInfo *IntrinsicInfo = nullptr; + tryToGetTargetInfo(*this, TRI, MRI, IntrinsicInfo, TII); - if (const MachineBasicBlock *MBB = getParent()) { - MF = MBB->getParent(); - if (MF) { - MRI = &MF->getRegInfo(); - TRI = MF->getSubtarget().getRegisterInfo(); - if (!TII) - TII = MF->getSubtarget().getInstrInfo(); - IntrinsicInfo = MF->getTarget().getIntrinsicInfo(); - } - } - + if (isCFIInstruction()) + assert(getNumOperands() == 1 && "Expected 1 operand in CFI instruction"); SmallBitVector PrintedTypes(8); bool ShouldPrintRegisterTies = hasComplexRegisterTies(); @@ -1248,18 +1267,23 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST, return findTiedOperandIdx(OpIdx); return 0U; }; + unsigned StartOp = 0; + unsigned e = getNumOperands(); + // Print explicitly defined operands on the left of an assignment syntax. - unsigned StartOp = 0, e = getNumOperands(); - for (; StartOp < e && getOperand(StartOp).isReg() && - getOperand(StartOp).isDef() && !getOperand(StartOp).isImplicit(); - ++StartOp) { + while (StartOp < e) { + const MachineOperand &MO = getOperand(StartOp); + if (!MO.isReg() || !MO.isDef() || MO.isImplicit()) + break; + if (StartOp != 0) OS << ", "; + LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{}; unsigned TiedOperandIdx = getTiedOperandIdx(StartOp); - getOperand(StartOp).print(OS, MST, TypeToPrint, /*PrintDef=*/false, - ShouldPrintRegisterTies, TiedOperandIdx, TRI, - IntrinsicInfo); + MO.print(OS, MST, TypeToPrint, /*PrintDef=*/false, ShouldPrintRegisterTies, + TiedOperandIdx, TRI, IntrinsicInfo); + ++StartOp; } if (StartOp != 0)